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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * ne1_tb\ethernet\shared_ethernet.h |
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16 * SMCS 9118 Ethernet driver implementation. |
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17 * |
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18 */ |
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19 |
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20 |
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21 |
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22 #include "variant.h" |
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23 #include "smcs9118_ethernet.h" |
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24 |
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25 const TUint32 ONE_MSEC = 1000; // in nanoseconds |
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26 const TUint32 TWO_SECONDS = 2000; // in milliseconds |
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27 const TUint32 SMCS9118_MAC_TIMEOUT = 50; |
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28 const TUint32 SMCS9118_MAX_RETRIES = 100; |
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29 |
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30 |
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31 DEthernetPddFactory::DEthernetPddFactory() |
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32 { |
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33 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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34 KPROFILE_PRINT("DEthernetPddFactory::DEthernetPddFactory()"); |
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35 #endif |
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36 iVersion=TVersion(KEthernetMajorVersionNumber, |
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37 KEthernetMinorVersionNumber, |
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38 KEthernetBuildVersionNumber); |
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39 } |
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40 |
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41 TInt DEthernetPddFactory::Install() |
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42 { |
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43 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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44 KPROFILE_PRINT("DEthernetPddFactory::Install()"); |
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45 #endif |
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46 return SetName(&KEthernetPddName); |
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47 } |
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48 |
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49 void DEthernetPddFactory::GetCaps(TDes8& /*aDes*/) const |
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50 /* |
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51 * Return the drivers capabilities. |
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52 */ |
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53 { |
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54 } |
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55 |
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56 |
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57 TInt DEthernetPddFactory::Create(DBase*& aChannel, TInt aUnit, const TDesC8* aInfo, const TVersion& aVer) |
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58 /* |
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59 * Create a Driver for the device. |
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60 */ |
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61 { |
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62 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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63 KPROFILE_PRINT("DEthernetPddFactory::Create()"); |
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64 #endif |
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65 TInt r = Validate(aUnit, aInfo, aVer); |
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66 if (r != KErrNone) |
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67 { |
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68 return r; |
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69 } |
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70 DEthernetPdd* pP = new DEthernetSMCS9118Pdd; |
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71 aChannel = pP; |
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72 if (!pP) |
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73 { |
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74 return KErrNoMemory; |
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75 } |
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76 r = pP->DoCreate(); |
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77 return r; |
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78 } |
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79 |
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80 TInt DEthernetPddFactory::Validate(TInt /*aUnit*/, const TDesC8* /*aInfo*/, const TVersion& aVer) |
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81 /* |
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82 * Validate the requested configuration |
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83 */ |
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84 { |
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85 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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86 KPROFILE_PRINT("DEthernetPddFactory::Validate()"); |
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87 #endif |
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88 |
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89 if (!Kern::QueryVersionSupported(iVersion,aVer)) |
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90 { |
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91 return KErrNotSupported; |
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92 } |
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93 |
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94 return KErrNone; |
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95 } |
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96 |
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97 #ifdef __SMP__ |
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98 TSpinLock DEthernetSMCS9118PddLock(SMCS9118_LOCK_ORDER); |
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99 #endif |
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100 DEthernetSMCS9118Pdd::DEthernetSMCS9118Pdd() |
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101 //Constructor |
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102 :iRxDfc(ServiceRxDfc, this, 1) |
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103 { |
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104 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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105 KPROFILE_PRINT("DEthernetSMCS9118Pdd::DEthernetSMCS9118Pdd()"); |
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106 #endif |
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107 |
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108 #ifdef __SMP__ |
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109 iDriverLock = &DEthernetSMCS9118PddLock; |
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110 #endif |
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111 iReady = EFalse; |
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112 } |
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113 |
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114 DEthernetSMCS9118Pdd::~DEthernetSMCS9118Pdd() |
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115 //Destructor |
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116 { |
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117 |
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118 //cancel any pending DFC requests |
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119 iRxDfc.Cancel(); |
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120 |
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121 // UnRegister the power handler with Symbian Power Framework |
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122 iPowerHandler.RelinquishPower(); |
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123 iPowerHandler.Remove(); |
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124 |
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125 // UnRegister interrupts |
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126 DisableInterrupt(iInterruptId); |
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127 UnbindInterrupt(iInterruptId); |
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128 |
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129 if (iDfcQ) |
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130 iDfcQ->Destroy(); |
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131 } |
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132 |
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133 void DEthernetSMCS9118Pdd::Stop(TStopMode aMode) |
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134 /** |
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135 * Stop receiving frames |
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136 * @param aMode The stop mode |
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137 */ |
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138 { |
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139 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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140 KPROFILE_PRINT("DEthernetSMCS9118Pdd::Stop()"); |
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141 #endif |
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142 |
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143 switch (aMode) |
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144 { |
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145 case EStopNormal: |
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146 case EStopEmergency: |
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147 iReady = EFalse; |
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148 iRxDfc.Cancel(); |
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149 // disable Rx, Tx |
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150 TUint32 status; |
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151 TInt32 err = ReadMac(SMCS9118_MAC_CR, status); |
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152 status &= ~(SMCS9118_MAC_RXEN | SMCS9118_MAC_TXEN | SMCS9118_MAC_RXALL); |
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153 err = WriteMac(SMCS9118_MAC_CR, status); |
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154 // clear any pending interrupts |
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155 Write32(SMCS9118_INT_EN, 0); |
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156 ByteTestDelay(1); |
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157 ClearInterrupt(iInterruptId); |
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158 // turn off the LED |
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159 status = Read32(SMCS9118_GPIO_CFG) & ~SMCS9118_GPIO_LED_EN; |
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160 Write32(SMCS9118_GPIO_CFG, status); |
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161 ByteTestDelay(1); |
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162 |
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163 break; |
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164 } |
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165 } |
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166 |
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167 TInt DEthernetSMCS9118Pdd::Configure(TEthernetConfigV01& /*aConfig*/) |
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168 /** |
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169 * Configure the device |
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170 * Reconfigure the device using the new configuration supplied. |
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171 * This should not change the MAC address. |
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172 * @param aConfig The new configuration |
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173 * @see ValidateConfig() |
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174 * @see MacConfigure() |
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175 * assume iDriverLock not held |
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176 */ |
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177 { |
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178 TUint32 retry; |
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179 TUint32 status; |
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180 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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181 KPROFILE_PRINT("DEthernetSMCS9118Pdd::Configure()"); |
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182 #endif |
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183 |
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184 if ((status = CardSoftReset()) != (TUint32)KErrNone) |
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185 { |
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186 return status; |
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187 } |
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188 |
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189 TInt irq = DriverLock(); |
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190 // disable chip interrupts |
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191 Write32(SMCS9118_INT_EN, 0); |
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192 ByteTestDelay(1); |
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193 Write32(SMCS9118_INT_STS, 0xffffffff); |
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194 ByteTestDelay(2); |
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195 Write32(SMCS9118_FIFO_INT, 0); |
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196 ByteTestDelay(1); |
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197 Write32(SMCS9118_IRQ_CFG, SMCS9118_IRQ_CFG_DEAS|SMCS9118_IRQ_CFG_TYPE); |
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198 ByteTestDelay(3); |
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199 |
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200 // AutoFlowControl setup |
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201 Write32(SMCS9118_AFC_CFG, SMCS9118_AFC_CFG_VAL); |
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202 ByteTestDelay(1); |
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203 |
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204 // TX FIFO setup |
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205 status = Read32(SMCS9118_HW_CFG); |
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206 status |= SMCS9118_TX_FIFO_SZ; |
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207 Write32(SMCS9118_HW_CFG, status); |
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208 ByteTestDelay(1); |
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209 |
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210 // wait for EEPROM load |
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211 retry = SMCS9118_MAX_RETRIES; |
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212 do |
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213 { |
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214 status = Read32(SMCS9118_E2P_CMD); |
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215 if (!(status & SMCS9118_E2P_CMD_BUSY)) |
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216 { |
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217 break; |
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218 } |
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219 Kern::NanoWait(ONE_MSEC); |
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220 } while (--retry); |
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221 if (retry == 0) |
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222 { |
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223 DriverUnlock(irq); |
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224 return KErrGeneral; |
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225 } |
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226 |
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227 // GPIO setup - turn on the LED ! |
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228 Write32(SMCS9118_GPIO_CFG, SMCS9118_GPIO_GPIOBUF|SMCS9118_GPIO_LED_EN); |
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229 ByteTestDelay(1); |
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230 |
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231 // PHY reset |
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232 status = Read32(SMCS9118_PMT_CTRL); |
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233 status |= SMCS9118_PMT_PHY_RST; |
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234 Write32(SMCS9118_PMT_CTRL, status); |
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235 ByteTestDelay(7); |
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236 retry = SMCS9118_MAX_RETRIES; |
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237 do |
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238 { |
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239 status = Read32(SMCS9118_PMT_CTRL); |
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240 if (!(status & SMCS9118_PMT_PHY_RST)) |
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241 { |
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242 break; |
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243 } |
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244 Kern::NanoWait(ONE_MSEC); |
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245 } while (--retry); |
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246 if (retry == 0) |
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247 { |
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248 DriverUnlock(irq); |
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249 return KErrGeneral; |
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250 } |
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251 ByteTestDelay(1); |
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252 |
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253 // Auto negotiate setup |
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254 TInt32 err = ReadPhy(SMCS9118_PHY_AUTONEG_AD, status); |
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255 if (err != KErrNone) |
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256 { |
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257 DriverUnlock(irq); |
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258 return err; |
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259 } |
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260 status |= SMCS9118_PHY_DEF_ANEG; |
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261 err = WritePhy(SMCS9118_PHY_AUTONEG_AD, status); |
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262 if (err != KErrNone) |
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263 { |
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264 DriverUnlock(irq); |
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265 return err; |
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266 } |
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267 |
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268 err = ReadPhy(SMCS9118_PHY_AUTONEG_AD, status); |
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269 if (err != KErrNone) |
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270 { |
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271 DriverUnlock(irq); |
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272 return err; |
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273 } |
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274 |
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275 err = ReadPhy(SMCS9118_PHY_BCR, status); |
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276 if (err != KErrNone) |
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277 { |
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278 DriverUnlock(irq); |
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279 return err; |
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280 } |
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281 status |= (SMCS9118_PHY_ANEG_RESTART|SMCS9118_PHY_ANEG_EN); |
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282 err = WritePhy(SMCS9118_PHY_BCR, status); |
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283 if (err != KErrNone) |
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284 { |
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285 DriverUnlock(irq); |
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286 return err; |
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287 } |
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288 |
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289 // wait for auto negotiation |
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290 DriverUnlock(irq); |
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291 NKern::Sleep(TWO_SECONDS); |
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292 irq = DriverLock(); |
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293 |
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294 err = ReadPhy(SMCS9118_PHY_BSR, status); |
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295 if (err != KErrNone) |
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296 { |
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297 DriverUnlock(irq); |
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298 return err; |
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299 } |
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300 if (!(status & SMCS9118_PHY_ANEG_CMPL)) |
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301 { |
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302 DriverUnlock(irq); |
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303 return KErrGeneral; |
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304 } |
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305 |
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306 // update the config based on what we negotiated |
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307 if (status & (SMCS9118_PHY_100BTX|SMCS9118_PHY_100BTXFD)) |
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308 { |
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309 iDefaultConfig.iEthSpeed = KEthSpeed100BaseTX; |
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310 } |
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311 if (status & (SMCS9118_PHY_10BTFD|SMCS9118_PHY_100BTXFD)) |
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312 { |
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313 iDefaultConfig.iEthDuplex = KEthDuplexFull; |
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314 } |
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315 |
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316 // setup store + forward |
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317 status = Read32(SMCS9118_HW_CFG); |
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318 status |= SMCS9118_HW_CFG_SF; |
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319 Write32(SMCS9118_HW_CFG, status); |
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320 ByteTestDelay(1); |
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321 |
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322 // setup Tx and Rx |
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323 Write32(SMCS9118_TX_CFG, SMCS9118_TX_CFG_TXSAO|SMCS9118_TX_CFG_TX_ON); |
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324 ByteTestDelay(1); |
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325 |
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326 TInt r; |
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327 r = WriteMac(SMCS9118_MAC_CR, SMCS9118_MAC_RXEN|SMCS9118_MAC_TXEN|SMCS9118_MAC_RXALL); |
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328 if (r != KErrNone) |
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329 { |
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330 DriverUnlock(irq); |
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331 return r; |
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332 } |
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333 |
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334 // Enable interrupts to CPU |
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335 r = EnableInterrupt(iInterruptId); |
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336 if(r != KErrNone) |
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337 { |
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338 TInt err; |
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339 __KTRACE_OPT(KHARDWARE,Kern::Printf("DEthernetSMSC9118Pdd::Start --- Interrupt::Enable()=%d", r)); |
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340 |
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341 // Disable TX, RX and exit |
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342 status &= ~(SMCS9118_MAC_RXEN | SMCS9118_MAC_TXEN | SMCS9118_MAC_RXALL); |
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343 err = WriteMac(SMCS9118_MAC_CR, status); |
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344 if (err != KErrNone) |
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345 { |
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346 DriverUnlock(irq); |
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347 return err; |
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348 } |
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349 |
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350 DriverUnlock(irq); |
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351 return r; |
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352 } |
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353 |
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354 // Rx Interrupt |
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355 Write32(SMCS9118_INT_EN, SMCS9118_INT_EN_RSFL); |
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356 ByteTestDelay(1); |
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357 |
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358 DriverUnlock(irq); |
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359 return KErrNone; |
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360 } |
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361 |
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362 |
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363 void DEthernetSMCS9118Pdd::MacConfigure(TEthernetConfigV01& aConfig) |
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364 /** |
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365 * Change the MAC address |
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366 * Attempt to change the MAC address of the device |
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367 * @param aConfig A Configuration containing the new MAC |
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368 * @see Configure() |
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369 * assume iDriverLock not held |
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370 */ |
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371 { |
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372 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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373 KPROFILE_PRINT("DEthernetSMCS9118Pdd::MacConfigure()"); |
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374 #endif |
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375 |
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376 |
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377 TUint32 mac, checkMac; |
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378 TInt err; |
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379 |
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380 TInt irq = DriverLock(); |
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381 mac = aConfig.iEthAddress[0]; |
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382 mac |= aConfig.iEthAddress[1]<<8; |
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383 mac |= aConfig.iEthAddress[2]<<16; |
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384 mac |= aConfig.iEthAddress[3]<<24; |
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385 |
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386 err = WriteMac(SMCS9118_MAC_ADDRL, mac); |
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387 if (err) |
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388 { |
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389 __KTRACE_OPT(KHARDWARE, Kern::Printf("DEthernetSMCS9118Pdd::MacConfigure() -- Failed to set MAC Address")); |
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390 DriverUnlock(irq); |
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391 return; |
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392 } |
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393 err = ReadMac(SMCS9118_MAC_ADDRL, checkMac); |
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394 if (err || checkMac != mac) |
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395 { |
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396 __KTRACE_OPT(KHARDWARE, Kern::Printf("DEthernetSMCS9118Pdd::MacConfigure() -- Failed to set MAC Address")); |
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397 DriverUnlock(irq); |
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398 return; |
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399 } |
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400 |
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401 mac = aConfig.iEthAddress[4]; |
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402 mac |= aConfig.iEthAddress[5]<<8; |
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403 err = WriteMac(SMCS9118_MAC_ADDRH, mac); |
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404 if (err) |
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405 { |
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406 __KTRACE_OPT(KHARDWARE, Kern::Printf("DEthernetSMCS9118Pdd::MacConfigure() -- Failed to set MAC Address")); |
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407 DriverUnlock(irq); |
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408 return; |
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409 } |
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410 err = ReadMac(SMCS9118_MAC_ADDRH, checkMac); |
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411 if (err || checkMac != mac) |
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412 { |
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413 __KTRACE_OPT(KHARDWARE, Kern::Printf("DEthernetSMCS9118Pdd::MacConfigure() -- Failed to set MAC Address")); |
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414 DriverUnlock(irq); |
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415 return; |
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416 } |
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417 |
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418 for (TInt i=0; i<=5; i++) |
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419 { |
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420 iDefaultConfig.iEthAddress[i] = aConfig.iEthAddress[i]; |
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421 } |
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422 |
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423 __KTRACE_OPT(KHARDWARE, Kern::Printf("-- MAC address %2x.%2x.%2x.%2x.%2x.%2x", |
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424 iDefaultConfig.iEthAddress[0], iDefaultConfig.iEthAddress[1], |
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425 iDefaultConfig.iEthAddress[2], iDefaultConfig.iEthAddress[3], |
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426 iDefaultConfig.iEthAddress[4], iDefaultConfig.iEthAddress[5])); |
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427 |
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428 DriverUnlock(irq); |
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429 return; |
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430 } |
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431 |
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432 |
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433 TInt DEthernetSMCS9118Pdd::Send(TBuf8<KMaxEthernetPacket+32>& aBuffer) |
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434 /** |
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435 * Transmit data |
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436 * @param aBuffer reference to the data to be sent |
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437 * @return KErrNone if the data has been sent |
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438 * assume iDriverLock not held |
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439 */ |
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440 { |
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441 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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442 KPROFILE_PRINT("DEthernetSMCS9118Pdd::Send()"); |
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443 #endif |
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444 |
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445 // Always request for power |
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446 iPowerHandler.RequestPower(); |
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447 TUint32* dataP = (TUint32 *)aBuffer.Ptr(); |
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448 TUint32 length = aBuffer.Length(); |
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449 |
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450 TInt irq = DriverLock(); |
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451 // can it fit |
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452 TUint32 status = Read32(SMCS9118_TX_FIFO_INF); |
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453 if ((status & SMCS9118_TX_SPACE_MASK) < length) |
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454 { |
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455 #if defined(INSTR) && defined(KTRACE_SYNCH) |
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456 KPROFILE_PRINT("eth -- Error... Send KErrSMCS9118TxOutOfMenory"); |
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457 #endif |
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458 DriverUnlock(irq); |
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459 return KErrTxOutOfMemory; |
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460 } |
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461 |
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462 status = (length & 0x7ff) | SMCS9118_TX_FIRSTSEG | SMCS9118_TX_LASTSEG; |
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463 Write32(SMCS9118_TX_DATA_FIFO, status); |
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464 status = (length & 0x7ff) | SMCS9118_TX_PKT_TAG; |
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465 Write32(SMCS9118_TX_DATA_FIFO, status); |
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466 |
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467 // calculate number of full words + remaining bytes |
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468 |
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469 TUint32 words = length >> 2; |
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470 TUint32 bytes = length & 3; |
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471 |
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472 // write words |
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473 while (words--) |
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474 { |
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475 Write32(SMCS9118_TX_DATA_FIFO, *dataP++); |
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476 } |
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477 |
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478 // write bytes |
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479 if (bytes) |
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480 { |
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481 TUint8 *dataBytes = (TUint8*) dataP; |
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482 status = 0; |
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483 switch (bytes) |
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484 { |
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485 case 3: |
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486 status |= dataBytes[2] << 16; |
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487 // fallthrough |
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488 case 2: |
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489 status |= dataBytes[1] << 8; |
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490 // fallthrough |
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491 case 1: |
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492 status |= dataBytes[0]; |
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493 } |
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494 Write32(SMCS9118_TX_DATA_FIFO, status); |
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495 } |
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496 |
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497 // Clear interrupt |
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498 TUint32 retries = SMCS9118_MAX_RETRIES; |
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499 while(retries-- && !((status = Read32(SMCS9118_INT_STS)) & SMCS9118_INT_STS_TX)) |
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500 { |
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501 ByteTestDelay(1); // delay |
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502 } |
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503 if (retries == 0 || (status & SMCS9118_INT_STS_TXE)) |
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504 { |
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505 DriverUnlock(irq); |
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506 return KErrGeneral; |
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507 } |
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508 Write32(SMCS9118_INT_STS, SMCS9118_INT_STS_TX); |
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509 ByteTestDelay(2); |
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510 |
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511 DriverUnlock(irq); |
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512 return KErrNone; |
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513 } |
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514 |
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515 TInt DEthernetSMCS9118Pdd::DiscardFrame() |
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516 /** |
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517 * Discard the frame by fast forwarding over it |
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518 * |
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519 * Optional: if this doesn't |
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520 * clear the frame, stop the receiver, dump the whole RX FIFO |
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521 * and restart the receiver |
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522 * assume iDriverLock held |
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523 */ |
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524 { |
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525 TUint32 retries = SMCS9118_MAX_RETRIES; |
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526 |
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527 // if it is 4 words or less then just read it |
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528 TInt32 status = Read32(SMCS9118_RX_STATUS); |
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529 TInt32 length = (status >> SMCS9118_RX_LEN_SHIFT) & SMCS9118_RX_LEN_MASK; |
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530 TInt32 words = length >> 2; |
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531 if (length & 3) |
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532 { |
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533 words++; |
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534 } |
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535 if (words <= 4) |
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536 { |
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537 while (words--) |
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538 { |
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539 status = Read32(SMCS9118_RX_DATA_FIFO); |
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540 } |
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541 status = Read32(SMCS9118_RX_DATA_FIFO); |
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542 return KErrNone; |
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543 } |
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544 |
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545 // FFWD over the frame |
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546 Write32(SMCS9118_RX_DP_CTL, SMCS9118_RX_DP_FFWD); |
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547 ByteTestDelay(1); |
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548 while((Read32(SMCS9118_RX_DP_CTL) & SMCS9118_RX_DP_FFWD) && --retries) |
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549 { |
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550 ByteTestDelay(1); // delay |
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551 } |
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552 if (retries != 0) |
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553 { |
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554 return KErrNone; |
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555 } |
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556 |
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557 #ifdef SMCS9118_DUMP_FIFO |
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558 // stop the receiver |
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559 TUint32 status; |
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560 TInt32 err; |
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561 err = ReadMac(SMCS9118_MAC_CR, status); |
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562 if (err != KErrNone) |
|
563 { |
|
564 return err; |
|
565 } |
|
566 status &= ~SMCS9118_MAC_RXEN; |
|
567 err = WriteMac(SMCS9118_MAC_CR, status); |
|
568 if (err != KErrNone) |
|
569 { |
|
570 return err; |
|
571 } |
|
572 |
|
573 // wait for reciever to stop |
|
574 retries = SMCS9118_MAX_RETRIES; |
|
575 Write32(SMCS9118_RX_DP_CTL, SMCS9118_RX_DP_FFWD); |
|
576 ByteTestDelay(2); |
|
577 while((Read32(SMCS9118_INT_STS) & SMCS9118_RXSTOP_INT) && --retries) |
|
578 { |
|
579 ByteTestDelay(1); // delay |
|
580 } |
|
581 if (retries == 0) |
|
582 { |
|
583 return KErrGeneral; |
|
584 } |
|
585 |
|
586 // dump the whole FIFO |
|
587 retries = SMCS9118_MAX_RETRIES; |
|
588 Write32(SMCS9118_RX_CFG, SMCS9118_RX_DUMP); |
|
589 ByteTestDelay(1); |
|
590 while((Read32(SMCS9118_RX_CFG) & SMCS9118_RX_DUMP) && --retries) |
|
591 { |
|
592 ByteTestDelay(1); // delay |
|
593 } |
|
594 if (retries != 0) |
|
595 { |
|
596 // re-enable RX |
|
597 err = ReadMac(SMCS9118_MAC_CR, status); |
|
598 if (err != KErrNone) |
|
599 { |
|
600 return err; |
|
601 } |
|
602 status |= SMCS9118_MAC_RXEN; |
|
603 err = WriteMac(SMCS9118_MAC_CR, status); |
|
604 return err; |
|
605 } |
|
606 #endif |
|
607 return KErrGeneral; |
|
608 } |
|
609 |
|
610 |
|
611 |
|
612 TInt DEthernetSMCS9118Pdd::ReceiveFrame(TBuf8<KMaxEthernetPacket+32>& aBuffer, TBool aOkToUse) |
|
613 /** |
|
614 * Retrieve data from the device - called by the RxDFC queued by the (variant's) ISR. |
|
615 * Pull the received data out of the device and into the supplied buffer. |
|
616 * Need to be told if the buffer is OK to use as if it not we could dump |
|
617 * the waiting frame in order to clear the interrupt if necessory. |
|
618 * @param aBuffer Reference to the buffer to be used to store the data in |
|
619 * @param aOkToUse Bool to indicate if the buffer is usable |
|
620 * @return KErrNone if the buffer has been filled. |
|
621 */ |
|
622 { |
|
623 TInt32 status; |
|
624 TUint32 length; |
|
625 |
|
626 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
627 KPROFILE_PRINT("DEthernetSMCS9118Pdd::ReceiveFrame()"); |
|
628 #endif |
|
629 // Always request for power (Needs to be done incase of external wakeup event) |
|
630 iPowerHandler.RequestPower(); |
|
631 |
|
632 TInt irq = DriverLock(); |
|
633 // If no buffer available dump frame |
|
634 if (!aOkToUse) |
|
635 { |
|
636 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
637 KPROFILE_PRINT("SMCS9118: No Rx buffer available"); |
|
638 #endif |
|
639 |
|
640 if ((status = DiscardFrame()) == KErrNone) |
|
641 { |
|
642 status = KErrGeneral; |
|
643 } |
|
644 DriverUnlock(irq); |
|
645 return status; |
|
646 } |
|
647 |
|
648 |
|
649 status = Read32(SMCS9118_RX_FIFO_INF); |
|
650 if(!(status & 0xffff)) |
|
651 { |
|
652 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
653 KPROFILE_PRINT("SMCS9118: Empty Rx FIFO"); |
|
654 #endif |
|
655 DriverUnlock(irq); |
|
656 return KErrGeneral; |
|
657 } |
|
658 |
|
659 // discard bad packets |
|
660 status = Read32(SMCS9118_RX_STATUS); |
|
661 length = (status >> SMCS9118_RX_LEN_SHIFT) & SMCS9118_RX_LEN_MASK; |
|
662 if (status & SMCS9118_RX_ES) |
|
663 { |
|
664 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
665 KPROFILE_PRINT("SMCS9118: Bad Rx Packet"); |
|
666 #endif |
|
667 |
|
668 if ((status = DiscardFrame()) == (TUint32)KErrNone) |
|
669 { |
|
670 status = KErrGeneral; |
|
671 } |
|
672 DriverUnlock(irq); |
|
673 return status; |
|
674 } |
|
675 |
|
676 TUint32 words = length >> 2; |
|
677 TUint32 *dataP = (TUint32*) aBuffer.Ptr(); |
|
678 |
|
679 if (length & 3) |
|
680 { |
|
681 words++; |
|
682 } |
|
683 |
|
684 while (words--) |
|
685 { |
|
686 *dataP++ = Read32(SMCS9118_RX_DATA_FIFO); |
|
687 } |
|
688 aBuffer.SetLength(length-4); |
|
689 |
|
690 DriverUnlock(irq); |
|
691 return KErrNone; |
|
692 } |
|
693 |
|
694 |
|
695 const TInt KEthernetDfcThreadPriority = 24; |
|
696 _LIT(KEthernetDfcThread,"EthernetDfcThread"); |
|
697 |
|
698 |
|
699 TInt DEthernetSMCS9118Pdd::DoCreate() |
|
700 /** |
|
701 * Does the hard and soft reset of the lan card. |
|
702 * Puts the default configuration in iDefaultConfig member |
|
703 */ |
|
704 { |
|
705 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
706 KPROFILE_PRINT("DEthernetSMCS9118Pdd::DoCreate()"); |
|
707 #endif |
|
708 |
|
709 |
|
710 // Register the power handler with Symbian Power Framework |
|
711 iPowerHandler.Add(); |
|
712 TInt r = iPowerHandler.SetEthernetPdd(this); |
|
713 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
714 __KTRACE_OPT(KPOWER, Kern::Printf("iPowerHandler.SetEthernetPdd() returned [%d]",r)); |
|
715 #endif |
|
716 |
|
717 // Allocate a kernel thread to run the DFC |
|
718 r = Kern::DynamicDfcQCreate(iDfcQ, KEthernetDfcThreadPriority, KEthernetDfcThread); |
|
719 |
|
720 if (r != KErrNone) |
|
721 { |
|
722 return r; |
|
723 } |
|
724 |
|
725 #ifdef CPU_AFFINITY_ANY |
|
726 NKern::ThreadSetCpuAffinity((NThread*) iDfcQ->iThread, KCpuAffinityAny); |
|
727 #endif |
|
728 |
|
729 iRxDfc.SetDfcQ(iDfcQ); |
|
730 |
|
731 TInt irq = DriverLock(); |
|
732 iDefaultConfig.iEthSpeed = KEthSpeed10BaseT; |
|
733 iDefaultConfig.iEthDuplex = KEthDuplexHalf; |
|
734 |
|
735 // detect if SMSC9118 card is available, ignore revision |
|
736 TUint32 id = Read32(SMCS9118_ID_REV) & SMCS9118_ID_MASK; |
|
737 if(id != SMCS9118_ID_VAL) |
|
738 { |
|
739 DriverUnlock(irq); |
|
740 return KErrHardwareNotAvailable; |
|
741 } |
|
742 |
|
743 TUint32 mac; |
|
744 r = ReadMac(SMCS9118_MAC_ADDRL, mac); |
|
745 if (r != KErrNone) |
|
746 { |
|
747 DriverUnlock(irq); |
|
748 return r; |
|
749 } |
|
750 |
|
751 iDefaultConfig.iEthAddress[0] = (TUint8)(mac); |
|
752 iDefaultConfig.iEthAddress[1] = (TUint8)(mac>>8); |
|
753 iDefaultConfig.iEthAddress[2] = (TUint8)(mac>>16); |
|
754 iDefaultConfig.iEthAddress[3] = (TUint8)(mac>>24); |
|
755 r = ReadMac(SMCS9118_MAC_ADDRH, mac); |
|
756 if (r != KErrNone) |
|
757 { |
|
758 DriverUnlock(irq); |
|
759 return r; |
|
760 } |
|
761 iDefaultConfig.iEthAddress[4] = (TUint8)(mac); |
|
762 iDefaultConfig.iEthAddress[5] = (TUint8)(mac>>8); |
|
763 |
|
764 // Serial number is the bottom 4 bytes of the MAC address |
|
765 TInt serialNum = (iDefaultConfig.iEthAddress[2] << 24) |
|
766 | (iDefaultConfig.iEthAddress[3] << 16) |
|
767 | (iDefaultConfig.iEthAddress[4] << 8) |
|
768 | (iDefaultConfig.iEthAddress[5] ); |
|
769 |
|
770 // Push the serial numberinto the variant config so it can be retrieved via HAL |
|
771 NE1_TBVariant::SetSerialNumber(serialNum); |
|
772 |
|
773 iInterruptId = KEthernetInterruptId; |
|
774 |
|
775 DriverUnlock(irq); |
|
776 __KTRACE_OPT(KHARDWARE, Kern::Printf("-- MAC address %2x.%2x.%2x.%2x.%2x.%2x", |
|
777 iDefaultConfig.iEthAddress[0], iDefaultConfig.iEthAddress[1], |
|
778 iDefaultConfig.iEthAddress[2], iDefaultConfig.iEthAddress[3], |
|
779 iDefaultConfig.iEthAddress[4], iDefaultConfig.iEthAddress[5])); |
|
780 |
|
781 // Register ISR |
|
782 r = BindInterrupt(KEthernetInterruptId, Isr, this); |
|
783 if(r != KErrNone) |
|
784 { |
|
785 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
786 KPROFILE_PRINT("-- Error!!! Ethernet failed to bind interrupt."); |
|
787 #endif |
|
788 return r; |
|
789 } |
|
790 return r; |
|
791 } |
|
792 |
|
793 void DEthernetSMCS9118Pdd::Sleep() |
|
794 /** |
|
795 * Put the card into D1 sleep |
|
796 * assume iDriverLock not held |
|
797 */ |
|
798 { |
|
799 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
800 KPROFILE_PRINT("DEthernetSMCS9118Pdd::Sleep()"); |
|
801 #endif |
|
802 |
|
803 TUint32 status; |
|
804 TInt irq = DriverLock(); |
|
805 status = Read32(SMCS9118_PMT_CTRL) | SMCS9118_PM_MODE_D1; |
|
806 Write32(SMCS9118_PMT_CTRL, status); |
|
807 DriverUnlock(irq); |
|
808 } |
|
809 |
|
810 TInt DEthernetSMCS9118Pdd::Wakeup() |
|
811 /** |
|
812 * Wake the card up |
|
813 * assume iDriverLock not held |
|
814 */ |
|
815 { |
|
816 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
817 KPROFILE_PRINT("DEthernetSMCS9118Pdd::Wakeup()"); |
|
818 #endif |
|
819 |
|
820 TUint32 status; |
|
821 |
|
822 // has card woken up yet ? |
|
823 |
|
824 TInt irq = DriverLock(); |
|
825 TUint32 retry = SMCS9118_MAX_RETRIES; |
|
826 do |
|
827 { |
|
828 Write32(SMCS9118_BYTE_TEST, 0x12345678); |
|
829 status = Read32(SMCS9118_PMT_CTRL); |
|
830 if (status & SMCS9118_PMT_READY) |
|
831 { |
|
832 break; |
|
833 } |
|
834 Kern::NanoWait(ONE_MSEC); |
|
835 } while (--retry); |
|
836 |
|
837 if (retry == 0) |
|
838 { |
|
839 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
840 KPROFILE_PRINT("-- Error!!! Problem in Wakeup of SMCS9118 card."); |
|
841 #endif |
|
842 DriverUnlock(irq); |
|
843 return KErrGeneral; |
|
844 } |
|
845 DriverUnlock(irq); |
|
846 return KErrNone; |
|
847 } |
|
848 |
|
849 TInt DEthernetSMCS9118Pdd::CardSoftReset() |
|
850 /** |
|
851 * Does the soft reset of the lan card |
|
852 * assume iDriverLock not held |
|
853 */ |
|
854 { |
|
855 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
856 KPROFILE_PRINT("DEthernetSMCS9118Pdd::CardSoftReset()"); |
|
857 #endif |
|
858 |
|
859 TInt32 status; |
|
860 |
|
861 // wake the card up |
|
862 status = Wakeup(); |
|
863 if (status != KErrNone) |
|
864 { |
|
865 return status; |
|
866 } |
|
867 |
|
868 // do soft reset |
|
869 TInt irq = DriverLock(); |
|
870 status = Read32(SMCS9118_HW_CFG); |
|
871 status |= SMCS9118_HW_CFG_SRST; |
|
872 Write32(SMCS9118_HW_CFG, status); |
|
873 |
|
874 ByteTestDelay(1); |
|
875 |
|
876 TUint32 retry = SMCS9118_MAX_RETRIES; |
|
877 do |
|
878 { |
|
879 status = Read32(SMCS9118_HW_CFG); |
|
880 if (!(status & SMCS9118_HW_CFG_SRST)) |
|
881 { |
|
882 break; |
|
883 } |
|
884 Kern::NanoWait(ONE_MSEC); |
|
885 } while (--retry); |
|
886 |
|
887 if (retry == 0) |
|
888 { |
|
889 DriverUnlock(irq); |
|
890 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
891 KPROFILE_PRINT("-- Error!!! Problem in soft reset of SMCS9118 card."); |
|
892 #endif |
|
893 return KErrGeneral; |
|
894 } |
|
895 |
|
896 ByteTestDelay(1); |
|
897 DriverUnlock(irq); |
|
898 |
|
899 return KErrNone; |
|
900 } |
|
901 |
|
902 |
|
903 /** |
|
904 * service the Isr |
|
905 */ |
|
906 void DEthernetSMCS9118Pdd::Isr(TAny* aPtr) |
|
907 { |
|
908 |
|
909 DEthernetSMCS9118Pdd &d=*(DEthernetSMCS9118Pdd*)aPtr; |
|
910 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
911 KPROFILE_PRINT("DEthernetSMCS9118Pdd::Isr"); |
|
912 #endif |
|
913 |
|
914 // get interrupt status |
|
915 TUint32 status = d.Read32(SMCS9118_INT_STS); |
|
916 |
|
917 if (d.IsReady() && (status & SMCS9118_INT_STS_RSFL)) |
|
918 { |
|
919 // We received an Rx Interrupt, so clear it |
|
920 // and queue on dfc |
|
921 d.Write32(SMCS9118_INT_EN, 0); |
|
922 d.iRxDfc.Add(); |
|
923 } |
|
924 else |
|
925 { |
|
926 // spurious interrupt ? |
|
927 d.Write32(SMCS9118_INT_STS, status); |
|
928 } |
|
929 d.ClearInterrupt(d.iInterruptId); |
|
930 } |
|
931 |
|
932 // |
|
933 // Queued by the ISR on a receive interrupt. Calls into LDD which calls back into |
|
934 // PDD.ReceiveFrame() to get the data and write it into the LDD managed FIFO. |
|
935 // Assume iDriverLock not held |
|
936 // |
|
937 |
|
938 void DEthernetSMCS9118Pdd::ServiceRxDfc(TAny* aPtr) |
|
939 { |
|
940 #if defined(INSTR) && defined(KTRACE_SYNCH) |
|
941 KPROFILE_PRINT("DEthernetSMCS9118Pdd::ServiceRxDfc"); |
|
942 #endif |
|
943 |
|
944 DEthernetSMCS9118Pdd &d=*(DEthernetSMCS9118Pdd*)aPtr; |
|
945 |
|
946 d.ReceiveIsr(); |
|
947 |
|
948 TInt irq = d.DriverLock(); |
|
949 // reset status |
|
950 d.Write32(SMCS9118_INT_STS, SMCS9118_INT_STS_RSFL); |
|
951 d.ByteTestDelay(2); |
|
952 |
|
953 // reenable interrupt |
|
954 d.Write32(SMCS9118_INT_EN, SMCS9118_INT_EN_RSFL); |
|
955 d.ByteTestDelay(1); |
|
956 d.DriverUnlock(irq); |
|
957 |
|
958 return; |
|
959 } |
|
960 |
|
961 /** |
|
962 * Read a MAC register |
|
963 * assume iDriverLock held |
|
964 */ |
|
965 TInt32 DEthernetSMCS9118Pdd::ReadMac(TUint32 aReg, TUint32 &aVal) |
|
966 { |
|
967 TUint32 timeout; |
|
968 |
|
969 for(timeout = 0; timeout < SMCS9118_MAC_TIMEOUT; timeout ++) |
|
970 { |
|
971 if(Read32(SMCS9118_MAC_CSR_CMD) & SMCS9118_MAC_CSR_BUSY) |
|
972 { |
|
973 Kern::NanoWait(ONE_MSEC); |
|
974 } |
|
975 } |
|
976 |
|
977 TUint32 cmd = 0; |
|
978 |
|
979 Write32(SMCS9118_MAC_CSR_CMD, cmd); |
|
980 ByteTestDelay(1); |
|
981 |
|
982 cmd = (aReg & 0xff) | SMCS9118_MAC_CSR_BUSY | SMCS9118_MAC_CSR_READ; |
|
983 |
|
984 Write32(SMCS9118_MAC_CSR_CMD, cmd); |
|
985 ByteTestDelay(1); |
|
986 |
|
987 for(timeout = 0; timeout < SMCS9118_MAC_TIMEOUT; timeout ++) |
|
988 { |
|
989 if(Read32(SMCS9118_MAC_CSR_CMD) & SMCS9118_MAC_CSR_BUSY) |
|
990 { |
|
991 Kern::NanoWait(ONE_MSEC); |
|
992 } |
|
993 else |
|
994 { |
|
995 aVal = Read32(SMCS9118_MAC_CSR_DATA); |
|
996 return KErrNone; |
|
997 } |
|
998 } |
|
999 return KErrTimedOut; |
|
1000 } |
|
1001 |
|
1002 /** |
|
1003 * Write a MAC register |
|
1004 * assume iDriverLock held |
|
1005 */ |
|
1006 TInt32 DEthernetSMCS9118Pdd::WriteMac(TUint32 aReg, TUint32 aVal) |
|
1007 { |
|
1008 if (Read32(SMCS9118_MAC_CSR_CMD) & SMCS9118_MAC_CSR_BUSY) |
|
1009 { |
|
1010 return KErrTimedOut; |
|
1011 } |
|
1012 |
|
1013 TUint32 cmd = 0; |
|
1014 TUint32 timeout; |
|
1015 |
|
1016 Write32(SMCS9118_MAC_CSR_CMD, cmd); |
|
1017 ByteTestDelay(1); |
|
1018 |
|
1019 cmd = (aReg & 0xff) | SMCS9118_MAC_CSR_BUSY; |
|
1020 |
|
1021 Write32(SMCS9118_MAC_CSR_DATA, aVal); |
|
1022 ByteTestDelay(1); |
|
1023 Write32(SMCS9118_MAC_CSR_CMD, cmd); |
|
1024 ByteTestDelay(1); |
|
1025 |
|
1026 for (timeout = 0; timeout < SMCS9118_MAC_TIMEOUT; timeout ++) |
|
1027 { |
|
1028 if(Read32(SMCS9118_MAC_CSR_CMD) & SMCS9118_MAC_CSR_BUSY) |
|
1029 { |
|
1030 Kern::NanoWait(ONE_MSEC); |
|
1031 } |
|
1032 else |
|
1033 { |
|
1034 return KErrNone; |
|
1035 } |
|
1036 } |
|
1037 return KErrTimedOut; |
|
1038 } |
|
1039 |
|
1040 /** |
|
1041 * Read a PHY register |
|
1042 * assume iDriverLock held |
|
1043 */ |
|
1044 TInt32 DEthernetSMCS9118Pdd::ReadPhy(TUint32 aReg, TUint32 &aValue) |
|
1045 { |
|
1046 TUint32 cmd; |
|
1047 TUint32 timeout; |
|
1048 TInt32 err; |
|
1049 |
|
1050 // bail out if busy |
|
1051 err = ReadMac(SMCS9118_MAC_MII_ACC, aValue); |
|
1052 if (err != KErrNone) |
|
1053 { |
|
1054 return err; |
|
1055 } |
|
1056 |
|
1057 if (aValue & SMCS9118_MII_BUSY) |
|
1058 { |
|
1059 return KErrTimedOut; |
|
1060 } |
|
1061 |
|
1062 cmd = SMCS9118_PHY_ADDR | (aReg << 6) | SMCS9118_MII_BUSY; |
|
1063 |
|
1064 err = WriteMac(SMCS9118_MAC_MII_ACC, cmd); |
|
1065 if (err != KErrNone) |
|
1066 { |
|
1067 return err; |
|
1068 } |
|
1069 |
|
1070 for(timeout = 0; timeout < SMCS9118_MAC_TIMEOUT; timeout++) |
|
1071 { |
|
1072 err = ReadMac(SMCS9118_MAC_MII_ACC, aValue); |
|
1073 if (err != KErrNone) |
|
1074 { |
|
1075 return err; |
|
1076 } |
|
1077 |
|
1078 if (!(aValue & SMCS9118_MII_BUSY)) |
|
1079 { |
|
1080 err = ReadMac(SMCS9118_MAC_MII_DATA, aValue); |
|
1081 return err; |
|
1082 } |
|
1083 } |
|
1084 return KErrTimedOut; |
|
1085 } |
|
1086 |
|
1087 /** |
|
1088 * Write a PHY register |
|
1089 * assume iDriverLock held |
|
1090 */ |
|
1091 TInt32 DEthernetSMCS9118Pdd::WritePhy(TUint32 aReg, TUint32 aVal) |
|
1092 { |
|
1093 TUint32 cmd; |
|
1094 TUint32 timeout; |
|
1095 TUint32 status; |
|
1096 TInt32 err; |
|
1097 |
|
1098 // bail out if busy |
|
1099 err = ReadMac(SMCS9118_MAC_MII_ACC, status); |
|
1100 if (err != KErrNone) |
|
1101 { |
|
1102 return err; |
|
1103 } |
|
1104 |
|
1105 if (status & SMCS9118_MII_BUSY) |
|
1106 { |
|
1107 return KErrTimedOut; |
|
1108 } |
|
1109 |
|
1110 cmd = SMCS9118_PHY_ADDR | (aReg << 6) | SMCS9118_MII_WRITE | SMCS9118_MII_BUSY; |
|
1111 |
|
1112 err = WriteMac(SMCS9118_MAC_MII_DATA, aVal & 0xffff); |
|
1113 if (err != KErrNone) |
|
1114 { |
|
1115 return err; |
|
1116 } |
|
1117 err = WriteMac(SMCS9118_MAC_MII_ACC, cmd); |
|
1118 if (err != KErrNone) |
|
1119 { |
|
1120 return err; |
|
1121 } |
|
1122 |
|
1123 for(timeout = 0; timeout < SMCS9118_MAC_TIMEOUT; timeout++) |
|
1124 { |
|
1125 err = ReadMac(SMCS9118_MAC_MII_ACC, status); |
|
1126 if (err != KErrNone) |
|
1127 { |
|
1128 return err; |
|
1129 } |
|
1130 if(!(status & SMCS9118_MII_BUSY)) |
|
1131 { |
|
1132 return KErrNone; |
|
1133 } |
|
1134 } |
|
1135 return KErrTimedOut; |
|
1136 } |
|
1137 // PDD entry point |
|
1138 DECLARE_STANDARD_PDD() |
|
1139 { |
|
1140 return new DEthernetPddFactory; |
|
1141 } |