navienginebsp/ne1_tb/ethernet/smcs9118_ethernet.inl
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     1 /*
       
     2 * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
       
     3 * All rights reserved.
       
     4 * This component and the accompanying materials are made available
       
     5 * under the terms of "Eclipse Public License v1.0"
       
     6 * which accompanies this distribution, and is available
       
     7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".
       
     8 *
       
     9 * Initial Contributors:
       
    10 * Nokia Corporation - initial contribution.
       
    11 *
       
    12 * Contributors:
       
    13 *
       
    14 * Description: 
       
    15 *
       
    16 */
       
    17 
       
    18 
       
    19 inline TInt32 DEthernetSMCS9118Pdd::IsReady()
       
    20 	{
       
    21 	return iReady;
       
    22 	}
       
    23 
       
    24 /**
       
    25  * see data sheet section 6.1, Host Interface Timing
       
    26  * "dummy" reads of the BYTE_TEST register will
       
    27  * guarantee the minimum write-to-read timing restrictions
       
    28  * as listed in Table 6.1
       
    29  */
       
    30 inline void DEthernetSMCS9118Pdd::ByteTestDelay(TUint32 aCount)
       
    31 	{
       
    32 	TUint32 i;
       
    33 
       
    34 	for (i = 0; i< aCount; i++)
       
    35 		{
       
    36 		AsspRegister::Read32(SMCS9118_BYTE_TEST);
       
    37 		}
       
    38 	}
       
    39 
       
    40 /**
       
    41  * Read a 32bit register
       
    42  */
       
    43 inline TUint32 DEthernetSMCS9118Pdd::Read32(TUint32 aReg)
       
    44 	{
       
    45 	return AsspRegister::Read32(aReg);
       
    46 	}
       
    47 
       
    48 /**
       
    49  * Write a 32bit register
       
    50  */
       
    51 inline void DEthernetSMCS9118Pdd::Write32(TUint32 aReg, TUint32 aVal)
       
    52 	{
       
    53 	AsspRegister::Write32(aReg, aVal);
       
    54 	}
       
    55 
       
    56 /**
       
    57  * Interrupt handling
       
    58  */
       
    59 inline void DEthernetSMCS9118Pdd::ClearInterrupt(TInt aId)
       
    60 	{
       
    61 	GPIO::ClearInterrupt(aId);
       
    62 	}
       
    63 
       
    64 inline void DEthernetSMCS9118Pdd::UnbindInterrupt(TInt aId)
       
    65 	{
       
    66 	GPIO::UnbindInterrupt(aId);
       
    67 	}
       
    68 
       
    69 inline TInt DEthernetSMCS9118Pdd::BindInterrupt(TInt aId, TGpioIsr aIsr, TAny *aPtr)
       
    70 	{
       
    71 	return GPIO::BindInterrupt(aId, aIsr, aPtr);
       
    72 	}
       
    73 
       
    74 inline TInt DEthernetSMCS9118Pdd::EnableInterrupt(TInt aId)
       
    75 	{
       
    76 	return GPIO::EnableInterrupt(aId);
       
    77 	}
       
    78 
       
    79 inline TInt DEthernetSMCS9118Pdd::DisableInterrupt(TInt aId)
       
    80 	{
       
    81 	return GPIO::DisableInterrupt(aId);
       
    82 	}
       
    83 
       
    84 /**
       
    85  * lock handling
       
    86  */
       
    87 inline TInt DEthernetSMCS9118Pdd::DriverLock()
       
    88 	{
       
    89 	return __SPIN_LOCK_IRQSAVE(*iDriverLock); 
       
    90 	}
       
    91 
       
    92 inline void DEthernetSMCS9118Pdd::DriverUnlock(TInt irq)
       
    93 	{
       
    94 	__SPIN_UNLOCK_IRQRESTORE(*iDriverLock, irq); 
       
    95 	}