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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * This file is part of the NE1_TB Variant Base Port |
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16 * Hardware Configuration Respoitory Published Setting IDs header. |
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17 * |
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18 */ |
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19 |
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20 |
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21 |
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22 /** |
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23 @file hcrconfig_assp.h |
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24 File provides definitions for the published set of HCR settings |
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25 identifiers applicable to the MHA Services on the NEC NaviEngine |
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26 base port. |
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27 |
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28 @publishedPartner |
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29 @prototype |
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30 */ |
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31 |
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32 #ifndef HCRCONFIG_MHA_H |
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33 #define HCRCONFIG_MHA_H |
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34 |
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35 |
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36 |
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37 // -- INCLUDES ---------------------------------------------------------------- |
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38 |
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39 #include <drivers/hcr.h> |
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40 |
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41 |
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42 |
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43 // -- CATEGORY UIDs ----------------------------------------------------------- |
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44 |
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45 |
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46 |
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47 // -- KEYS -------------------------------------------------------------------- |
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48 |
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49 /** |
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50 HCR Settings identifing the assignment of Interrrupt lines. |
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51 |
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52 These element keys are used along with the KHcrCat_MHA_Interrupt category UID |
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53 to identify and read the HCR setting. |
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54 */ |
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55 #define INT_SRC 0x00010000 |
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56 const HCR::TElementId KHcrKey_Interrupt_ExBus = INT_SRC + 11; //< |
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57 |
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58 const HCR::TElementId KHcrKey_Interrupt_I2C = INT_SRC + 12; //< |
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59 |
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60 const HCR::TElementId KHcrKey_Interrupt_CSI0 = INT_SRC + 13; //< |
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61 const HCR::TElementId KHcrKey_Interrupt_CSI1 = INT_SRC + 14; //< |
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62 |
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63 const HCR::TElementId KHcrKey_Interrupt_Timer0 = INT_SRC + 21; //< SoC Timer0 interrupt |
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64 const HCR::TElementId KHcrKey_Interrupt_Timer1 = INT_SRC + 22; //< SoC Timer1 interrupt |
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65 const HCR::TElementId KHcrKey_Interrupt_Timer2 = INT_SRC + 23; //< SoC Timer2 interrupt |
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66 const HCR::TElementId KHcrKey_Interrupt_Timer3 = INT_SRC + 24; //< SoC Timer3 interrupt |
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67 const HCR::TElementId KHcrKey_Interrupt_Timer4 = INT_SRC + 25; //< SoC Timer4 interrupt |
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68 const HCR::TElementId KHcrKey_Interrupt_Timer5 = INT_SRC + 26; //< SoC Timer5 interrupt |
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69 |
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70 const HCR::TElementId KHcrKey_Interrupt_PWM = INT_SRC + 31; //< |
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71 |
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72 const HCR::TElementId KHcrKey_Interrupt_SD0 = INT_SRC + 32; //< SD #0 : OXMNIRQ |
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73 const HCR::TElementId KHcrKey_Interrupt_SD1 = INT_SRC + 33; //< SD #1 : OXASIOIRQ //SDIO |
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74 |
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75 const HCR::TElementId KHcrKey_Interrupt_CF = INT_SRC + 41; //< |
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76 const HCR::TElementId KHcrKey_Interrupt_NAND = INT_SRC + 42; //< Nand Controller |
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77 const HCR::TElementId KHcrKey_Interrupt_MIF = INT_SRC + 43; //< |
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78 const HCR::TElementId KHcrKey_Interrupt_DTV = INT_SRC + 44; //< |
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79 const HCR::TElementId KHcrKey_Interrupt_SGX = INT_SRC + 45; //< |
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80 |
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81 const HCR::TElementId KHcrKey_Interrupt_DISP0 = INT_SRC + 51; //< DISP 0 |
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82 const HCR::TElementId KHcrKey_Interrupt_DISP1 = INT_SRC + 52; //< |
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83 const HCR::TElementId KHcrKey_Interrupt_DISP2 = INT_SRC + 53; //< |
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84 |
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85 const HCR::TElementId KHcrKey_Interrupt_Video = INT_SRC + 61; //< |
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86 const HCR::TElementId KHcrKey_Interrupt_SPDIF0 = INT_SRC + 62; //< |
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87 const HCR::TElementId KHcrKey_Interrupt_SPDIF1 = INT_SRC + 63; //< |
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88 |
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89 const HCR::TElementId KHcrKey_Interrupt_I2S0 = INT_SRC + 71; //< I2S 0 Interrupts |
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90 const HCR::TElementId KHcrKey_Interrupt_I2S1 = INT_SRC + 72; //< |
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91 const HCR::TElementId KHcrKey_Interrupt_I2S2 = INT_SRC + 73; //< |
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92 const HCR::TElementId KHcrKey_Interrupt_I2S3 = INT_SRC + 74; //< |
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93 |
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94 const HCR::TElementId KHcrKey_Interrupt_APB = INT_SRC + 81; //< |
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95 const HCR::TElementId KHcrKey_Interrupt_AHB0 = INT_SRC + 82; //< |
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96 const HCR::TElementId KHcrKey_Interrupt_AHB1 = INT_SRC + 83; //< |
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97 const HCR::TElementId KHcrKey_Interrupt_AHB2 = INT_SRC + 84; //< |
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98 |
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99 const HCR::TElementId KHcrKey_Interrupt_AXI = INT_SRC + 91; //< |
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100 |
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101 const HCR::TElementId KHcrKey_Interrupt_PCIint = INT_SRC + 101; //< PCI Int |
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102 const HCR::TElementId KHcrKey_Interrupt_PCIserrb = INT_SRC + 102; //< PCI Systerm Error |
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103 const HCR::TElementId KHcrKey_Interrupt_PCIperrb = INT_SRC + 103; //< PCI Parity Error |
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104 const HCR::TElementId KHcrKey_Interrupt_PCIExInt = INT_SRC + 104; //< |
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105 const HCR::TElementId KHcrKey_Interrupt_PCIExSerrb = INT_SRC + 105; //< |
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106 const HCR::TElementId KHcrKey_Interrupt_PCIExPerrb = INT_SRC + 106; //< |
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107 |
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108 const HCR::TElementId KHcrKey_Interrupt_USBHintA = INT_SRC + 111; //< USB Host Int A |
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109 const HCR::TElementId KHcrKey_Interrupt_USBHintB = INT_SRC + 112; //< USB Host Int B |
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110 const HCR::TElementId KHcrKey_Interrupt_USBHsmi = INT_SRC + 113; //< USB Host System Management Interrupt |
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111 const HCR::TElementId KHcrKey_Interrupt_USBHpme = INT_SRC + 114; //< USB Host Power Management Event |
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112 |
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113 const HCR::TElementId KHcrKey_Interrupt_ATA6 = INT_SRC + 121; //< |
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114 |
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115 const HCR::TElementId KHcrKey_Interrupt_DMAC32_0end = INT_SRC + 131; //< |
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116 const HCR::TElementId KHcrKey_Interrupt_DMAC32_0err = INT_SRC + 132; //< |
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117 const HCR::TElementId KHcrKey_Interrupt_DMAC32_1end = INT_SRC + 133; //< |
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118 const HCR::TElementId KHcrKey_Interrupt_DMAC32_1err = INT_SRC + 134; //< |
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119 const HCR::TElementId KHcrKey_Interrupt_DMAC32_2end = INT_SRC + 135; //< |
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120 const HCR::TElementId KHcrKey_Interrupt_DMAC32_2err = INT_SRC + 136; //< |
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121 const HCR::TElementId KHcrKey_Interrupt_DMAC32_3end = INT_SRC + 137; //< |
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122 const HCR::TElementId KHcrKey_Interrupt_DMAC32_3err = INT_SRC + 138; //< |
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123 const HCR::TElementId KHcrKey_Interrupt_DMAC32_4end = INT_SRC + 139; //< |
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124 const HCR::TElementId KHcrKey_Interrupt_DMAC32_4err = INT_SRC + 140; //< |
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125 |
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126 const HCR::TElementId KHcrKey_Interrupt_UART0 = INT_SRC + 151; //< SoC Uart #0 |
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127 const HCR::TElementId KHcrKey_Interrupt_UART1 = INT_SRC + 152; //< SoC Uart #1 |
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128 const HCR::TElementId KHcrKey_Interrupt_UART2 = INT_SRC + 153; //< SoC Uart #2 |
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129 const HCR::TElementId KHcrKey_Interrupt_UART3 = INT_SRC + 154; //< |
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130 const HCR::TElementId KHcrKey_Interrupt_UART4 = INT_SRC + 155; //< |
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131 const HCR::TElementId KHcrKey_Interrupt_UART5 = INT_SRC + 156; //< |
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132 const HCR::TElementId KHcrKey_Interrupt_UART6 = INT_SRC + 157; //< |
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133 const HCR::TElementId KHcrKey_Interrupt_UART7 = INT_SRC + 158; //< |
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134 |
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135 const HCR::TElementId KHcrKey_Interrupt_GPIO = INT_SRC + 161; //< |
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136 const HCR::TElementId KHcrKey_Interrupt_eWDT = INT_SRC + 162; //< |
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137 const HCR::TElementId KHcrKey_Interrupt_SATA = INT_SRC + 163; //< |
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138 |
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139 const HCR::TElementId KHcrKey_Interrupt_DMACaxi_End = INT_SRC + 171; //< |
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140 const HCR::TElementId KHcrKey_Interrupt_DMACaxi_Err = INT_SRC + 172; //< |
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141 |
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142 const HCR::TElementId KHcrKey_Interrupt_PMUIRG0 = INT_SRC + 181; //< |
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143 const HCR::TElementId KHcrKey_Interrupt_PMUIRG1 = INT_SRC + 182; //< |
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144 const HCR::TElementId KHcrKey_Interrupt_PMUIRG2 = INT_SRC + 183; //< |
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145 const HCR::TElementId KHcrKey_Interrupt_PMUIRG3 = INT_SRC + 184; //< |
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146 const HCR::TElementId KHcrKey_Interrupt_PMUIRG4 = INT_SRC + 185; //< |
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147 const HCR::TElementId KHcrKey_Interrupt_PMUIRG5 = INT_SRC + 186; //< |
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148 const HCR::TElementId KHcrKey_Interrupt_PMUIRG6 = INT_SRC + 187; //< |
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149 const HCR::TElementId KHcrKey_Interrupt_PMUIRG7 = INT_SRC + 188; //< |
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150 const HCR::TElementId KHcrKey_Interrupt_PMUIRG8 = INT_SRC + 189; //< |
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151 const HCR::TElementId KHcrKey_Interrupt_PMUIRG9 = INT_SRC + 190; //< |
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152 const HCR::TElementId KHcrKey_Interrupt_PMUIRG10 = INT_SRC + 191; //< |
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153 const HCR::TElementId KHcrKey_Interrupt_PMUIRG11 = INT_SRC + 192; //< |
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154 |
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155 const HCR::TElementId KHcrKey_Interrupt_COMMRX0 = INT_SRC + 201; //< |
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156 const HCR::TElementId KHcrKey_Interrupt_COMMRX1 = INT_SRC + 202; //< |
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157 const HCR::TElementId KHcrKey_Interrupt_COMMRX2 = INT_SRC + 203; //< |
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158 const HCR::TElementId KHcrKey_Interrupt_COMMRX3 = INT_SRC + 204; //< |
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159 const HCR::TElementId KHcrKey_Interrupt_COMMTX0 = INT_SRC + 205; //< |
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160 const HCR::TElementId KHcrKey_Interrupt_COMMTX1 = INT_SRC + 206; //< |
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161 const HCR::TElementId KHcrKey_Interrupt_COMMTX2 = INT_SRC + 207; //< |
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162 const HCR::TElementId KHcrKey_Interrupt_COMMTX3 = INT_SRC + 208; //< |
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163 |
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164 const HCR::TElementId KHcrKey_Interrupt_PWRCTLO0 = INT_SRC + 211; //< |
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165 const HCR::TElementId KHcrKey_Interrupt_PWRCTLO1 = INT_SRC + 212; //< |
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166 const HCR::TElementId KHcrKey_Interrupt_PWRCTLO2 = INT_SRC + 213; //< |
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167 const HCR::TElementId KHcrKey_Interrupt_PWRCTLO3 = INT_SRC + 214; //< |
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168 |
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169 const HCR::TElementId KHcrKey_Interrupt_DMACexbus_End = INT_SRC + 221; //< |
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170 const HCR::TElementId KHcrKey_Interrupt_DMACexbus_Err = INT_SRC + 222; //< |
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171 const HCR::TElementId KHcrKey_Interrupt_AHBbridge3 = INT_SRC + 223; //< |
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172 |
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173 #undef INT_SRC |
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174 |
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175 |
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176 /** |
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177 HCR Settings identifing the GPIO pin assignments. |
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178 |
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179 These element keys are used along with the KHcrCat_MHA_GPIO category UID |
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180 to identify and read the HCR setting. |
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181 */ |
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182 #define GPIO_PIN 0x00020000 |
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183 const HCR::TElementId KHcrKey_GpioPin_UART1_DSR = GPIO_PIN + 11; //< Serial DSR on RGB board |
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184 const HCR::TElementId KHcrKey_GpioPin_UART1_DTR = GPIO_PIN + 12; //< Serial DTR on RGB board |
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185 const HCR::TElementId KHcrKey_GpioPin_UART1_DCD = GPIO_PIN + 13; //< Serial DCD on RGB board |
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186 |
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187 const HCR::TElementId KHcrKey_GpioPin_CKERST = GPIO_PIN + 21; //< Line to FPGA |
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188 |
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189 const HCR::TElementId KHcrKey_GpioPin_CSI_CS42L51 = GPIO_PIN + 22; //< Line to CS42L51 |
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190 const HCR::TElementId KHcrKey_GpioPin_CSIa = GPIO_PIN + 23; //< Line to Test Pin Header |
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191 const HCR::TElementId KHcrKey_GpioPin_CSIb = GPIO_PIN + 24; //< Line to Test Pin Header |
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192 const HCR::TElementId KHcrKey_GpioPin_CSIc = GPIO_PIN + 25; //< Line to Test Pin Header |
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193 |
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194 const HCR::TElementId KHcrKey_GpioPin_PCIa = GPIO_PIN + 26; //< ExtBus Connector |
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195 const HCR::TElementId KHcrKey_GpioPin_PCIb = GPIO_PIN + 27; //< ExtBus Connector |
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196 const HCR::TElementId KHcrKey_GpioPin_PCIc = GPIO_PIN + 28; //< ExtBus Connector |
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197 |
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198 const HCR::TElementId KHcrKey_GpioPin_RGB = GPIO_PIN + 41; //< Line to FPGA |
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199 |
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200 const HCR::TElementId KHcrKey_GpioPin_eTRON = GPIO_PIN + 42; //< Line to FPGA |
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201 |
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202 const HCR::TElementId KHcrKey_GpioPin_LCDl = GPIO_PIN + 43; //< Line to FPGA |
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203 |
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204 const HCR::TElementId KHcrKey_GpioPin_RTC = GPIO_PIN + 44; //< Line to FPGA |
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205 |
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206 const HCR::TElementId KHcrKey_GpioPin_LINT20 = GPIO_PIN + 45; //< Line to FPGA |
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207 |
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208 const HCR::TElementId KHcrKey_GpioPin_AUDIO_RESET = GPIO_PIN + 46; //< CS42L51 codec reset line |
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209 |
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210 const HCR::TElementId KHcrKey_GpioPin_SWb0 = GPIO_PIN + 61; //< Line to FPGA |
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211 const HCR::TElementId KHcrKey_GpioPin_SWb1 = GPIO_PIN + 62; //< Line to FPGA |
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212 #undef GPIO_PIN |
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213 |
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214 |
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215 /** |
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216 HCR Settings identifing the I2S Bus Channels. |
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217 |
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218 These element keys are used along with the KHcrCat_MHA_I2S category UID |
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219 to identify and read the HCR setting. |
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220 */ |
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221 #define I2S_CHAN 0x00030000 |
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222 const HCR::TElementId KHcrKey_I2S_CS42L51 = I2S_CHAN + 11; //< Channel used with the Audio Codec |
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223 const HCR::TElementId KHcrKey_I2S_Reserved1 = I2S_CHAN + 12; //< |
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224 const HCR::TElementId KHcrKey_I2S_Reserved2 = I2S_CHAN + 13; //< |
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225 const HCR::TElementId KHcrKey_I2S_Reserved3 = I2S_CHAN + 14; //< |
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226 #undef I2S_CHAN |
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227 |
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228 |
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229 /** |
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230 HCR Settings identifing the I2C Bus IDs. |
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231 |
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232 These element keys are used along with the KHcrCat_MHA_I2C category UID |
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233 to identify and read the HCR setting. |
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234 */ |
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235 #define I2C_BUS 0x00040000 |
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236 const HCR::TElementId KHcrKey_I2C_ReservedA = I2C_BUS + 11; //< |
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237 const HCR::TElementId KHcrKey_I2C_ReservedB = I2C_BUS + 12; //< |
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238 #undef I2S_BUS |
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239 |
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240 |
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241 /** |
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242 HCR Settings identifing the SPI/CSI Bus Channels. |
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243 |
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244 These element keys are used along with the KHcrCat_MHA_SPI_CSI category UID |
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245 to identify and read the HCR setting. |
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246 */ |
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247 #define CSI_CHAN 0x00050000 |
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248 const HCR::TElementId KHcrKey_CSI_CS42L51 = CSI_CHAN + 11; //< |
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249 const HCR::TElementId KHcrKey_CSI_ReservedB = CSI_CHAN + 12; //< |
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250 #undef CSI_CHAN |
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251 |
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252 |
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253 #endif HCRCONFIG_MHA_H |
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254 |