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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * ne1_tb\specific\powerresources.h |
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16 * |
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17 */ |
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18 |
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19 |
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20 |
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21 #ifndef __POWERRESOURCES_H__ |
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22 #define __POWERRESOURCES_H__ |
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23 |
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24 /** Enumeration for static resource Id */ |
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25 enum ResourceId |
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26 { |
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27 /** Resource Id for I2S 0 MCLK Resource */ |
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28 ENE1_TBI2S0MclkResource = 1, |
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29 /** Resource Id for I2S 1 MCLK Resource */ |
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30 ENE1_TBI2S1MclkResource = 2, |
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31 /** Resource Id for I2S 2 MCLK Resource */ |
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32 ENE1_TBI2S2MclkResource = 3, |
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33 /** Resource Id for I2S 3 MCLK Resource */ |
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34 ENE1_TBI2S3MclkResource = 4, |
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35 /** Resource Id for I2S 0 SCLK Resource */ |
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36 ENE1_TBI2S0SclkResource = 5, |
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37 /** Resource Id for I2S 1 SCLK Resource */ |
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38 ENE1_TBI2S1SclkResource = 6, |
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39 /** Resource Id for I2S 2 SCLK Resource */ |
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40 ENE1_TBI2S2SclkResource = 7, |
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41 /** Resource Id for I2S 3 SCLK Resource */ |
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42 ENE1_TBI2S3SclkResource = 8, |
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43 /** Resource Id for CSI 0 clock Resource */ |
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44 ENE1_TBCSI0ClockResource = 9, |
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45 /** Resource Id for CSI 1 clock Resource */ |
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46 ENE1_TBCSI1ClockResource = 10, |
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47 /** Resource Id for Display DCLK Resource */ |
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48 ENE1_TBDisplayDclkResource = 11, |
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49 /** Resource Id for LCD Resource */ |
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50 ENE1_TBLcdResource = 12, |
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51 /** Resource Id for Board Power Resource */ |
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52 ENE1_TBBoardPowerResource = 13, |
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53 /** Resource Id for PCI Clock enable resource */ |
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54 ENE1_TBPCIClkResource = 14, |
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55 /** Add any new resource above this */ |
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56 EMaxResourceCount |
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57 }; |
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58 |
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59 |
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60 /** Resource name for board power.*/ |
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61 _LIT(KBoardPower, "NE1_TBBoardPower"); |
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62 |
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63 /** Resource name for LCD Power. */ |
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64 _LIT(KLcdPower, "NE1_TBLcdPower"); |
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65 |
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66 /** Resource name for PCI clock enable resource */ |
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67 _LIT(KPCIClk, "NE1_TBPCIClk"); |
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68 |
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69 /** Enumeration for binary resource |
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70 Possible values for board power and lcd power resource. |
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71 */ |
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72 enum EBinaryResPower |
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73 { |
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74 /** Power OFF */ |
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75 E_OFF, |
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76 /** Power ON */ |
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77 E_ON |
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78 }; |
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79 |
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80 /** Resource name for display Dclk */ |
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81 _LIT(KDisplayDclk, "NE1_TBDisplayDclk"); |
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82 |
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83 /** Enumeration of possible programmable divider for display DCLK */ |
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84 enum TDisplayDclk |
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85 { |
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86 /** 399MHz divide by 20 */ |
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87 EDisplayDclk19950KHz = 0, |
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88 /** 399MHz divide by 19 */ |
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89 EDisplayDclk21000KHz, |
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90 /** 399MHz divide by 18 */ |
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91 EDisplayDclk22166KHz, |
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92 /** 399MHz divide by 17 */ |
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93 EDisplayDclk23470KHz, |
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94 /** 399MHz divide by 16 */ |
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95 EDisplayDclk24937KHz, |
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96 /** 399MHz divide by 15 */ |
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97 EDisplayDclk26600KHz, |
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98 /** 399MHz divide by 14 */ |
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99 EDisplayDclk28500KHz, |
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100 /** 399MHz divide by 13 */ |
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101 EDisplayDclk30692KHz, |
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102 /** 399MHz divide by 12 */ |
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103 EDisplayDclk33250KHz, |
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104 /** 399MHz divide by 11 */ |
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105 EDisplayDclk36272KHz, |
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106 /** 399MHz divide by 10 */ |
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107 EDisplayDclk39900KHz, |
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108 /** 399MHz divide by 9 */ |
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109 EDisplayDclk44333KHz, |
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110 /** 399MHz divide by 8 */ |
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111 EDisplayDclk49875KHz, |
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112 /** 399MHz divide by 7 */ |
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113 EDisplayDclk57000KHz, |
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114 /** 399MHz divide by 6 */ |
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115 EDisplayDclk66500KHz, |
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116 /** 399MHz divide by 5 */ |
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117 EDisplayDclk79800KHz |
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118 }; |
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119 |
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120 /** Resource name for CSI 0 clock */ |
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121 _LIT(KCSI0Clock, "NE1_TBCSI0Clock"); |
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122 |
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123 /** Resource name for CSI 1 clock */ |
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124 _LIT(KCSI1Clock, "NE1_TBCSI1Clock"); |
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125 |
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126 /** Enumeration of possible frequency for CSI clock */ |
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127 enum TCSIClock |
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128 { |
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129 /** SCLK1 (slave mode) */ |
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130 ECSIClkSck1 = 0, |
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131 /** 1/512 PCLK frequency for CSI clock (master mode) */ |
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132 ECSIClk130KHz, |
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133 /** 1/256 PCLK frequency for CSI clock (master mode) */ |
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134 ECSIClk260KHz, |
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135 /** 1/128 PCLK frequency for CSI clock (master mode) */ |
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136 ECSIClk521KHz, |
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137 /** 1/64 PCLK frequency for CSI clock (master mode) */ |
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138 ECSIClk1040KHz, |
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139 /** 1/32 PCLK frequency for CSI clock (master mode) */ |
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140 ECSIClk2080KHz, |
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141 /** 1/16 PCLK frequency for CSI clock (master mode) */ |
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142 ECSIClk4170KHz, |
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143 /** 1/4 PCLK frequency for CSI clock (master mode) */ |
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144 ECSIClk16670KHz |
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145 }; |
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146 |
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147 /** Resource name for I2S0 MCLK */ |
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148 _LIT(KI2S0Mclk, "NE1_TBI2S0Mclk"); |
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149 /** Resource name for I2S1 MCLK */ |
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150 _LIT(KI2S1Mclk, "NE1_TBI2S1Mclk"); |
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151 /** Resource name for I2S2 MCLK */ |
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152 _LIT(KI2S2Mclk, "NE1_TBI2S2Mclk"); |
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153 /** Resource name for I2S3 MCLK */ |
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154 _LIT(KI2S3Mclk, "NE1_TBI2S3Mclk"); |
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155 |
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156 /** Enumeration of possible frequency for I2S MCLK */ |
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157 enum TI2SMclk |
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158 { |
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159 /** Enable MCLK masking */ |
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160 EI2SMclkMask = -1, |
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161 /** 36.864MHz MCLK frequency */ |
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162 EI2SMclk36864KHz = 0, |
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163 /** 24.576MHz MCLK frequency */ |
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164 EI2SMclk24576KHz = 1, |
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165 /** 18.432MHz MCLK frequency */ |
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166 EI2SMclk18432KHz = 2, |
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167 /** 33.8688MHz MCLK frequency */ |
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168 EI2SMclk33868KHz = 4, |
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169 /** 22.5792MHz MCLK frequency */ |
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170 EI2SMclk22579KHz = 5, |
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171 /** 16.9344MHz MCLK frequency */ |
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172 EI2SMclk16934KHz = 6 |
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173 }; |
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174 |
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175 /** Resource name for I2S0 SCLK */ |
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176 _LIT(KI2S0Sclk, "NE1_TBI2S0Sclk"); |
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177 /** Resource name for I2S1 SCLK */ |
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178 _LIT(KI2S1Sclk, "NE1_TBI2S1Sclk"); |
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179 /** Resource name for I2S2 SCLK */ |
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180 _LIT(KI2S2Sclk, "NE1_TBI2S2Sclk"); |
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181 /** Resource name for I2S3 SCLK */ |
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182 _LIT(KI2S3Sclk, "NE1_TBI2S3Sclk"); |
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183 |
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184 /** Enumeration of possible frequency for I2S SCLK */ |
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185 enum TI2SSclk |
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186 { |
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187 /** 8KHz Sampling frequency in master mode */ |
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188 EI2SSclk8000Hz = 0, |
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189 /** 12KHz Sampling frequency in master mode */ |
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190 EI2SSclk12000Hz = 1, |
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191 /** 16KHz Sampling frequency in master mode */ |
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192 EI2SSclk16000Hz = 2, |
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193 /** 24KHz Sampling frequency in master mode */ |
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194 EI2SSclk24000Hz = 3, |
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195 /** 32KHz Sampling frequency in master mode */ |
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196 EI2SSclk32000Hz = 4, |
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197 /** 48KHz Sampling frequency in master mode */ |
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198 EI2SSclk48000Hz = 5, |
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199 /** 11.025KHz Sampling frequency in master mode */ |
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200 EI2SSclk11025Hz = 8, |
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201 /** 22.05KHz Sampling frequency in master mode */ |
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202 EI2SSclk22050Hz = 9, |
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203 /** 44.1KHz Sampling frequency in master mode */ |
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204 EI2SSclk44100Hz = 10 |
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205 }; |
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206 |
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207 #endif //__POWERRESOURCES_H__ |
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208 |