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1 ; |
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2 ; Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 ; All rights reserved. |
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4 ; This component and the accompanying materials are made available |
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5 ; under the terms of "Eclipse Public License v1.0" |
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6 ; which accompanies this distribution, and is available |
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7 ; at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 ; |
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9 ; Initial Contributors: |
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10 ; Nokia Corporation - initial contribution. |
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11 ; |
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12 ; Contributors: |
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13 ; |
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14 ; Description: |
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15 ; ne1_tb\nandboot\coreldrasm.s |
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16 ; |
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17 |
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18 INCLUDE armcpudefs.inc ; Constants used by the MMU code |
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19 INCLUDE nand_plat.inc ; NAND device specifics |
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20 INCLUDE naviengine.inc |
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21 |
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22 EXPORT BootEntry |
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23 EXPORT GetRomTargetAddress |
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24 EXPORT GetSMRIBTargetAddress |
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25 EXPORT GetSMRTargetStartAddress |
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26 EXPORT GetSMRTargetMaxAddress |
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27 EXPORT clearRestartTimer |
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28 EXPORT RestartAuxiliaryCores |
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29 IF USE_MMU |
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30 IMPORT setupMMU |
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31 EXPORT GetPageTableBaseAddress |
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32 EXPORT GetMemoryBankArrayBase |
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33 EXPORT GetNumberOfMemoryBankAddresses |
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34 ELSE ; USE_MMU |
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35 ; NOT using MMU |
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36 IMPORT loadmain |
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37 EXPORT bootos |
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38 ENDIF ; USE_MMU |
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39 |
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40 EXPORT charout |
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41 EXPORT WriteW |
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42 |
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43 ;****************************************************************************** |
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44 ; Constants |
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45 |
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46 KHwSDramAddr EQU 0x80000000 |
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47 KSDramSizeDdr EQU 0x10000000 ; 256 MBytes |
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48 |
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49 |
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50 KSerial0PhysBase EQU 0x18034000 ; // must be same number as in ne1_tb.s |
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51 ;Serial Port Register Offsets |
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52 Serial_DLL EQU 0 |
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53 Serial_DLH EQU 4 |
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54 Serial_LCR EQU 0xc |
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55 Serial_THR EQU 0 |
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56 Serial_LSR EQU 0x14 |
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57 |
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58 ; KRomTargetAddress is the memory location where the core image will be |
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59 ; placed in RAM. |
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60 KRomTargetAddress EQU KHwSDramAddr ; Base of RAM |
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61 KSDramTopAddress EQU KHwSDramAddr + KSDramSizeDdr ; 0x90000000 |
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62 KSRTargetSize EQU 0x02000000 ; 32 Mb |
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63 KSRIBTargetAddress EQU KSDramTopAddress - KSRTargetSize ;0x8E000000 (Top of Ram - 0x02000000 (32 Mb)) |
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64 KSRIBTargetSize EQU 0x00001000 ; 4 Kb |
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65 KSRTargetStartAddress EQU KSRIBTargetAddress + KSRIBTargetSize ; 0x8E001000 (+4Kb) |
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66 KSRTargetMaxAddress EQU KSDramTopAddress |
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67 |
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68 ; define linker area for placement of .text section (LINKBASE) |
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69 ; also use PRESERVE8 to indicate (to linker) stack 8B alignment |
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70 |
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71 PRESERVE8 |
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72 AREA |Boot$$Code|, CODE, READONLY, ALIGN=6 |
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73 |
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74 ;****************************************************************************** |
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75 ; Entry point for the Core Loader |
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76 ; Note that this MUST be at the start of the image!!! |
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77 ;****************************************************************************** |
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78 BootEntry |
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79 |
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80 LDR r13, =KCoreldrStackAddr ; C code needs a stack |
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81 |
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82 bl PauseAuxiliaryCores |
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83 |
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84 ; This hardware reference platorm, NaviEngine, bootstraps the coreloader image from NAND and |
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85 ; has just started executing. Most of the hardware setup, such as configuring RAM, has |
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86 ; already been done by the bootloader. For systems that boot directly from the coreloader |
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87 ; image most of the hardware setup will need to be done here as it won't have been done |
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88 ; in bootoader code. |
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89 |
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90 BL InitUart |
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91 |
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92 IF USE_MMU |
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93 |
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94 b setupMMU |
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95 |
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96 ; Store the page tables after the coreloader on the next 128K boundary |
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97 KCoreLdrPDEAddress EQU ( ( _LINKBASE_ +0x00020000)) :AND: 0xfff20000 |
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98 |
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99 ; Format of table is, for each mapping region |
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100 ; virtual address, physical address, length of region (each these must be |
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101 ; megabyte aligned) the PDEs created will be for 1MB sections and so will cover |
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102 ; 1MB above the VA+length. |
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103 ; |
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104 ; A table with more elements would look like this |
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105 ; memoryTable DCD virtual_address1, physical_address1, length1 |
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106 ; DCD virtual_address2, physical_address2, length2 |
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107 ; DCD virtual_address3, physical_address3, length3 |
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108 ; |
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109 memoryTable DCD KHwSDramAddr, KHwSDramAddr, KSDramSizeDdr; Map all SDRAM |
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110 |
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111 GetPageTableBaseAddress |
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112 LDR r0,=KCoreLdrPDEAddress |
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113 __JUMP lr |
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114 |
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115 GetMemoryBankArrayBase |
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116 ADRL r0,memoryTable |
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117 __JUMP lr |
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118 |
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119 GetNumberOfMemoryBankAddresses |
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120 MOV r0,#1 ; 1 row only |
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121 __JUMP lr |
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122 |
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123 ELSE ; USE_MMU |
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124 ; NOT using MMU |
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125 |
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126 b loadmain ; jump directly into the NAND core loader without setting up the MMU |
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127 |
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128 ; bootos symbol needs defining if NOT using the MMU code |
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129 bootos |
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130 |
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131 BL RestartAuxiliaryCores |
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132 MOV pc, r0 ; jump off to OS |
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133 |
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134 ENDIF ; USE_MMU |
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135 |
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136 |
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137 GetRomTargetAddress |
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138 ldr r0, =KRomTargetAddress |
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139 __JUMP lr |
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140 |
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141 GetSMRIBTargetAddress |
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142 ldr r0, =KSRIBTargetAddress |
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143 __JUMP lr |
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144 |
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145 GetSMRTargetStartAddress |
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146 ldr r0, =KSRTargetStartAddress |
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147 __JUMP lr |
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148 |
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149 GetSMRTargetMaxAddress |
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150 ldr r0, =KSRTargetMaxAddress |
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151 __JUMP lr |
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152 |
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153 ;****************************************************************************** |
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154 ; writes character in r0 to the debug port |
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155 ;****************************************************************************** |
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156 charout |
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157 STMFD sp!, {r1,r2,lr} |
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158 LDR r1, =KSerial0PhysBase |
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159 |
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160 ; wait for debug port to be ready for data |
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161 1 |
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162 LDR r2, [r1, #Serial_LSR] |
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163 TST r2, #0x20 |
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164 BEQ %BT1 |
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165 |
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166 ; output character to debug port |
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167 STR r0, [r1, #Serial_THR] |
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168 |
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169 LDMFD sp!, {r1,r2,pc} |
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170 |
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171 ;****************************************************************************** |
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172 ; Printf("%0x", r0) a word to the serial port (stack required) |
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173 ; |
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174 ; Enter with |
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175 ; r0 = word |
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176 ; debug port initialised |
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177 ; |
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178 ; Leave with |
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179 ; no registers changed |
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180 ;****************************************************************************** |
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181 WriteW |
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182 STMFD sp!, {r0-r4, lr} |
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183 MOV r4, #28 |
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184 MOV r1, r0 |
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185 |
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186 1 MOV r0, r1, LSR r4 |
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187 AND r0, r0, #0x0000000F |
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188 CMP r0, #9 |
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189 ADDLE r0, r0, #48 |
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190 ADDGT r0, r0, #55 |
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191 BL charout |
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192 SUBS r4, r4, #4 |
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193 BGE %BT1 |
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194 |
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195 MOV r0, #' ' |
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196 BL charout |
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197 |
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198 LDMFD sp!, {r0-r4, pc} |
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199 |
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200 ;****************************************************************************** |
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201 ; Prepares and starts a timer |
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202 ; Preserves all registers |
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203 ; NOT SUPPORTED ON NAVIENGINE - SUPPLIED TO ALLOW COMPILE |
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204 ;****************************************************************************** |
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205 clearRestartTimer |
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206 MOV r0, lr |
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207 NOP |
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208 MOV pc, r0 |
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209 |
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210 ;****************************************************************************** |
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211 ; Initialise the serial port (stack required) |
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212 ; This is derived from the NaviEngine bootstrap's debug uart initialisation code. |
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213 ; Enter with : |
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214 ; none |
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215 ; Leave with : |
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216 ; no registers changed |
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217 ;****************************************************************************** |
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218 InitUart |
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219 MOV r0, lr |
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220 LDR r1, =KSerial0PhysBase |
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221 |
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222 ; set up debug port |
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223 MOV r2, #0x83 |
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224 STR r2, [r1, #Serial_LCR] |
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225 MOV r2, #KBaudRateDiv_default |
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226 STR r2, [r1, #Serial_DLL] |
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227 MOV r2, #0 |
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228 STR r2, [r1, #Serial_DLH] |
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229 MOV r2, #0x03 |
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230 STR r2, [r1, #Serial_LCR] |
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231 |
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232 MOV pc, r0 |
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233 |
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234 |
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235 |
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236 |
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237 |
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238 ;*************************************************************************************** |
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239 ; SMP code - PauseAuxiliaryCores |
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240 ; Expects lr and sp |
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241 ;*************************************************************************************** |
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242 PauseAuxiliaryCores |
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243 |
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244 |
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245 ; IF SMP |
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246 |
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247 ; Is this the boot processor ? |
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248 MRC p15, 0, r0, c0, c0, 5 |
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249 ANDS r0, r0, #0x0f ; r0 = CPU number 0-3 |
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250 BEQ IsBootProcessor ; Branch out if CPU 0 (= boot processor) |
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251 mov r10, r0 |
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252 ; No - this is an AP |
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253 |
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254 mov r5, r13 |
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255 add r13, r13, r10, lsl #2 ; Move to stack var for this core |
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256 mov r3, #10 |
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257 |
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258 1 |
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259 ldr r4, [r5] ; load message |
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260 teq r3,r4 ; is message r3? |
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261 streq r3, [r13] ; |
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262 addeq r3, r3, #1 |
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263 teq r3, #13 |
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264 beq Signaled |
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265 |
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266 nop |
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267 nop |
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268 nop |
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269 nop |
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270 |
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271 B %BA1 |
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272 |
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273 Signaled |
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274 |
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275 ldr pc, =KRomTargetAddress |
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276 |
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277 IsBootProcessor |
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278 add r13, r13, #16 ; reserve space on stack for signaling |
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279 mov pc, lr |
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280 |
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281 |
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282 |
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283 ;*************************************************************************************** |
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284 ; SMP code - RestartAuxiliaryCores |
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285 ; Expects lr, r0 - address to start cores at. |
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286 ; Corrupts r1-3 |
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287 ;*************************************************************************************** |
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288 |
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289 |
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290 RestartAuxiliaryCores |
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291 |
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292 ;KCoreldrStackAddr EQU 0x8C0003FC |
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293 |
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294 |
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295 ; This code wakes the other cores, causing them to run the image |
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296 |
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297 LDR r3, =KCoreldrStackAddr ; Find our origanal stack frame |
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298 mov r2 , #10 |
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299 1 |
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300 str r2, [r3] ; send r2 |
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301 |
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302 ldr r1, [r3, #4] ; read from core 1 |
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303 teq r1, r2 ; has it recieved? |
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304 bne %BA1 |
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305 |
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306 ldr r1, [r3, #8] ; read from core 2 |
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307 teq r1, r2 ; has it recieved? |
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308 bne %BA1 |
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309 |
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310 ldr r1, [r3, #12] ; read from core 3 |
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311 teq r1, r2 ; has it recieved? |
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312 bne %BA1 |
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313 |
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314 add r2,r2, #1 ; add 1 to our massage, and try agian |
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315 teq r2, #13 ; we repeat a few times, to make sure |
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316 bne %BA1 |
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317 |
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318 mov pc, lr |
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319 |
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320 END |