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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * ne1_tb\specific\variant.cia |
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16 * |
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17 */ |
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18 |
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19 |
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20 |
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21 #include <e32cia.h> |
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22 #include "variant.h" |
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23 #include "mconf.h" |
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24 |
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25 /****************************************************************************** |
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26 * Interrupt handling/dispatch |
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27 ******************************************************************************/ |
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28 __NAKED__ void XIntDispatch(TAny*) |
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29 { |
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30 // Service second-level Variant Interrupts |
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31 // Enter with r0->{Variant int controller base; Handlers;} |
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32 asm("stmfd sp!, {r4,lr} "); |
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33 asm("ldmia r0, {r3,r4} "); // r3=Variant interrupt controller base, r4->handlers |
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34 asm("0: "); |
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35 asm("ldr r0, [r3, #%a0]" : : "i" ((TInt)KHoIntContEnable)); // r0=bitmask with enabled interrupts |
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36 asm("ldr r1, [r3, #%a0]" : : "i" ((TInt)KHoIntContPending)); // r1=bitmask with pending interrupts |
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37 asm("mov r2, #31 "); // int id |
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38 asm("and r0, r0, r1 "); |
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39 asm("bics r0, r0, #0xf8000000 "); // mask unused bits (only 26 2nd-level ints defined) |
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40 asm("ldmeqfd sp!, {r4,pc} "); // if no 2nd level interrupts pending, exit |
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41 asm("cmp r0, #0x00010000 "); |
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42 asm("movcc r0, r0, lsl #16 "); |
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43 asm("subcc r2, r2, #16 "); |
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44 asm("cmp r0, #0x01000000 "); |
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45 asm("movcc r0, r0, lsl #8 "); |
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46 asm("subcc r2, r2, #8 "); |
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47 asm("cmp r0, #0x10000000 "); |
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48 asm("movcc r0, r0, lsl #4 "); |
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49 asm("subcc r2, r2, #4 "); |
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50 asm("cmp r0, #0x40000000 "); |
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51 asm("movcc r0, r0, lsl #2 "); |
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52 asm("subcc r2, r2, #2 "); |
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53 asm("cmp r0, #0x80000000 "); |
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54 asm("subcc r2, r2, #1 "); // r2=bit no. of MS 1 |
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55 asm("add r0, r4, r2, lsl #3 "); // r0->handler for this interrupt |
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56 asm("adr lr, 0b "); // look again after calling handler |
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57 asm("ldmia r0, {r0,pc} "); // jump to handler |
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58 } |
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59 |
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60 |
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61 extern "C" __NAKED__ void __arm_sev() |
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62 { |
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63 ARM_SEV; |
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64 __JUMP(, lr); |
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65 } |
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66 |
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67 __NAKED__ void __cpu_idle() |
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68 { |
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69 __DATA_SYNC_BARRIER_Z__(r1); |
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70 ARM_WFI; |
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71 __JUMP(,lr); |
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72 } |
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73 |
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74 #ifdef __SMP__ |
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75 __NAKED__ void __cache_off() |
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76 { |
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77 asm("stmfd sp!, {r4-r12,lr} "); |
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78 asm("ldr r7, __SCUAddr "); |
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79 asm("mov r8, #0 "); |
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80 __ASM_CLI(); |
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81 asm("bl cinvd "); // Clean and invalidate D cache |
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82 asm("mrc p15, 0, r0, c1, c0, 1 "); // get AUXCR |
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83 asm("bic r0, r0, #0x20 "); // clear SMP bit |
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84 asm("mcr p15, 0, r0, c1, c0, 1 "); |
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85 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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86 asm("mcr p15, 0, r8, c7, c5, 4 "); // ISB |
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87 asm("mrc p15, 0, r2, c0, c0, 5 "); // CPU number |
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88 asm("mov r2, r2, lsl #2 "); // *4 |
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89 asm("mov r3, #15 "); |
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90 asm("mov r3, r3, lsl r2 "); // r3 = 0x0f << (4*cpu#) |
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91 asm("str r3, [r7, #0x0C] "); // Invalidate SCU tags for this CPU |
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92 |
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93 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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94 asm("mcr p15, 0, r8, c7, c5, 4 "); // ISB |
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95 asm("mrc p15, 0, r0, c1, c0, 0 "); // get SCTLR |
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96 asm("bic r0, r0, #0x04 "); // disable D cache |
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97 asm("mcr p15, 0, r0, c1, c0, 0 "); |
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98 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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99 asm("mcr p15, 0, r8, c7, c5, 4 "); // ISB |
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100 asm("bl invd "); // Invalidate D cache |
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101 |
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102 asm("mrc p15, 0, r2, c0, c0, 5 "); // CPU number |
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103 asm("mov r2, r2, lsl #1 "); // *2 |
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104 asm("mov r3, #3 "); |
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105 asm("mov r3, r3, lsl r2 "); // r3 = 0x03 << (2*cpu#) |
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106 asm("ldr r1, [r7, #0x08] "); // SCU CPU status register |
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107 asm("orr r1, r1, r3 "); // set bits to 11 (power off mode) |
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108 asm("str r1, [r7, #0x08] "); |
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109 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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110 |
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111 asm("ldmfd sp!, {r4-r12,pc} "); |
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112 |
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113 asm("__SCUAddr: "); |
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114 asm(".word %a0" : : "i" ((TInt)KHwBaseSCU)); |
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115 |
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116 |
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117 // Clean and invalidate the D cache |
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118 // this code assumes number of sets is a multiple of 4 |
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119 // modifies r0-r6,r12 |
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120 asm("cinvd: "); |
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121 asm("mrc p15, 0, r0, c0, c0, 1 "); // r0 = cache type register |
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122 asm("mov r4, r0, lsr #12 "); |
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123 asm("mov r5, r0, lsr #15 "); |
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124 asm("mov r6, r0, lsr #18 "); |
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125 asm("and r4, r4, #3 "); // r4 = Dsize.len |
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126 asm("and r5, r5, #7 "); // r5 = Dsize.assoc |
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127 asm("and r6, r6, #15 "); // r6 = Dsize.size |
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128 asm("mov r2, #8 "); |
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129 asm("mov r2, r2, lsl r4 "); // r2 = D cache line length |
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130 asm("add r1, r6, #6 "); // r1 = Dsize.size + 6 = log2(size/8 bytes) |
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131 asm("sub r1, r1, r4 "); // r1 = log2(size/line length) |
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132 asm("mov r3, #1 "); |
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133 asm("mov r3, r3, lsl r1 "); // r3 = size in lines if M=0 |
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134 asm("add r1, r6, #9 "); // r1 = Dsize.size + 9 = log2(size bytes) |
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135 asm("sub r1, r1, r5 "); // r1 = log2(size/assoc) |
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136 asm("mov r12, #1 "); |
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137 asm("mov r1, r12, lsl r1 "); // r1 = way size |
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138 asm("mov r12, r12, ror r5 "); // r12 = 2^32>>floor(log2(assoc)) |
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139 asm("and r12, r12, #0xFF000000 "); // lose bit 0 if assoc=1 |
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140 asm("tst r0, #0x4000 "); // test Dsize.M |
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141 asm("addne r3, r3, r3, lsr #1 "); // multiply size by 1.5 if M=1 |
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142 asm("movne r12, r12, lsr #1 "); // 1 more bit for WAY field if M=1 |
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143 |
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144 // Have r2 = line length/bytes, r3 = cache size/lines |
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145 // r1 = size/assoc (=way size) |
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146 // r12 = iCleanAndInvalidatePtr=2^32 >> ceil(log2(assoc)) |
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147 |
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148 asm("mov r0, #0 "); // cache index |
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149 asm("1: "); |
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150 asm("mcr p15, 0, r0, c7, c14, 2 "); // CleanAndInvalidate line whose way/set index is in r0 |
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151 asm("add r0, r0, r2 "); // next line in way |
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152 asm("mcr p15, 0, r0, c7, c14, 2 "); // CleanAndInvalidate line whose way/set index is in r0 |
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153 asm("add r0, r0, r2 "); // next line in way |
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154 asm("mcr p15, 0, r0, c7, c14, 2 "); // CleanAndInvalidate line whose way/set index is in r0 |
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155 asm("add r0, r0, r2 "); // next line in way |
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156 asm("mcr p15, 0, r0, c7, c14, 2 "); // CleanAndInvalidate line whose way/set index is in r0 |
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157 asm("add r0, r0, r2 "); // next line in way |
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158 asm("tst r0, r1 "); // all lines in way done? |
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159 asm("bic r0, r0, r1 "); // clear set index |
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160 asm("addne r0, r0, r12 "); // if all lines in way done, next way |
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161 asm("subs r3, r3, #4 "); // 4 lines done |
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162 asm("bne 1b "); // loop through lines |
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163 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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164 __JUMP(, lr); |
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165 |
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166 // Invalidate the D cache |
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167 // this code assumes number of sets is a multiple of 4 |
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168 // modifies r0-r6,r12 |
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169 asm("invd: "); |
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170 asm("mrc p15, 0, r0, c0, c0, 1 "); // r0 = cache type register |
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171 asm("mov r4, r0, lsr #12 "); |
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172 asm("mov r5, r0, lsr #15 "); |
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173 asm("mov r6, r0, lsr #18 "); |
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174 asm("and r4, r4, #3 "); // r4 = Dsize.len |
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175 asm("and r5, r5, #7 "); // r5 = Dsize.assoc |
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176 asm("and r6, r6, #15 "); // r6 = Dsize.size |
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177 asm("mov r2, #8 "); |
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178 asm("mov r2, r2, lsl r4 "); // r2 = D cache line length |
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179 asm("add r1, r6, #6 "); // r1 = Dsize.size + 6 = log2(size/8 bytes) |
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180 asm("sub r1, r1, r4 "); // r1 = log2(size/line length) |
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181 asm("mov r3, #1 "); |
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182 asm("mov r3, r3, lsl r1 "); // r3 = size in lines if M=0 |
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183 asm("add r1, r6, #9 "); // r1 = Dsize.size + 9 = log2(size bytes) |
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184 asm("sub r1, r1, r5 "); // r1 = log2(size/assoc) |
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185 asm("mov r12, #1 "); |
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186 asm("mov r1, r12, lsl r1 "); // r1 = way size |
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187 asm("mov r12, r12, ror r5 "); // r12 = 2^32>>floor(log2(assoc)) |
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188 asm("and r12, r12, #0xFF000000 "); // lose bit 0 if assoc=1 |
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189 asm("tst r0, #0x4000 "); // test Dsize.M |
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190 asm("addne r3, r3, r3, lsr #1 "); // multiply size by 1.5 if M=1 |
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191 asm("movne r12, r12, lsr #1 "); // 1 more bit for WAY field if M=1 |
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192 |
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193 // Have r2 = line length/bytes, r3 = cache size/lines |
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194 // r1 = size/assoc (=way size) |
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195 // r12 = iCleanAndInvalidatePtr=2^32 >> ceil(log2(assoc)) |
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196 |
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197 asm("mov r0, #0 "); // cache index |
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198 asm("1: "); |
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199 asm("mcr p15, 0, r0, c7, c6, 2 "); // Invalidate line whose way/set index is in r0 |
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200 asm("add r0, r0, r2 "); // next line in way |
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201 asm("mcr p15, 0, r0, c7, c6, 2 "); // Invalidate line whose way/set index is in r0 |
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202 asm("add r0, r0, r2 "); // next line in way |
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203 asm("mcr p15, 0, r0, c7, c6, 2 "); // Invalidate line whose way/set index is in r0 |
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204 asm("add r0, r0, r2 "); // next line in way |
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205 asm("mcr p15, 0, r0, c7, c6, 2 "); // Invalidate line whose way/set index is in r0 |
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206 asm("add r0, r0, r2 "); // next line in way |
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207 asm("tst r0, r1 "); // all lines in way done? |
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208 asm("bic r0, r0, r1 "); // clear set index |
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209 asm("addne r0, r0, r12 "); // if all lines in way done, next way |
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210 asm("subs r3, r3, #4 "); // 4 lines done |
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211 asm("bne 1b "); // loop through lines |
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212 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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213 __JUMP(, lr); |
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214 } |
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215 |
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216 __NAKED__ void __cache_on() |
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217 { |
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218 asm("stmfd sp!, {r4-r12,lr} "); |
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219 asm("mov r8, #0 "); |
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220 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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221 asm("ldr r7, __SCUAddr "); |
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222 asm("mrc p15, 0, r2, c0, c0, 5 "); // CPU number |
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223 asm("mov r2, r2, lsl #1 "); // *2 |
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224 asm("mov r3, #3 "); |
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225 asm("mov r3, r3, lsl r2 "); // r3 = 0x03 << (2*cpu#) |
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226 asm("ldr r1, [r7, #0x08] "); // SCU CPU status register |
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227 asm("bic r1, r1, r3 "); // set bits to 00 (normal mode) |
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228 asm("str r1, [r7, #0x08] "); |
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229 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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230 asm("bl cinvd "); // Clean and invalidate D cache |
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231 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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232 asm("mcr p15, 0, r8, c7, c5, 4 "); // ISB |
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233 asm("mrc p15, 0, r0, c1, c0, 0 "); // get SCTLR |
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234 asm("orr r0, r0, #0x04 "); // enable D cache |
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235 asm("mcr p15, 0, r0, c1, c0, 0 "); |
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236 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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237 asm("mcr p15, 0, r8, c7, c5, 4 "); // ISB |
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238 asm("mrc p15, 0, r0, c1, c0, 1 "); // get AUXCR |
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239 asm("orr r0, r0, #0x20 "); // set SMP bit |
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240 asm("mcr p15, 0, r0, c1, c0, 1 "); |
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241 asm("mcr p15, 0, r8, c7, c10, 4 "); // DSB |
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242 asm("mcr p15, 0, r8, c7, c5, 4 "); // ISB |
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243 asm("ldmfd sp!, {r4-r12,pc} "); |
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244 } |
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245 #endif |