|
1 /* |
|
2 * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
|
3 * All rights reserved. |
|
4 * This component and the accompanying materials are made available |
|
5 * under the terms of "Eclipse Public License v1.0" |
|
6 * which accompanies this distribution, and is available |
|
7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
|
8 * |
|
9 * Initial Contributors: |
|
10 * Nokia Corporation - initial contribution. |
|
11 * |
|
12 * Contributors: |
|
13 * |
|
14 * Description: |
|
15 * |
|
16 */ |
|
17 |
|
18 // |
|
19 // TO DO: (mandatory) |
|
20 // |
|
21 // Add here a definition for your CPU (list in CONFIG.INC) |
|
22 // |
|
23 macro __CPU_ARM11MP__ |
|
24 // |
|
25 // TO DO: (mandatory) |
|
26 // |
|
27 // Add here a definition for your Memory Model |
|
28 // |
|
29 #define MM_MULTIPLE |
|
30 // |
|
31 // TO DO: (mandatory) |
|
32 // |
|
33 // Macro which generates the names for the binaries for this platform |
|
34 // |
|
35 #ifndef VariantTarget |
|
36 #define VariantTarget(name,ext) _ne1_tb_##name##.##ext |
|
37 #endif |
|
38 |
|
39 #ifndef VariantMediaDefIncludePath |
|
40 #define VariantMediaDefIncludePath SYMBIAN_OS_LAYER_PLATFORM_EXPORT_PATH(ne1_tb) |
|
41 #endif |
|
42 |
|
43 // Used in MMP files for include paths e.g. to hcrconfig.h header and others |
|
44 #ifndef VariantIncludePath |
|
45 #define VariantIncludePath SYMBIAN_BASE_SYSTEMINCLUDE(ne1_tb) |
|
46 #endif |
|
47 |
|
48 #ifndef AsspIncludePath |
|
49 #define AsspIncludePath SYMBIAN_ASSP_SYSTEMINCLUDE(naviengine) |
|
50 #endif |
|
51 |
|
52 |
|
53 //Include debug support |
|
54 macro __DEBUGGER_SUPPORT__ |
|
55 |
|
56 // |
|
57 // TO DO: |
|
58 // |
|
59 // If euser is built from the variant, uncomment the following line to build it |
|
60 // as ARM rather than Thumb |
|
61 // |
|
62 //#define __BUILD_VARIANT_EUSER_AS_ARM__ |
|
63 // |
|
64 // TO DO: (optional) |
|
65 // |
|
66 // To replace some of the generic utility functions with variant specific |
|
67 // versions (eg to replace memcpy with a version optimised for the hardware), |
|
68 // uncomment the two lines below and edit the files in the replacementUtils |
|
69 // directory. |
|
70 // |
|
71 //#define REPLACE_GENERIC_UTILS |
|
72 //#define VariantReplacementUtilsPath ne1_tb/replacement_utils |
|
73 // |
|
74 // TO DO: (optional) |
|
75 // |
|
76 // Enable BTrace support in release versions of the kernel by adding |
|
77 // the following BTRACE macro declarations |
|
78 // |
|
79 macro BTRACE_KERNEL_ALL |
|
80 // |
|
81 // TO DO: |
|
82 // |
|
83 // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor. |
|
84 // |
|
85 //#define __CPU_ARM1136_IS_R1__ |
|
86 // |
|
87 |
|
88 // Include the following line if default memory mapping should use shared memory. |
|
89 // Should be on for multicore (SMP) devices. |
|
90 |
|
91 macro __CPU_USE_SHARED_MEMORY |
|
92 |
|
93 // Include the following line if CPU cannot tolerate the presence of nonshared |
|
94 // cached memory. This seems to be the case for the ARM11 MPCore - corruption |
|
95 // of data is observed in non-shared cached regions if __CPU_USE_SHARED_MEMORY |
|
96 // is used. |
|
97 |
|
98 macro __CPU_FORCE_SHARED_MEMORY_IF_CACHED |
|
99 |
|
100 |
|
101 |
|
102 // TO DO: |
|
103 // |
|
104 // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973 |
|
105 // "CLREX instruction might be ignored during data cache line fill" |
|
106 // is fixed on this hardware. |
|
107 // |
|
108 //#define __CPU_ARM1136_ERRATUM_406973_FIXED |
|
109 |
|
110 // Uncomment next line if using the ARM1136 processor and ARM1136 Erratum 408022 |
|
111 // "Cancelled write to CONTEXTID register might update ASID" |
|
112 // is fixed on this hardware. |
|
113 // |
|
114 //#define __CPU_ARM1136_ERRATUM_408022_FIXED |
|
115 |
|
116 |
|
117 // Uncomment if: |
|
118 // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
|
119 // operation might fail to invalidate some lines if coincident with linefill" |
|
120 // is fixed on this hardware, or |
|
121 // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
|
122 // operation might fail to invalidate some lines if coincident with linefill |
|
123 // is fixed on this hardware. |
|
124 // Workaround: |
|
125 // 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
|
126 // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
|
127 // If this macro is enabled, it should be accompanied by: |
|
128 // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
|
129 // |
|
130 // #define __CPU_ARM1136_ERRATUM_411920_FIXED |
|
131 |
|
132 macro FAULTY_NONSHARED_DEVICE_MEMORY |
|
133 |
|
134 // SMP Timestamp uses inline code from BSP |
|
135 macro __NKERN_TIMESTAMP_USE_INLINE_BSP_CODE__ |
|
136 #define AsspNKernIncludePath SYMBIAN_OS_LAYER_PLATFORM_EXPORT_PATH(assp/naviengine/nkern) |
|
137 |
|
138 // FIQ can not be disabled on naviengine, tell kernel to ignore it... |
|
139 macro __FIQ_IS_UNCONTROLLED__ |
|
140 |
|
141 macro MONITOR_THREAD_CPU_TIME |
|
142 |
|
143 #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__) |
|
144 library VariantTarget(kanaviengine,lib) |
|
145 #endif |
|
146 |
|
147 // Include CrazyInterrupts support (changing CPU targets for following HW interrupts) |
|
148 // comment this macro - once SMP kernel is fully functional |
|
149 macro SMP_CRAZY_INTERRUPTS |
|
150 |
|
151 // Include VFP support |
|
152 macro __CPU_HAS_VFP |
|
153 #define USE_VFP_MATH |
|
154 |
|
155 // Include GPIO STATIC EXTENSION |
|
156 macro __USE_GPIO_STATIC_EXTENSION__ |
|
157 |