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1 // |
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2 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 // All rights reserved. |
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4 // This component and the accompanying materials are made available |
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5 // under the terms of "Eclipse Public License v1.0" |
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6 // which accompanies this distribution, and is available |
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7 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 // |
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9 // Initial Contributors: |
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10 // Nokia Corporation - initial contribution. |
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11 // |
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12 // Contributors: |
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13 // |
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14 // Description: |
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15 // |
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16 ////////////////////////////////////////////////////////////////////////////// |
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17 // |
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18 // This script will perform a full hardware initialisation of the NaviEngine board. |
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19 // |
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20 // Change History: |
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21 // |
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22 // 01/01/2008 1.0 : Initial version |
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23 // 08/05/2009 1.1 : Tidied up in readiness for putting into Nokia's distribution system |
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24 // |
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25 ////////////////////////////////////////////////////////////////////////////// |
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26 |
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27 &scriptversion=1.1 |
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28 |
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29 print "=======================================================================" |
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30 print "&Platform initialisation script version &scriptversion" |
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31 |
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32 ; Initialise system control coprocessor |
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33 print "Initialising system control coprocessor" |
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34 |
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35 ; <MCR|MRC> p15, <op1>, Rd, CRn, CRm, <op2> |
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36 ; BIT0-3:CRn |
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37 ; BIT4-7:CRm |
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38 ; BIT8-10:<op2> |
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39 ; BIT12-14:<op1> |
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40 |
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41 ;*CPU Init |
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42 ;*MMU/D-cache/I-cache disabled |
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43 ; c1, 0, c0, 0 |
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44 core 0 |
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45 d.s C15:0x0001 %LE %LONG 0x00054078 |
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46 core 1 |
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47 d.s C15:0x0001 %LE %LONG 0x00054078 |
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48 core 2 |
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49 d.s C15:0x0001 %LE %LONG 0x00054078 |
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50 core 3 |
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51 d.s C15:0x0001 %LE %LONG 0x00054078 |
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52 |
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53 ;*Invalidate both caches |
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54 ; c7, 0, c7, 0 |
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55 d.s C15:0x0077 %LE %LONG 0x0 |
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56 |
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57 ;*Invalidate TLBs |
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58 ; c8, 0, c7, 0 |
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59 d.s C15:0x0078 %LE %LONG 0x0 |
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60 |
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61 system.resettarget |
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62 print "Initialising bus controller and peripherals" |
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63 |
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64 ;*DDR2 Init |
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65 data.set sd:0x18021044 %LE %LONG 0x30022123 |
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66 data.set sd:0x18021058 %LE %LONG 0x00000001 |
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67 data.set sd:0x18021008 %LE %LONG 0x00000020 |
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68 |
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69 wait.1s |
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70 |
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71 ;*delay(Memo Register dummy write) |
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72 data.set sd:0x18037C0C %LE %LONG 0x00000000 |
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73 data.set sd:0x18021008 %LE %LONG 0x10000004 |
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74 data.set sd:0x18021008 %LE %LONG 0x00010002 |
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75 data.set sd:0x18021008 %LE %LONG 0x00018002 |
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76 data.set sd:0x18021008 %LE %LONG 0x00008002 |
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77 data.set sd:0x18021008 %LE %LONG 0X1D480002 |
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78 data.set sd:0x18021008 %LE %LONG 0x10000004 |
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79 data.set sd:0x18021008 %LE %LONG 0x00000001 |
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80 data.set sd:0x18021008 %LE %LONG 0x00000001 |
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81 |
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82 ;*delay(Memo Register dummy write) |
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83 data.set sd:0x18037C0C %LE %LONG 0x00000000 |
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84 data.set sd:0x18037C0C %LE %LONG 0x00000000 |
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85 data.set sd:0x18037C0C %LE %LONG 0x00000000 |
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86 data.set sd:0x18021008 %LE %LONG 0x19480002 |
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87 data.set sd:0x18021008 %LE %LONG 0x01308002 |
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88 data.set sd:0x18021008 %LE %LONG 0x00000100 |
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89 data.set sd:0x18021040 %LE %LONG 0x1485A912 |
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90 data.set sd:0x18021034 %LE %LONG 0x00000121 |
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91 |
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92 ;*SysCon Init |
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93 ;* .word 0x18037C80 %LE %LONG 0x007F0103 |
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94 data.set sd:0x18037C80 %LE %LONG 0x00000000 |
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95 |
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96 ;*ExBus Init |
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97 data.set sd:0x1801A000 %LE %LONG 0x0000004A |
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98 data.set sd:0x1801A004 %LE %LONG 0x08000049 |
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99 data.set sd:0x1801A008 %LE %LONG 0x0600004E |
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100 data.set sd:0x1801A00C %LE %LONG 0x0400004B |
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101 data.set sd:0x1801A010 %LE %LONG 0x1000004A |
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102 data.set sd:0x1801A014 %LE %LONG 0x1400000A |
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103 data.set sd:0x1801A020 %LE %LONG 0x10388E7F |
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104 data.set sd:0x1801A024 %LE %LONG 0x10388E7E |
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105 data.set sd:0x1801A028 %LE %LONG 0x10388E7E |
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106 data.set sd:0x1801A02C %LE %LONG 0x10388E7F |
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107 data.set sd:0x1801A030 %LE %LONG 0x10388E7E |
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108 data.set sd:0x1801A034 %LE %LONG 0x10388E7E |
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109 |
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110 ;*ExBus PCS5 UART-EX Init |
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111 d.s SD:0x14020003 %LE %BYTE 0x00 |
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112 d.s SD:0x14020001 %LE %BYTE 0x00 |
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113 d.s SD:0x14020002 %LE %BYTE 0x07 |
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114 d.s SD:0x14020003 %LE %BYTE 0x80 |
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115 d.s SD:0x14020000 %LE %BYTE 0x1E |
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116 d.s SD:0x14020001 %LE %BYTE 0x00 |
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117 d.s SD:0x14020003 %LE %BYTE 0x03 |
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118 d.s SD:0x14020004 %LE %BYTE 0x03 |
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119 |
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120 ;*ExBus PCS5 CharLED |
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121 d.s SD:0x14000000 %LE %BYTE 0x59 |
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122 d.s SD:0x14000001 %LE %BYTE 0x45 |
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123 d.s SD:0x14000002 %LE %BYTE 0x53 |
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124 d.s SD:0x14000003 %LE %BYTE 0x21 |
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125 d.s SD:0x14000004 %LE %BYTE 0x21 |
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126 d.s SD:0x14000005 %LE %BYTE 0x20 |
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127 d.s SD:0x14000006 %LE %BYTE 0x20 |
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128 d.s SD:0x14000007 %LE %BYTE 0x20 |
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129 |
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130 ;*ExBus PCS4 LED |
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131 d.s SD:0x10000030 %LE %WORD 0x00AA |
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132 |
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133 data.set sd:0x18037C14 %LE %LONG 0x00000000 |
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134 |
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135 enddo |
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136 |