/*

 * OMAP2 Display Subsystem.

 *

 * Copyright (C) 2008 Nokia Corporation

 * Written by Andrzej Zaborowski <andrew@openedhand.com>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 or

 * (at your option) version 3 of the License.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 */

#include "hw.h"

#include "console.h"

#include "omap.h"

struct omap_dss_s {

    qemu_irq irq;

    qemu_irq drq;

    DisplayState *state;

    int autoidle;

    int control;

    int enable;

    struct omap_dss_panel_s {

        int enable;

        int nx;

        int ny;

        int x;

        int y;

    } dig, lcd;

    struct {

        uint32_t idlemode;

        uint32_t irqst;

        uint32_t irqen;

        uint32_t control;

        uint32_t config;

        uint32_t capable;

        uint32_t timing[4];

        int line;

        uint32_t bg[2];

        uint32_t trans[2];

        struct omap_dss_plane_s {

            int enable;

            int bpp;

            int posx;

            int posy;

            int nx;

            int ny;

            target_phys_addr_t addr[3];

            uint32_t attr;

            uint32_t tresh;

            int rowinc;

            int colinc;

            int wininc;

        } l[3];

        int invalidate;

        uint16_t palette[256];

    } dispc;

    struct {

        int idlemode;

        uint32_t control;

        int enable;

        int pixels;

        int busy;

        int skiplines;

        uint16_t rxbuf;

        uint32_t config[2];

        uint32_t time[4];

        uint32_t data[6];

        uint16_t vsync;

        uint16_t hsync;

        struct rfbi_chip_s *chip[2];

    } rfbi;

};

static void omap_dispc_interrupt_update(struct omap_dss_s *s)

{

    qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen);

}

static void omap_rfbi_reset(struct omap_dss_s *s)

{

    s->rfbi.idlemode = 0;

    s->rfbi.control = 2;

    s->rfbi.enable = 0;

    s->rfbi.pixels = 0;

    s->rfbi.skiplines = 0;

    s->rfbi.busy = 0;

    s->rfbi.config[0] = 0x00310000;

    s->rfbi.config[1] = 0x00310000;

    s->rfbi.time[0] = 0;

    s->rfbi.time[1] = 0;

    s->rfbi.time[2] = 0;

    s->rfbi.time[3] = 0;

    s->rfbi.data[0] = 0;

    s->rfbi.data[1] = 0;

    s->rfbi.data[2] = 0;

    s->rfbi.data[3] = 0;

    s->rfbi.data[4] = 0;

    s->rfbi.data[5] = 0;

    s->rfbi.vsync = 0;

    s->rfbi.hsync = 0;

}

void omap_dss_reset(struct omap_dss_s *s)

{

    s->autoidle = 0;

    s->control = 0;

    s->enable = 0;

    s->dig.enable = 0;

    s->dig.nx = 1;

    s->dig.ny = 1;

    s->lcd.enable = 0;

    s->lcd.nx = 1;

    s->lcd.ny = 1;

    s->dispc.idlemode = 0;

    s->dispc.irqst = 0;

    s->dispc.irqen = 0;

    s->dispc.control = 0;

    s->dispc.config = 0;

    s->dispc.capable = 0x161;

    s->dispc.timing[0] = 0;

    s->dispc.timing[1] = 0;

    s->dispc.timing[2] = 0;

    s->dispc.timing[3] = 0;

    s->dispc.line = 0;

    s->dispc.bg[0] = 0;

    s->dispc.bg[1] = 0;

    s->dispc.trans[0] = 0;

    s->dispc.trans[1] = 0;

    s->dispc.l[0].enable = 0;

    s->dispc.l[0].bpp = 0;

    s->dispc.l[0].addr[0] = 0;

    s->dispc.l[0].addr[1] = 0;

    s->dispc.l[0].addr[2] = 0;

    s->dispc.l[0].posx = 0;

    s->dispc.l[0].posy = 0;

    s->dispc.l[0].nx = 1;

    s->dispc.l[0].ny = 1;

    s->dispc.l[0].attr = 0;

    s->dispc.l[0].tresh = 0;

    s->dispc.l[0].rowinc = 1;

    s->dispc.l[0].colinc = 1;

    s->dispc.l[0].wininc = 0;

    omap_rfbi_reset(s);

    omap_dispc_interrupt_update(s);

}

static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_dss_s *s = (struct omap_dss_s *) opaque;

    switch (addr) {

    case 0x00:	/* DSS_REVISIONNUMBER */

        return 0x20;

    case 0x10:	/* DSS_SYSCONFIG */

        return s->autoidle;

    case 0x14:	/* DSS_SYSSTATUS */

        return 1;						/* RESETDONE */

    case 0x40:	/* DSS_CONTROL */

        return s->control;

    case 0x50:	/* DSS_PSA_LCD_REG_1 */

    case 0x54:	/* DSS_PSA_LCD_REG_2 */

    case 0x58:	/* DSS_PSA_VIDEO_REG */

        /* TODO: fake some values when appropriate s->control bits are set */

        return 0;

    case 0x5c:	/* DSS_STATUS */

        return 1 + (s->control & 1);

    default:

        break;

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static void omap_diss_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_dss_s *s = (struct omap_dss_s *) opaque;

    switch (addr) {

    case 0x00:	/* DSS_REVISIONNUMBER */

    case 0x14:	/* DSS_SYSSTATUS */

    case 0x50:	/* DSS_PSA_LCD_REG_1 */

    case 0x54:	/* DSS_PSA_LCD_REG_2 */

    case 0x58:	/* DSS_PSA_VIDEO_REG */

    case 0x5c:	/* DSS_STATUS */

        OMAP_RO_REG(addr);

        break;

    case 0x10:	/* DSS_SYSCONFIG */

        if (value & 2)						/* SOFTRESET */

            omap_dss_reset(s);

        s->autoidle = value & 1;

        break;

    case 0x40:	/* DSS_CONTROL */

        s->control = value & 0x3dd;

        break;

    default:

        OMAP_BAD_REG(addr);

    }

}

static CPUReadMemoryFunc *omap_diss1_readfn[] = {

    omap_badwidth_read32,

    omap_badwidth_read32,

    omap_diss_read,

};

static CPUWriteMemoryFunc *omap_diss1_writefn[] = {

    omap_badwidth_write32,

    omap_badwidth_write32,

    omap_diss_write,

};

static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_dss_s *s = (struct omap_dss_s *) opaque;

    switch (addr) {

    case 0x000:	/* DISPC_REVISION */

        return 0x20;

    case 0x010:	/* DISPC_SYSCONFIG */

        return s->dispc.idlemode;

    case 0x014:	/* DISPC_SYSSTATUS */

        return 1;						/* RESETDONE */

    case 0x018:	/* DISPC_IRQSTATUS */

        return s->dispc.irqst;

    case 0x01c:	/* DISPC_IRQENABLE */

        return s->dispc.irqen;

    case 0x040:	/* DISPC_CONTROL */

        return s->dispc.control;

    case 0x044:	/* DISPC_CONFIG */

        return s->dispc.config;

    case 0x048:	/* DISPC_CAPABLE */

        return s->dispc.capable;

    case 0x04c:	/* DISPC_DEFAULT_COLOR0 */

        return s->dispc.bg[0];

    case 0x050:	/* DISPC_DEFAULT_COLOR1 */

        return s->dispc.bg[1];

    case 0x054:	/* DISPC_TRANS_COLOR0 */

        return s->dispc.trans[0];

    case 0x058:	/* DISPC_TRANS_COLOR1 */

        return s->dispc.trans[1];

    case 0x05c:	/* DISPC_LINE_STATUS */

        return 0x7ff;

    case 0x060:	/* DISPC_LINE_NUMBER */

        return s->dispc.line;

    case 0x064:	/* DISPC_TIMING_H */

        return s->dispc.timing[0];

    case 0x068:	/* DISPC_TIMING_V */

        return s->dispc.timing[1];

    case 0x06c:	/* DISPC_POL_FREQ */

        return s->dispc.timing[2];

    case 0x070:	/* DISPC_DIVISOR */

        return s->dispc.timing[3];

    case 0x078:	/* DISPC_SIZE_DIG */

        return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1);

    case 0x07c:	/* DISPC_SIZE_LCD */

        return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1);

    case 0x080:	/* DISPC_GFX_BA0 */

        return s->dispc.l[0].addr[0];

    case 0x084:	/* DISPC_GFX_BA1 */

        return s->dispc.l[0].addr[1];

    case 0x088:	/* DISPC_GFX_POSITION */

        return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx;

    case 0x08c:	/* DISPC_GFX_SIZE */

        return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1);

    case 0x0a0:	/* DISPC_GFX_ATTRIBUTES */

        return s->dispc.l[0].attr;

    case 0x0a4:	/* DISPC_GFX_FIFO_TRESHOLD */

        return s->dispc.l[0].tresh;

    case 0x0a8:	/* DISPC_GFX_FIFO_SIZE_STATUS */

        return 256;

    case 0x0ac:	/* DISPC_GFX_ROW_INC */

        return s->dispc.l[0].rowinc;

    case 0x0b0:	/* DISPC_GFX_PIXEL_INC */

        return s->dispc.l[0].colinc;

    case 0x0b4:	/* DISPC_GFX_WINDOW_SKIP */

        return s->dispc.l[0].wininc;

    case 0x0b8:	/* DISPC_GFX_TABLE_BA */

        return s->dispc.l[0].addr[2];

    case 0x0bc:	/* DISPC_VID1_BA0 */

    case 0x0c0:	/* DISPC_VID1_BA1 */

    case 0x0c4:	/* DISPC_VID1_POSITION */

    case 0x0c8:	/* DISPC_VID1_SIZE */

    case 0x0cc:	/* DISPC_VID1_ATTRIBUTES */

    case 0x0d0:	/* DISPC_VID1_FIFO_TRESHOLD */

    case 0x0d4:	/* DISPC_VID1_FIFO_SIZE_STATUS */

    case 0x0d8:	/* DISPC_VID1_ROW_INC */

    case 0x0dc:	/* DISPC_VID1_PIXEL_INC */

    case 0x0e0:	/* DISPC_VID1_FIR */

    case 0x0e4:	/* DISPC_VID1_PICTURE_SIZE */

    case 0x0e8:	/* DISPC_VID1_ACCU0 */

    case 0x0ec:	/* DISPC_VID1_ACCU1 */

    case 0x0f0 ... 0x140:	/* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */

    case 0x14c:	/* DISPC_VID2_BA0 */

    case 0x150:	/* DISPC_VID2_BA1 */

    case 0x154:	/* DISPC_VID2_POSITION */

    case 0x158:	/* DISPC_VID2_SIZE */

    case 0x15c:	/* DISPC_VID2_ATTRIBUTES */

    case 0x160:	/* DISPC_VID2_FIFO_TRESHOLD */

    case 0x164:	/* DISPC_VID2_FIFO_SIZE_STATUS */

    case 0x168:	/* DISPC_VID2_ROW_INC */

    case 0x16c:	/* DISPC_VID2_PIXEL_INC */

    case 0x170:	/* DISPC_VID2_FIR */

    case 0x174:	/* DISPC_VID2_PICTURE_SIZE */

    case 0x178:	/* DISPC_VID2_ACCU0 */

    case 0x17c:	/* DISPC_VID2_ACCU1 */

    case 0x180 ... 0x1d0:	/* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */

    case 0x1d4:	/* DISPC_DATA_CYCLE1 */

    case 0x1d8:	/* DISPC_DATA_CYCLE2 */

    case 0x1dc:	/* DISPC_DATA_CYCLE3 */

        return 0;

    default:

        break;

    }

    OMAP_BAD_REG(addr);

    return 0;

}

static void omap_disc_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_dss_s *s = (struct omap_dss_s *) opaque;

    switch (addr) {

    case 0x010:	/* DISPC_SYSCONFIG */

        if (value & 2)						/* SOFTRESET */

            omap_dss_reset(s);

        s->dispc.idlemode = value & 0x301b;

        break;

    case 0x018:	/* DISPC_IRQSTATUS */

        s->dispc.irqst &= ~value;

        omap_dispc_interrupt_update(s);

        break;

    case 0x01c:	/* DISPC_IRQENABLE */

        s->dispc.irqen = value & 0xffff;

        omap_dispc_interrupt_update(s);

        break;

    case 0x040:	/* DISPC_CONTROL */

        s->dispc.control = value & 0x07ff9fff;

        s->dig.enable = (value >> 1) & 1;

        s->lcd.enable = (value >> 0) & 1;

        if (value & (1 << 12))			/* OVERLAY_OPTIMIZATION */

            if (~((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1))

                 fprintf(stderr, "%s: Overlay Optimization when no overlay "

                                 "region effectively exists leads to "

                                 "unpredictable behaviour!\n", __FUNCTION__);

        if (value & (1 << 6)) {				/* GODIGITAL */

            /* XXX: Shadowed fields are:

             * s->dispc.config

             * s->dispc.capable

             * s->dispc.bg[0]

             * s->dispc.bg[1]

             * s->dispc.trans[0]

             * s->dispc.trans[1]

             * s->dispc.line

             * s->dispc.timing[0]

             * s->dispc.timing[1]

             * s->dispc.timing[2]

             * s->dispc.timing[3]

             * s->lcd.nx

             * s->lcd.ny

             * s->dig.nx

             * s->dig.ny

             * s->dispc.l[0].addr[0]

             * s->dispc.l[0].addr[1]

             * s->dispc.l[0].addr[2]

             * s->dispc.l[0].posx

             * s->dispc.l[0].posy

             * s->dispc.l[0].nx

             * s->dispc.l[0].ny

             * s->dispc.l[0].tresh

             * s->dispc.l[0].rowinc

             * s->dispc.l[0].colinc

             * s->dispc.l[0].wininc

             * All they need to be loaded here from their shadow registers.

             */

        }

        if (value & (1 << 5)) {				/* GOLCD */

             /* XXX: Likewise for LCD here.  */

        }

        s->dispc.invalidate = 1;

        break;

    case 0x044:	/* DISPC_CONFIG */

        s->dispc.config = value & 0x3fff;

        /* XXX:

         * bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded

         * bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded

         */

        s->dispc.invalidate = 1;

        break;

    case 0x048:	/* DISPC_CAPABLE */

        s->dispc.capable = value & 0x3ff;

        break;

    case 0x04c:	/* DISPC_DEFAULT_COLOR0 */

        s->dispc.bg[0] = value & 0xffffff;

        s->dispc.invalidate = 1;

        break;

    case 0x050:	/* DISPC_DEFAULT_COLOR1 */

        s->dispc.bg[1] = value & 0xffffff;

        s->dispc.invalidate = 1;

        break;

    case 0x054:	/* DISPC_TRANS_COLOR0 */

        s->dispc.trans[0] = value & 0xffffff;

        s->dispc.invalidate = 1;

        break;

    case 0x058:	/* DISPC_TRANS_COLOR1 */

        s->dispc.trans[1] = value & 0xffffff;

        s->dispc.invalidate = 1;

        break;

    case 0x060:	/* DISPC_LINE_NUMBER */

        s->dispc.line = value & 0x7ff;

        break;

    case 0x064:	/* DISPC_TIMING_H */

        s->dispc.timing[0] = value & 0x0ff0ff3f;

        break;

    case 0x068:	/* DISPC_TIMING_V */

        s->dispc.timing[1] = value & 0x0ff0ff3f;

        break;

    case 0x06c:	/* DISPC_POL_FREQ */

        s->dispc.timing[2] = value & 0x0003ffff;

        break;

    case 0x070:	/* DISPC_DIVISOR */

        s->dispc.timing[3] = value & 0x00ff00ff;

        break;

    case 0x078:	/* DISPC_SIZE_DIG */

        s->dig.nx = ((value >>  0) & 0x7ff) + 1;		/* PPL */

        s->dig.ny = ((value >> 16) & 0x7ff) + 1;		/* LPP */

        s->dispc.invalidate = 1;

        break;

    case 0x07c:	/* DISPC_SIZE_LCD */

        s->lcd.nx = ((value >>  0) & 0x7ff) + 1;		/* PPL */

        s->lcd.ny = ((value >> 16) & 0x7ff) + 1;		/* LPP */

        s->dispc.invalidate = 1;

        break;

    case 0x080:	/* DISPC_GFX_BA0 */

        s->dispc.l[0].addr[0] = (target_phys_addr_t) value;

        s->dispc.invalidate = 1;

        break;

    case 0x084:	/* DISPC_GFX_BA1 */

        s->dispc.l[0].addr[1] = (target_phys_addr_t) value;

        s->dispc.invalidate = 1;

        break;

    case 0x088:	/* DISPC_GFX_POSITION */

        s->dispc.l[0].posx = ((value >>  0) & 0x7ff);		/* GFXPOSX */

        s->dispc.l[0].posy = ((value >> 16) & 0x7ff);		/* GFXPOSY */

        s->dispc.invalidate = 1;

        break;

    case 0x08c:	/* DISPC_GFX_SIZE */

        s->dispc.l[0].nx = ((value >>  0) & 0x7ff) + 1;		/* GFXSIZEX */

        s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1;		/* GFXSIZEY */

        s->dispc.invalidate = 1;

        break;

    case 0x0a0:	/* DISPC_GFX_ATTRIBUTES */

        s->dispc.l[0].attr = value & 0x7ff;

        if (value & (3 << 9))

            fprintf(stderr, "%s: Big-endian pixel format not supported\n",

                            __FUNCTION__);

        s->dispc.l[0].enable = value & 1;

        s->dispc.l[0].bpp = (value >> 1) & 0xf;

        s->dispc.invalidate = 1;

        break;

    case 0x0a4:	/* DISPC_GFX_FIFO_TRESHOLD */

        s->dispc.l[0].tresh = value & 0x01ff01ff;

        break;

    case 0x0ac:	/* DISPC_GFX_ROW_INC */

        s->dispc.l[0].rowinc = value;

        s->dispc.invalidate = 1;

        break;

    case 0x0b0:	/* DISPC_GFX_PIXEL_INC */

        s->dispc.l[0].colinc = value;

        s->dispc.invalidate = 1;