/*

 *  SH4 translation

 *

 *  Copyright (c) 2005 Samuel Tardieu

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include <assert.h>

#define DEBUG_DISAS

#define SH4_DEBUG_DISAS

//#define SH4_SINGLE_STEP

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "tcg-op.h"

#include "qemu-common.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

typedef struct DisasContext {

    struct TranslationBlock *tb;

    target_ulong pc;

    uint32_t sr;

    uint32_t fpscr;

    uint16_t opcode;

    uint32_t flags;

    int bstate;

    int memidx;

    uint32_t delayed_pc;

    int singlestep_enabled;

    uint32_t features;

} DisasContext;

#if defined(CONFIG_USER_ONLY)

#define IS_USER(ctx) 1

#else

#define IS_USER(ctx) (!(ctx->sr & SR_MD))

#endif

enum {

    BS_NONE     = 0, /* We go out of the TB without reaching a branch or an

                      * exception condition

                      */

    BS_STOP     = 1, /* We want to stop translation for any reason */

    BS_BRANCH   = 2, /* We reached a branch condition     */

    BS_EXCP     = 3, /* We reached an exception condition */

};

/* global register indexes */

static TCGv_ptr cpu_env;

static TCGv cpu_gregs[24];

static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;

static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;

static TCGv cpu_pr, cpu_fpscr, cpu_fpul;

static TCGv cpu_fregs[32];

/* internal register indexes */

static TCGv cpu_flags, cpu_delayed_pc;

#include "gen-icount.h"

static void sh4_translate_init(void)

{

    int i;

    static int done_init = 0;

    static const char * const gregnames[24] = {

        "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",

        "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",

        "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",

        "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",

        "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"

    };

    static const char * const fregnames[32] = {

         "FPR0_BANK0",  "FPR1_BANK0",  "FPR2_BANK0",  "FPR3_BANK0",

         "FPR4_BANK0",  "FPR5_BANK0",  "FPR6_BANK0",  "FPR7_BANK0",

         "FPR8_BANK0",  "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",

        "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",

         "FPR0_BANK1",  "FPR1_BANK1",  "FPR2_BANK1",  "FPR3_BANK1",

         "FPR4_BANK1",  "FPR5_BANK1",  "FPR6_BANK1",  "FPR7_BANK1",

         "FPR8_BANK1",  "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",

        "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",

    };

    if (done_init)

        return;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    for (i = 0; i < 24; i++)

        cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                              offsetof(CPUState, gregs[i]),

                                              gregnames[i]);

    cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,

                                    offsetof(CPUState, pc), "PC");

    cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,

                                    offsetof(CPUState, sr), "SR");

    cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,

                                     offsetof(CPUState, ssr), "SSR");

    cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,

                                     offsetof(CPUState, spc), "SPC");

    cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,

                                     offsetof(CPUState, gbr), "GBR");

    cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,

                                     offsetof(CPUState, vbr), "VBR");

    cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,

                                     offsetof(CPUState, sgr), "SGR");

    cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,

                                     offsetof(CPUState, dbr), "DBR");

    cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,

                                      offsetof(CPUState, mach), "MACH");

    cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,

                                      offsetof(CPUState, macl), "MACL");

    cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,

                                    offsetof(CPUState, pr), "PR");

    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,

                                       offsetof(CPUState, fpscr), "FPSCR");

    cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,

                                      offsetof(CPUState, fpul), "FPUL");

    cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,

				       offsetof(CPUState, flags), "_flags_");

    cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,

					    offsetof(CPUState, delayed_pc),

					    "_delayed_pc_");

    for (i = 0; i < 32; i++)

        cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                              offsetof(CPUState, fregs[i]),

                                              fregnames[i]);

    /* register helpers */

#define GEN_HELPER 2

#include "helper.h"

    done_init = 1;

}

void cpu_dump_state(CPUState * env, FILE * f,

		    int (*cpu_fprintf) (FILE * f, const char *fmt, ...),

		    int flags)

{

    int i;

    cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",

		env->pc, env->sr, env->pr, env->fpscr);

    cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",

		env->spc, env->ssr, env->gbr, env->vbr);

    cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",

		env->sgr, env->dbr, env->delayed_pc, env->fpul);

    for (i = 0; i < 24; i += 4) {

	cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",

		    i, env->gregs[i], i + 1, env->gregs[i + 1],

		    i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);

    }

    if (env->flags & DELAY_SLOT) {

	cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",

		    env->delayed_pc);

    } else if (env->flags & DELAY_SLOT_CONDITIONAL) {

	cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",

		    env->delayed_pc);

    }

}

static void cpu_sh4_reset(CPUSH4State * env)

{

#if defined(CONFIG_USER_ONLY)

    env->sr = 0;

#else

    env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;

#endif

    env->vbr = 0;

    env->pc = 0xA0000000;

#if defined(CONFIG_USER_ONLY)

    env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */

    set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */

#else

    env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */

    set_float_rounding_mode(float_round_to_zero, &env->fp_status);

#endif

    env->mmucr = 0;

}

typedef struct {

    const char *name;

    int id;

    uint32_t pvr;

    uint32_t prr;

    uint32_t cvr;

    uint32_t features;

} sh4_def_t;

static sh4_def_t sh4_defs[] = {

    {

	.name = "SH7750R",

	.id = SH_CPU_SH7750R,

	.pvr = 0x00050000,

	.prr = 0x00000100,

	.cvr = 0x00110000,

    }, {

	.name = "SH7751R",

	.id = SH_CPU_SH7751R,

	.pvr = 0x04050005,

	.prr = 0x00000113,

	.cvr = 0x00110000,	/* Neutered caches, should be 0x20480000 */

    }, {

	.name = "SH7785",

	.id = SH_CPU_SH7785,

	.pvr = 0x10300700,

	.prr = 0x00000200,

	.cvr = 0x71440211,

	.features = SH_FEATURE_SH4A,

     },

};

static const sh4_def_t *cpu_sh4_find_by_name(const char *name)

{

    int i;

    if (strcasecmp(name, "any") == 0)

	return &sh4_defs[0];

    for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)

	if (strcasecmp(name, sh4_defs[i].name) == 0)

	    return &sh4_defs[i];

    return NULL;

}

void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))

{

    int i;

    for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)

	(*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);

}

static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)

{

    env->pvr = def->pvr;

    env->prr = def->prr;

    env->cvr = def->cvr;

    env->id = def->id;

}

CPUSH4State *cpu_sh4_init(const char *cpu_model)

{

    CPUSH4State *env;

    const sh4_def_t *def;

    def = cpu_sh4_find_by_name(cpu_model);

    if (!def)

	return NULL;

    env = qemu_mallocz(sizeof(CPUSH4State));

    if (!env)

	return NULL;

    env->features = def->features;

    cpu_exec_init(env);

    sh4_translate_init();

    env->cpu_model_str = cpu_model;

    cpu_sh4_reset(env);

    cpu_sh4_register(env, def);

    tlb_flush(env, 1);

    return env;

}

static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)

{

    TranslationBlock *tb;

    tb = ctx->tb;

    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&

	!ctx->singlestep_enabled) {

	/* Use a direct jump if in same page and singlestep not enabled */

        tcg_gen_goto_tb(n);

        tcg_gen_movi_i32(cpu_pc, dest);

        tcg_gen_exit_tb((long) tb + n);

    } else {

        tcg_gen_movi_i32(cpu_pc, dest);

        if (ctx->singlestep_enabled)

            gen_helper_debug();

        tcg_gen_exit_tb(0);

    }

}

static void gen_jump(DisasContext * ctx)

{

    if (ctx->delayed_pc == (uint32_t) - 1) {

	/* Target is not statically known, it comes necessarily from a

	   delayed jump as immediate jump are conditinal jumps */

	tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);

	if (ctx->singlestep_enabled)

	    gen_helper_debug();

	tcg_gen_exit_tb(0);

    } else {

	gen_goto_tb(ctx, 0, ctx->delayed_pc);

    }

}

static inline void gen_branch_slot(uint32_t delayed_pc, int t)

{

    TCGv sr;

    int label = gen_new_label();

    tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);

    sr = tcg_temp_new();

    tcg_gen_andi_i32(sr, cpu_sr, SR_T);

    tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);

    tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);

    gen_set_label(label);

}

/* Immediate conditional jump (bt or bf) */

static void gen_conditional_jump(DisasContext * ctx,

				 target_ulong ift, target_ulong ifnott)

{

    int l1;

    TCGv sr;

    l1 = gen_new_label();

    sr = tcg_temp_new();

    tcg_gen_andi_i32(sr, cpu_sr, SR_T);

    tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);

    gen_goto_tb(ctx, 0, ifnott);

    gen_set_label(l1);

    gen_goto_tb(ctx, 1, ift);

}

/* Delayed conditional jump (bt or bf) */

static void gen_delayed_conditional_jump(DisasContext * ctx)

{

    int l1;

    TCGv ds;

    l1 = gen_new_label();

    ds = tcg_temp_new();

    tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);

    tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);

    gen_goto_tb(ctx, 1, ctx->pc + 2);

    gen_set_label(l1);

    tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);

    gen_jump(ctx);

}

static inline void gen_set_t(void)

{

    tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);

}

static inline void gen_clr_t(void)

{

    tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);

}

static inline void gen_cmp(int cond, TCGv t0, TCGv t1)

{

    int label1 = gen_new_label();

    int label2 = gen_new_label();

    tcg_gen_brcond_i32(cond, t1, t0, label1);

    gen_clr_t();

    tcg_gen_br(label2);

    gen_set_label(label1);

    gen_set_t();

    gen_set_label(label2);

}

static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)

{

    int label1 = gen_new_label();

    int label2 = gen_new_label();

    tcg_gen_brcondi_i32(cond, t0, imm, label1);

    gen_clr_t();

    tcg_gen_br(label2);

    gen_set_label(label1);

    gen_set_t();

    gen_set_label(label2);

}

static inline void gen_store_flags(uint32_t flags)

{

    tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);

    tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);

}

static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)

{

    TCGv tmp = tcg_temp_new();

    p0 &= 0x1f;

    p1 &= 0x1f;

    tcg_gen_andi_i32(tmp, t1, (1 << p1));

    tcg_gen_andi_i32(t0, t0, ~(1 << p0));

    if (p0 < p1)

        tcg_gen_shri_i32(tmp, tmp, p1 - p0);

    else if (p0 > p1)

        tcg_gen_shli_i32(tmp, tmp, p0 - p1);

    tcg_gen_or_i32(t0, t0, tmp);

    tcg_temp_free(tmp);

}

static inline void gen_load_fpr64(TCGv_i64 t, int reg)

{

    tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);

}

static inline void gen_store_fpr64 (TCGv_i64 t, int reg)

{

    TCGv_i32 tmp = tcg_temp_new_i32();

    tcg_gen_trunc_i64_i32(tmp, t);

    tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);

    tcg_gen_shri_i64(t, t, 32);

    tcg_gen_trunc_i64_i32(tmp, t);

    tcg_gen_mov_i32(cpu_fregs[reg], tmp);

    tcg_temp_free_i32(tmp);

}

#define B3_0 (ctx->opcode & 0xf)

#define B6_4 ((ctx->opcode >> 4) & 0x7)

#define B7_4 ((ctx->opcode >> 4) & 0xf)

#define B7_0 (ctx->opcode & 0xff)

#define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))

#define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \

  (ctx->opcode & 0xfff))

#define B11_8 ((ctx->opcode >> 8) & 0xf)

#define B15_12 ((ctx->opcode >> 12) & 0xf)

#define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \

		(cpu_gregs[x + 16]) : (cpu_gregs[x]))

#define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \

		? (cpu_gregs[x + 16]) : (cpu_gregs[x]))

#define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))

#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))

#define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))

#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */

#define CHECK_NOT_DELAY_SLOT \

  if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))     \

  {                                                           \

      tcg_gen_movi_i32(cpu_pc, ctx->pc-2);                    \

      gen_helper_raise_slot_illegal_instruction();            \

      ctx->bstate = BS_EXCP;                                  \

      return;                                                 \

  }

#define CHECK_PRIVILEGED                                      \

  if (IS_USER(ctx)) {                                         \

      tcg_gen_movi_i32(cpu_pc, ctx->pc);                      \

      gen_helper_raise_illegal_instruction();                 \

      ctx->bstate = BS_EXCP;                                  \

      return;                                                 \

  }

#define CHECK_FPU_ENABLED                                       \

  if (ctx->flags & SR_FD) {                                     \

      if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \

          tcg_gen_movi_i32(cpu_pc, ctx->pc-2);                  \

          gen_helper_raise_slot_fpu_disable();                  \

      } else {                                                  \

          tcg_gen_movi_i32(cpu_pc, ctx->pc);                    \

          gen_helper_raise_fpu_disable();                       \

      }                                                         \

      ctx->bstate = BS_EXCP;                                    \

      return;                                                   \

  }

static void _decode_opc(DisasContext * ctx)

{

#if 0

    fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);

#endif

    switch (ctx->opcode) {

    case 0x0019:		/* div0u */

	tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));

	return;

    case 0x000b:		/* rts */

	CHECK_NOT_DELAY_SLOT

	tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x0028:		/* clrmac */

	tcg_gen_movi_i32(cpu_mach, 0);

	tcg_gen_movi_i32(cpu_macl, 0);

	return;

    case 0x0048:		/* clrs */

	tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);

	return;

    case 0x0008:		/* clrt */

	gen_clr_t();

	return;

    case 0x0038:		/* ldtlb */

	CHECK_PRIVILEGED

	gen_helper_ldtlb();

	return;

    case 0x002b:		/* rte */

	CHECK_PRIVILEGED

	CHECK_NOT_DELAY_SLOT

	tcg_gen_mov_i32(cpu_sr, cpu_ssr);

	tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);

	ctx->flags |= DELAY_SLOT;

	ctx->delayed_pc = (uint32_t) - 1;

	return;

    case 0x0058:		/* sets */

	tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);