/*

 * USB UHCI controller emulation

 *

 * Copyright (c) 2005 Fabrice Bellard

 *

 * Copyright (c) 2008 Max Krasnyansky

 *     Magor rewrite of the UHCI data structures parser and frame processor

 *     Support for fully async operation and multiple outstanding transactions

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "hw.h"

#include "usb.h"

#include "pci.h"

#include "qemu-timer.h"

//#define DEBUG

//#define DEBUG_DUMP_DATA

#define UHCI_CMD_FGR      (1 << 4)

#define UHCI_CMD_EGSM     (1 << 3)

#define UHCI_CMD_GRESET   (1 << 2)

#define UHCI_CMD_HCRESET  (1 << 1)

#define UHCI_CMD_RS       (1 << 0)

#define UHCI_STS_HCHALTED (1 << 5)

#define UHCI_STS_HCPERR   (1 << 4)

#define UHCI_STS_HSERR    (1 << 3)

#define UHCI_STS_RD       (1 << 2)

#define UHCI_STS_USBERR   (1 << 1)

#define UHCI_STS_USBINT   (1 << 0)

#define TD_CTRL_SPD     (1 << 29)

#define TD_CTRL_ERROR_SHIFT  27

#define TD_CTRL_IOS     (1 << 25)

#define TD_CTRL_IOC     (1 << 24)

#define TD_CTRL_ACTIVE  (1 << 23)

#define TD_CTRL_STALL   (1 << 22)

#define TD_CTRL_BABBLE  (1 << 20)

#define TD_CTRL_NAK     (1 << 19)

#define TD_CTRL_TIMEOUT (1 << 18)

#define UHCI_PORT_RESET (1 << 9)

#define UHCI_PORT_LSDA  (1 << 8)

#define UHCI_PORT_ENC   (1 << 3)

#define UHCI_PORT_EN    (1 << 2)

#define UHCI_PORT_CSC   (1 << 1)

#define UHCI_PORT_CCS   (1 << 0)

#define FRAME_TIMER_FREQ 1000

#define FRAME_MAX_LOOPS  100

#define NB_PORTS 2

#ifdef DEBUG

#define dprintf printf

const char *pid2str(int pid)

{

    switch (pid) {

    case USB_TOKEN_SETUP: return "SETUP";

    case USB_TOKEN_IN:    return "IN";

    case USB_TOKEN_OUT:   return "OUT";

    }

    return "?";

}

#else

#define dprintf(...)

#endif

#ifdef DEBUG_DUMP_DATA

static void dump_data(const uint8_t *data, int len)

{

    int i;

    printf("uhci: data: ");

    for(i = 0; i < len; i++)

        printf(" %02x", data[i]);

    printf("\n");

}

#else

static void dump_data(const uint8_t *data, int len) {}

#endif

/* 

 * Pending async transaction.

 * 'packet' must be the first field because completion

 * handler does "(UHCIAsync *) pkt" cast.

 */

typedef struct UHCIAsync {

    USBPacket packet;

    struct UHCIAsync *next;

    uint32_t  td;

    uint32_t  token;

    int8_t    valid;

    uint8_t   done;

    uint8_t   buffer[2048];

} UHCIAsync;

typedef struct UHCIPort {

    USBPort port;

    uint16_t ctrl;

} UHCIPort;

typedef struct UHCIState {

    PCIDevice dev;

    uint16_t cmd; /* cmd register */

    uint16_t status;

    uint16_t intr; /* interrupt enable register */

    uint16_t frnum; /* frame number */

    uint32_t fl_base_addr; /* frame list base address */

    uint8_t sof_timing;

    uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */

    QEMUTimer *frame_timer;

    UHCIPort ports[NB_PORTS];

    /* Interrupts that should be raised at the end of the current frame.  */

    uint32_t pending_int_mask;

    /* Active packets */

    UHCIAsync *async_pending;

    UHCIAsync *async_pool;

} UHCIState;

typedef struct UHCI_TD {

    uint32_t link;

    uint32_t ctrl; /* see TD_CTRL_xxx */

    uint32_t token;

    uint32_t buffer;

} UHCI_TD;

typedef struct UHCI_QH {

    uint32_t link;

    uint32_t el_link;

} UHCI_QH;

static UHCIAsync *uhci_async_alloc(UHCIState *s)

{

    UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));

    if (async) {

        memset(&async->packet, 0, sizeof(async->packet));

        async->valid = 0;

        async->td    = 0;

        async->token = 0;

        async->done  = 0;

        async->next  = NULL;

    }

    return async;

}

static void uhci_async_free(UHCIState *s, UHCIAsync *async)

{

    qemu_free(async);

}

static void uhci_async_link(UHCIState *s, UHCIAsync *async)

{

    async->next = s->async_pending;

    s->async_pending = async;

}

static void uhci_async_unlink(UHCIState *s, UHCIAsync *async)

{

    UHCIAsync *curr = s->async_pending;

    UHCIAsync **prev = &s->async_pending;

    while (curr) {

	if (curr == async) {

            *prev = curr->next;

            return;

        }

        prev = &curr->next;

        curr = curr->next;

    }

}

static void uhci_async_cancel(UHCIState *s, UHCIAsync *async)

{

    dprintf("uhci: cancel td 0x%x token 0x%x done %u\n",

           async->td, async->token, async->done);

    if (!async->done)

        usb_cancel_packet(&async->packet);

    uhci_async_free(s, async);

}

/*

 * Mark all outstanding async packets as invalid.

 * This is used for canceling them when TDs are removed by the HCD.

 */

static UHCIAsync *uhci_async_validate_begin(UHCIState *s)

{

    UHCIAsync *async = s->async_pending;

    while (async) {

        async->valid--;

        async = async->next;

    }

    return NULL;

}

/*

 * Cancel async packets that are no longer valid

 */

static void uhci_async_validate_end(UHCIState *s)

{

    UHCIAsync *curr = s->async_pending;

    UHCIAsync **prev = &s->async_pending;

    UHCIAsync *next;

    while (curr) {

        if (curr->valid > 0) {

            prev = &curr->next;

            curr = curr->next;

            continue;

        }

        next = curr->next;

        /* Unlink */

        *prev = next;

        uhci_async_cancel(s, curr);

        curr = next;

    }

}

static void uhci_async_cancel_all(UHCIState *s)

{

    UHCIAsync *curr = s->async_pending;

    UHCIAsync *next;

    while (curr) {

        next = curr->next;

        uhci_async_cancel(s, curr);

        curr = next;

    }

    s->async_pending = NULL;

}

static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)

{

    UHCIAsync *async = s->async_pending;

    UHCIAsync *match = NULL;

    int count = 0;

    /*

     * We're looking for the best match here. ie both td addr and token.

     * Otherwise we return last good match. ie just token.

     * It's ok to match just token because it identifies the transaction

     * rather well, token includes: device addr, endpoint, size, etc.

     *

     * Also since we queue async transactions in reverse order by returning

     * last good match we restores the order.

     *

     * It's expected that we wont have a ton of outstanding transactions.

     * If we ever do we'd want to optimize this algorithm.

     */

    while (async) {

        if (async->token == token) {

            /* Good match */

            match = async;

            if (async->td == addr) {

                /* Best match */

                break;

            }

        }

        async = async->next;

        count++;

    }

    if (count > 64)

	fprintf(stderr, "uhci: warning lots of async transactions\n");

    return match;

}

static void uhci_attach(USBPort *port1, USBDevice *dev);

static void uhci_update_irq(UHCIState *s)

{

    int level;

    if (((s->status2 & 1) && (s->intr & (1 << 2))) ||

        ((s->status2 & 2) && (s->intr & (1 << 3))) ||

        ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||

        ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||

        (s->status & UHCI_STS_HSERR) ||

        (s->status & UHCI_STS_HCPERR)) {

        level = 1;

    } else {

        level = 0;

    }

    qemu_set_irq(s->dev.irq[3], level);

}

static void uhci_reset(UHCIState *s)

{

    uint8_t *pci_conf;

    int i;

    UHCIPort *port;

    dprintf("uhci: full reset\n");

    pci_conf = s->dev.config;

    pci_conf[0x6a] = 0x01; /* usb clock */

    pci_conf[0x6b] = 0x00;

    s->cmd = 0;

    s->status = 0;

    s->status2 = 0;

    s->intr = 0;

    s->fl_base_addr = 0;

    s->sof_timing = 64;

    for(i = 0; i < NB_PORTS; i++) {

        port = &s->ports[i];

        port->ctrl = 0x0080;

        if (port->port.dev)

            uhci_attach(&port->port, port->port.dev);

    }

    uhci_async_cancel_all(s);

}

static void uhci_save(QEMUFile *f, void *opaque)

{

    UHCIState *s = opaque;

    uint8_t num_ports = NB_PORTS;

    int i;

    uhci_async_cancel_all(s);

    pci_device_save(&s->dev, f);

    qemu_put_8s(f, &num_ports);

    for (i = 0; i < num_ports; ++i)

        qemu_put_be16s(f, &s->ports[i].ctrl);

    qemu_put_be16s(f, &s->cmd);

    qemu_put_be16s(f, &s->status);

    qemu_put_be16s(f, &s->intr);

    qemu_put_be16s(f, &s->frnum);

    qemu_put_be32s(f, &s->fl_base_addr);

    qemu_put_8s(f, &s->sof_timing);

    qemu_put_8s(f, &s->status2);

    qemu_put_timer(f, s->frame_timer);

}

static int uhci_load(QEMUFile *f, void *opaque, int version_id)

{

    UHCIState *s = opaque;

    uint8_t num_ports;

    int i, ret;

    if (version_id > 1)

        return -EINVAL;

    ret = pci_device_load(&s->dev, f);

    if (ret < 0)

        return ret;

    qemu_get_8s(f, &num_ports);

    if (num_ports != NB_PORTS)

        return -EINVAL;

    for (i = 0; i < num_ports; ++i)

        qemu_get_be16s(f, &s->ports[i].ctrl);

    qemu_get_be16s(f, &s->cmd);

    qemu_get_be16s(f, &s->status);

    qemu_get_be16s(f, &s->intr);

    qemu_get_be16s(f, &s->frnum);

    qemu_get_be32s(f, &s->fl_base_addr);

    qemu_get_8s(f, &s->sof_timing);

    qemu_get_8s(f, &s->status2);

    qemu_get_timer(f, s->frame_timer);

    return 0;

}

static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)

{

    UHCIState *s = opaque;

    addr &= 0x1f;

    switch(addr) {

    case 0x0c:

        s->sof_timing = val;

        break;

    }

}

static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)

{

    UHCIState *s = opaque;

    uint32_t val;

    addr &= 0x1f;

    switch(addr) {

    case 0x0c:

        val = s->sof_timing;

        break;

    default:

        val = 0xff;

        break;

    }

    return val;

}

static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)

{

    UHCIState *s = opaque;

    addr &= 0x1f;

    dprintf("uhci: writew port=0x%04x val=0x%04x\n", addr, val);

    switch(addr) {

    case 0x00:

        if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {

            /* start frame processing */

            qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock));

            s->status &= ~UHCI_STS_HCHALTED;

        } else if (!(val & UHCI_CMD_RS)) {

            s->status |= UHCI_STS_HCHALTED;

        }

        if (val & UHCI_CMD_GRESET) {

            UHCIPort *port;

            USBDevice *dev;

            int i;

            /* send reset on the USB bus */

            for(i = 0; i < NB_PORTS; i++) {

                port = &s->ports[i];

                dev = port->port.dev;

                if (dev) {

                    usb_send_msg(dev, USB_MSG_RESET);

                }

            }

            uhci_reset(s);

            return;

        }

        if (val & UHCI_CMD_HCRESET) {

            uhci_reset(s);

            return;

        }

        s->cmd = val;

        break;

    case 0x02:

        s->status &= ~val;

        /* XXX: the chip spec is not coherent, so we add a hidden

           register to distinguish between IOC and SPD */

        if (val & UHCI_STS_USBINT)

            s->status2 = 0;

        uhci_update_irq(s);

        break;

    case 0x04:

        s->intr = val;

        uhci_update_irq(s);

        break;

    case 0x06:

        if (s->status & UHCI_STS_HCHALTED)

            s->frnum = val & 0x7ff;

        break;

    case 0x10 ... 0x1f:

        {

            UHCIPort *port;

            USBDevice *dev;

            int n;

            n = (addr >> 1) & 7;

            if (n >= NB_PORTS)

                return;

            port = &s->ports[n];

            dev = port->port.dev;

            if (dev) {

                /* port reset */

                if ( (val & UHCI_PORT_RESET) &&

                     !(port->ctrl & UHCI_PORT_RESET) ) {

                    usb_send_msg(dev, USB_MSG_RESET);

                }

            }

            port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb);

            /* some bits are reset when a '1' is written to them */

            port->ctrl &= ~(val & 0x000a);

        }

        break;

    }

}

static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)

{

    UHCIState *s = opaque;

    uint32_t val;

    addr &= 0x1f;

    switch(addr) {

    case 0x00:

        val = s->cmd;

        break;

    case 0x02:

        val = s->status;

        break;

    case 0x04: