/*

   SPARC translation

   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>

   Copyright (C) 2003-2005 Fabrice Bellard

   This library is free software; you can redistribute it and/or

   modify it under the terms of the GNU Lesser General Public

   License as published by the Free Software Foundation; either

   version 2 of the License, or (at your option) any later version.

   This library is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public

   License along with this library; if not, write to the Free Software

   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "helper.h"

#include "tcg-op.h"

#define GEN_HELPER 1

#include "helper.h"

#define DEBUG_DISAS

#define DYNAMIC_PC  1 /* dynamic pc value */

#define JUMP_PC     2 /* dynamic pc value which takes only two values

                         according to jump_pc[T2] */

/* global register indexes */

static TCGv_ptr cpu_env, cpu_regwptr;

static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;

static TCGv_i32 cpu_psr;

static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];

static TCGv cpu_y;

#ifndef CONFIG_USER_ONLY

static TCGv cpu_tbr;

#endif

static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;

#ifdef TARGET_SPARC64

static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;

static TCGv cpu_gsr;

static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;

static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;

static TCGv_i32 cpu_softint;

#else

static TCGv cpu_wim;

#endif

/* local register indexes (only used inside old micro ops) */

static TCGv cpu_tmp0;

static TCGv_i32 cpu_tmp32;

static TCGv_i64 cpu_tmp64;

/* Floating point registers */

static TCGv_i32 cpu_fpr[TARGET_FPREGS];

#include "gen-icount.h"

typedef struct DisasContext {

    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */

    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */

    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */

    int is_br;

    int mem_idx;

    int fpu_enabled;

    int address_mask_32bit;

    struct TranslationBlock *tb;

    sparc_def_t *def;

} DisasContext;

// This function uses non-native bit order

#define GET_FIELD(X, FROM, TO) \

  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))

// This function uses the order in the manuals, i.e. bit 0 is 2^0

#define GET_FIELD_SP(X, FROM, TO) \

    GET_FIELD(X, 31 - (TO), 31 - (FROM))

#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)

#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))

#ifdef TARGET_SPARC64

#define FFPREG(r) (r)

#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))

#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))

#else

#define FFPREG(r) (r)

#define DFPREG(r) (r & 0x1e)

#define QFPREG(r) (r & 0x1c)

#endif

#define UA2005_HTRAP_MASK 0xff

#define V8_TRAP_MASK 0x7f

static int sign_extend(int x, int len)

{

    len = 32 - len;

    return (x << len) >> len;

}

#define IS_IMM (insn & (1<<13))

/* floating point registers moves */

static void gen_op_load_fpr_DT0(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.lower));

}

static void gen_op_load_fpr_DT1(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +

                   offsetof(CPU_DoubleU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +

                   offsetof(CPU_DoubleU, l.lower));

}

static void gen_op_store_DT0_fpr(unsigned int dst)

{

    tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.upper));

    tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.lower));

}

static void gen_op_load_fpr_QT0(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upmost));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lower));

    tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lowest));

}

static void gen_op_load_fpr_QT1(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.upmost));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.lower));

    tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.lowest));

}

static void gen_op_store_QT0_fpr(unsigned int dst)

{

    tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upmost));

    tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upper));

    tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lower));

    tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lowest));

}

/* moves */

#ifdef CONFIG_USER_ONLY

#define supervisor(dc) 0

#ifdef TARGET_SPARC64

#define hypervisor(dc) 0

#endif

#else

#define supervisor(dc) (dc->mem_idx >= 1)

#ifdef TARGET_SPARC64

#define hypervisor(dc) (dc->mem_idx == 2)

#else

#endif

#endif

#ifdef TARGET_SPARC64

#ifndef TARGET_ABI32

#define AM_CHECK(dc) ((dc)->address_mask_32bit)

#else

#define AM_CHECK(dc) (1)

#endif

#endif

static inline void gen_address_mask(DisasContext *dc, TCGv addr)

{

#ifdef TARGET_SPARC64

    if (AM_CHECK(dc))

        tcg_gen_andi_tl(addr, addr, 0xffffffffULL);

#endif

}

static inline void gen_movl_reg_TN(int reg, TCGv tn)

{

    if (reg == 0)

        tcg_gen_movi_tl(tn, 0);

    else if (reg < 8)

        tcg_gen_mov_tl(tn, cpu_gregs[reg]);

    else {

        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

    }

}

static inline void gen_movl_TN_reg(int reg, TCGv tn)

{

    if (reg == 0)

        return;

    else if (reg < 8)

        tcg_gen_mov_tl(cpu_gregs[reg], tn);

    else {

        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

    }

}

static inline void gen_goto_tb(DisasContext *s, int tb_num,

                               target_ulong pc, target_ulong npc)

{

    TranslationBlock *tb;

    tb = s->tb;

    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&

        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {

        /* jump to same page: we can use a direct jump */

        tcg_gen_goto_tb(tb_num);

        tcg_gen_movi_tl(cpu_pc, pc);

        tcg_gen_movi_tl(cpu_npc, npc);

        tcg_gen_exit_tb((long)tb + tb_num);

    } else {

        /* jump to another page: currently not optimized */

        tcg_gen_movi_tl(cpu_pc, pc);

        tcg_gen_movi_tl(cpu_npc, npc);

        tcg_gen_exit_tb(0);

    }

}

// XXX suboptimal

static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_cc_clear_icc(void)

{

    tcg_gen_movi_i32(cpu_psr, 0);

}

#ifdef TARGET_SPARC64

static inline void gen_cc_clear_xcc(void)

{

    tcg_gen_movi_i32(cpu_xcc, 0);

}

#endif

/* old op:

    if (!T0)

        env->psr |= PSR_ZERO;

    if ((int32_t) T0 < 0)

        env->psr |= PSR_NEG;

*/

static inline void gen_cc_NZ_icc(TCGv dst)

{

    TCGv r_temp;

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    r_temp = tcg_temp_new();

    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);

    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);

    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);

    gen_set_label(l1);

    tcg_gen_ext32s_tl(r_temp, dst);

    tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);

    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);

    gen_set_label(l2);

    tcg_temp_free(r_temp);

}

#ifdef TARGET_SPARC64

static inline void gen_cc_NZ_xcc(TCGv dst)

{

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);

    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);

    gen_set_label(l1);

    tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);

    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);

    gen_set_label(l2);

}

#endif

/* old op:

    if (T0 < src1)

        env->psr |= PSR_CARRY;

*/

static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)

{

    TCGv r_temp1, r_temp2;

    int l1;

    l1 = gen_new_label();

    r_temp1 = tcg_temp_new();

    r_temp2 = tcg_temp_new();

    tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);

    tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);

    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);

    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);

    gen_set_label(l1);

    tcg_temp_free(r_temp1);

    tcg_temp_free(r_temp2);

}

#ifdef TARGET_SPARC64

static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)

{

    int l1;

    l1 = gen_new_label();

    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);

    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);

    gen_set_label(l1);

}

#endif

/* old op:

    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))

        env->psr |= PSR_OVF;

*/

static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)

{

    TCGv r_temp;

    r_temp = tcg_temp_new();

    tcg_gen_xor_tl(r_temp, src1, src2);

    tcg_gen_not_tl(r_temp, r_temp);

    tcg_gen_xor_tl(cpu_tmp0, src1, dst);

    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);

    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);

    tcg_temp_free(r_temp);

    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);

}

#ifdef TARGET_SPARC64

static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)

{

    TCGv r_temp;

    r_temp = tcg_temp_new();

    tcg_gen_xor_tl(r_temp, src1, src2);

    tcg_gen_not_tl(r_temp, r_temp);

    tcg_gen_xor_tl(cpu_tmp0, src1, dst);

    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));

    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);

    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);

    tcg_temp_free(r_temp);

    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);

}

#endif

static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)

{

    TCGv r_temp;

    TCGv_i32 r_const;

    int l1;

    l1 = gen_new_label();

    r_temp = tcg_temp_new();

    tcg_gen_xor_tl(r_temp, src1, src2);

    tcg_gen_not_tl(r_temp, r_temp);

    tcg_gen_xor_tl(cpu_tmp0, src1, dst);

    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);

    r_const = tcg_const_i32(TT_TOVF);

    gen_helper_raise_exception(r_const);

    tcg_temp_free_i32(r_const);

    gen_set_label(l1);

    tcg_temp_free(r_temp);

}

static inline void gen_cc_V_tag(TCGv src1, TCGv src2)

{

    int l1;

    l1 = gen_new_label();

    tcg_gen_or_tl(cpu_tmp0, src1, src2);

    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);

    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);

    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);

    gen_set_label(l1);

}

static inline void gen_tag_tv(TCGv src1, TCGv src2)

{

    int l1;

    TCGv_i32 r_const;

    l1 = gen_new_label();

    tcg_gen_or_tl(cpu_tmp0, src1, src2);

    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);

    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);

    r_const = tcg_const_i32(TT_TOVF);

    gen_helper_raise_exception(r_const);

    tcg_temp_free_i32(r_const);

    gen_set_label(l1);

}

static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    gen_cc_clear_icc();

    gen_cc_NZ_icc(cpu_cc_dst);

    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

#ifdef TARGET_SPARC64

    gen_cc_clear_xcc();

    gen_cc_NZ_xcc(cpu_cc_dst);

    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

#endif

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    gen_mov_reg_C(cpu_tmp0, cpu_psr);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);

    gen_cc_clear_icc();

    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

#ifdef TARGET_SPARC64

    gen_cc_clear_xcc();

    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

#endif

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);

    gen_cc_NZ_icc(cpu_cc_dst);

    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

#ifdef TARGET_SPARC64

    gen_cc_NZ_xcc(cpu_cc_dst);

    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

#endif

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    gen_cc_clear_icc();

    gen_cc_NZ_icc(cpu_cc_dst);

    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);

#ifdef TARGET_SPARC64

    gen_cc_clear_xcc();

    gen_cc_NZ_xcc(cpu_cc_dst);

    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

#endif

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    gen_tag_tv(cpu_cc_src, cpu_cc_src2);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    gen_cc_clear_icc();

    gen_cc_NZ_icc(cpu_cc_dst);

    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

#ifdef TARGET_SPARC64

    gen_cc_clear_xcc();

    gen_cc_NZ_xcc(cpu_cc_dst);

    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

#endif

    tcg_gen_mov_tl(dst, cpu_cc_dst);