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1 /* |
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2 * QEMU Crystal CS4231 audio chip emulation |
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3 * |
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4 * Copyright (c) 2006 Fabrice Bellard |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "audiodev.h" |
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26 #include "audio/audio.h" |
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27 #include "isa.h" |
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28 #include "qemu-timer.h" |
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29 |
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30 /* |
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31 Missing features: |
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32 ADC |
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33 Loopback |
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34 Timer |
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35 ADPCM |
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36 More... |
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37 */ |
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38 |
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39 /* #define DEBUG */ |
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40 /* #define DEBUG_XLAW */ |
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41 |
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42 static struct { |
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43 int irq; |
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44 int dma; |
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45 int port; |
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46 int aci_counter; |
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47 } conf = {9, 3, 0x534, 1}; |
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48 |
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49 #ifdef DEBUG |
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50 #define dolog(...) AUD_log ("cs4231a", __VA_ARGS__) |
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51 #else |
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52 #define dolog(...) |
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53 #endif |
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54 |
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55 #define lwarn(...) AUD_log ("cs4231a", "warning: " __VA_ARGS__) |
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56 #define lerr(...) AUD_log ("cs4231a", "error: " __VA_ARGS__) |
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57 |
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58 #define CS_REGS 16 |
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59 #define CS_DREGS 32 |
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60 |
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61 typedef struct CSState { |
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62 QEMUSoundCard card; |
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63 qemu_irq *pic; |
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64 uint32_t regs[CS_REGS]; |
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65 uint8_t dregs[CS_DREGS]; |
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66 int irq; |
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67 int dma; |
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68 int port; |
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69 int shift; |
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70 int dma_running; |
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71 int audio_free; |
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72 int transferred; |
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73 int aci_counter; |
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74 SWVoiceOut *voice; |
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75 int16_t *tab; |
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76 } CSState; |
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77 |
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78 #define IO_READ_PROTO(name) \ |
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79 static uint32_t name (void *opaque, uint32_t addr) |
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80 |
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81 #define IO_WRITE_PROTO(name) \ |
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82 static void name (void *opaque, uint32_t addr, uint32_t val) |
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83 |
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84 #define GET_SADDR(addr) (addr & 3) |
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85 |
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86 #define MODE2 (1 << 6) |
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87 #define MCE (1 << 6) |
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88 #define PMCE (1 << 4) |
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89 #define CMCE (1 << 5) |
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90 #define TE (1 << 6) |
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91 #define PEN (1 << 0) |
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92 #define INT (1 << 0) |
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93 #define IEN (1 << 1) |
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94 #define PPIO (1 << 6) |
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95 #define PI (1 << 4) |
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96 #define CI (1 << 5) |
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97 #define TI (1 << 6) |
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98 |
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99 enum { |
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100 Index_Address, |
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101 Index_Data, |
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102 Status, |
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103 PIO_Data |
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104 }; |
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105 |
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106 enum { |
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107 Left_ADC_Input_Control, |
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108 Right_ADC_Input_Control, |
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109 Left_AUX1_Input_Control, |
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110 Right_AUX1_Input_Control, |
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111 Left_AUX2_Input_Control, |
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112 Right_AUX2_Input_Control, |
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113 Left_DAC_Output_Control, |
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114 Right_DAC_Output_Control, |
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115 FS_And_Playback_Data_Format, |
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116 Interface_Configuration, |
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117 Pin_Control, |
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118 Error_Status_And_Initialization, |
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119 MODE_And_ID, |
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120 Loopback_Control, |
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121 Playback_Upper_Base_Count, |
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122 Playback_Lower_Base_Count, |
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123 Alternate_Feature_Enable_I, |
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124 Alternate_Feature_Enable_II, |
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125 Left_Line_Input_Control, |
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126 Right_Line_Input_Control, |
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127 Timer_Low_Base, |
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128 Timer_High_Base, |
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129 RESERVED, |
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130 Alternate_Feature_Enable_III, |
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131 Alternate_Feature_Status, |
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132 Version_Chip_ID, |
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133 Mono_Input_And_Output_Control, |
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134 RESERVED_2, |
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135 Capture_Data_Format, |
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136 RESERVED_3, |
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137 Capture_Upper_Base_Count, |
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138 Capture_Lower_Base_Count |
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139 }; |
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140 |
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141 static int freqs[2][8] = { |
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142 { 8000, 16000, 27420, 32000, -1, -1, 48000, 9000 }, |
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143 { 5510, 11025, 18900, 22050, 37800, 44100, 33075, 6620 } |
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144 }; |
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145 |
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146 /* Tables courtesy http://hazelware.luggle.com/tutorials/mulawcompression.html */ |
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147 static int16_t MuLawDecompressTable[256] = |
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148 { |
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149 -32124,-31100,-30076,-29052,-28028,-27004,-25980,-24956, |
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150 -23932,-22908,-21884,-20860,-19836,-18812,-17788,-16764, |
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151 -15996,-15484,-14972,-14460,-13948,-13436,-12924,-12412, |
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152 -11900,-11388,-10876,-10364, -9852, -9340, -8828, -8316, |
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153 -7932, -7676, -7420, -7164, -6908, -6652, -6396, -6140, |
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154 -5884, -5628, -5372, -5116, -4860, -4604, -4348, -4092, |
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155 -3900, -3772, -3644, -3516, -3388, -3260, -3132, -3004, |
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156 -2876, -2748, -2620, -2492, -2364, -2236, -2108, -1980, |
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157 -1884, -1820, -1756, -1692, -1628, -1564, -1500, -1436, |
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158 -1372, -1308, -1244, -1180, -1116, -1052, -988, -924, |
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159 -876, -844, -812, -780, -748, -716, -684, -652, |
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160 -620, -588, -556, -524, -492, -460, -428, -396, |
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161 -372, -356, -340, -324, -308, -292, -276, -260, |
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162 -244, -228, -212, -196, -180, -164, -148, -132, |
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163 -120, -112, -104, -96, -88, -80, -72, -64, |
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164 -56, -48, -40, -32, -24, -16, -8, 0, |
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165 32124, 31100, 30076, 29052, 28028, 27004, 25980, 24956, |
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166 23932, 22908, 21884, 20860, 19836, 18812, 17788, 16764, |
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167 15996, 15484, 14972, 14460, 13948, 13436, 12924, 12412, |
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168 11900, 11388, 10876, 10364, 9852, 9340, 8828, 8316, |
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169 7932, 7676, 7420, 7164, 6908, 6652, 6396, 6140, |
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170 5884, 5628, 5372, 5116, 4860, 4604, 4348, 4092, |
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171 3900, 3772, 3644, 3516, 3388, 3260, 3132, 3004, |
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172 2876, 2748, 2620, 2492, 2364, 2236, 2108, 1980, |
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173 1884, 1820, 1756, 1692, 1628, 1564, 1500, 1436, |
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174 1372, 1308, 1244, 1180, 1116, 1052, 988, 924, |
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175 876, 844, 812, 780, 748, 716, 684, 652, |
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176 620, 588, 556, 524, 492, 460, 428, 396, |
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177 372, 356, 340, 324, 308, 292, 276, 260, |
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178 244, 228, 212, 196, 180, 164, 148, 132, |
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179 120, 112, 104, 96, 88, 80, 72, 64, |
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180 56, 48, 40, 32, 24, 16, 8, 0 |
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181 }; |
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182 |
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183 static int16_t ALawDecompressTable[256] = |
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184 { |
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185 -5504, -5248, -6016, -5760, -4480, -4224, -4992, -4736, |
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186 -7552, -7296, -8064, -7808, -6528, -6272, -7040, -6784, |
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187 -2752, -2624, -3008, -2880, -2240, -2112, -2496, -2368, |
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188 -3776, -3648, -4032, -3904, -3264, -3136, -3520, -3392, |
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189 -22016,-20992,-24064,-23040,-17920,-16896,-19968,-18944, |
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190 -30208,-29184,-32256,-31232,-26112,-25088,-28160,-27136, |
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191 -11008,-10496,-12032,-11520,-8960, -8448, -9984, -9472, |
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192 -15104,-14592,-16128,-15616,-13056,-12544,-14080,-13568, |
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193 -344, -328, -376, -360, -280, -264, -312, -296, |
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194 -472, -456, -504, -488, -408, -392, -440, -424, |
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195 -88, -72, -120, -104, -24, -8, -56, -40, |
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196 -216, -200, -248, -232, -152, -136, -184, -168, |
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197 -1376, -1312, -1504, -1440, -1120, -1056, -1248, -1184, |
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198 -1888, -1824, -2016, -1952, -1632, -1568, -1760, -1696, |
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199 -688, -656, -752, -720, -560, -528, -624, -592, |
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200 -944, -912, -1008, -976, -816, -784, -880, -848, |
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201 5504, 5248, 6016, 5760, 4480, 4224, 4992, 4736, |
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202 7552, 7296, 8064, 7808, 6528, 6272, 7040, 6784, |
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203 2752, 2624, 3008, 2880, 2240, 2112, 2496, 2368, |
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204 3776, 3648, 4032, 3904, 3264, 3136, 3520, 3392, |
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205 22016, 20992, 24064, 23040, 17920, 16896, 19968, 18944, |
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206 30208, 29184, 32256, 31232, 26112, 25088, 28160, 27136, |
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207 11008, 10496, 12032, 11520, 8960, 8448, 9984, 9472, |
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208 15104, 14592, 16128, 15616, 13056, 12544, 14080, 13568, |
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209 344, 328, 376, 360, 280, 264, 312, 296, |
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210 472, 456, 504, 488, 408, 392, 440, 424, |
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211 88, 72, 120, 104, 24, 8, 56, 40, |
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212 216, 200, 248, 232, 152, 136, 184, 168, |
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213 1376, 1312, 1504, 1440, 1120, 1056, 1248, 1184, |
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214 1888, 1824, 2016, 1952, 1632, 1568, 1760, 1696, |
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215 688, 656, 752, 720, 560, 528, 624, 592, |
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216 944, 912, 1008, 976, 816, 784, 880, 848 |
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217 }; |
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218 |
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219 static void cs_reset(void *opaque) |
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220 { |
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221 CSState *s = opaque; |
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222 |
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223 s->regs[Index_Address] = 0x40; |
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224 s->regs[Index_Data] = 0x00; |
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225 s->regs[Status] = 0x00; |
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226 s->regs[PIO_Data] = 0x00; |
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227 |
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228 s->dregs[Left_ADC_Input_Control] = 0x00; |
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229 s->dregs[Right_ADC_Input_Control] = 0x00; |
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230 s->dregs[Left_AUX1_Input_Control] = 0x88; |
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231 s->dregs[Right_AUX1_Input_Control] = 0x88; |
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232 s->dregs[Left_AUX2_Input_Control] = 0x88; |
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233 s->dregs[Right_AUX2_Input_Control] = 0x88; |
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234 s->dregs[Left_DAC_Output_Control] = 0x80; |
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235 s->dregs[Right_DAC_Output_Control] = 0x80; |
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236 s->dregs[FS_And_Playback_Data_Format] = 0x00; |
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237 s->dregs[Interface_Configuration] = 0x08; |
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238 s->dregs[Pin_Control] = 0x00; |
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239 s->dregs[Error_Status_And_Initialization] = 0x00; |
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240 s->dregs[MODE_And_ID] = 0x8a; |
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241 s->dregs[Loopback_Control] = 0x00; |
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242 s->dregs[Playback_Upper_Base_Count] = 0x00; |
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243 s->dregs[Playback_Lower_Base_Count] = 0x00; |
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244 s->dregs[Alternate_Feature_Enable_I] = 0x00; |
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245 s->dregs[Alternate_Feature_Enable_II] = 0x00; |
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246 s->dregs[Left_Line_Input_Control] = 0x88; |
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247 s->dregs[Right_Line_Input_Control] = 0x88; |
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248 s->dregs[Timer_Low_Base] = 0x00; |
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249 s->dregs[Timer_High_Base] = 0x00; |
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250 s->dregs[RESERVED] = 0x00; |
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251 s->dregs[Alternate_Feature_Enable_III] = 0x00; |
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252 s->dregs[Alternate_Feature_Status] = 0x00; |
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253 s->dregs[Version_Chip_ID] = 0xa0; |
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254 s->dregs[Mono_Input_And_Output_Control] = 0xa0; |
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255 s->dregs[RESERVED_2] = 0x00; |
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256 s->dregs[Capture_Data_Format] = 0x00; |
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257 s->dregs[RESERVED_3] = 0x00; |
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258 s->dregs[Capture_Upper_Base_Count] = 0x00; |
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259 s->dregs[Capture_Lower_Base_Count] = 0x00; |
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260 } |
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261 |
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262 static void cs_audio_callback (void *opaque, int free) |
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263 { |
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264 CSState *s = opaque; |
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265 s->audio_free = free; |
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266 } |
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267 |
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268 static void cs_reset_voices (CSState *s, uint32_t val) |
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269 { |
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270 int xtal; |
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271 struct audsettings as; |
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272 |
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273 #ifdef DEBUG_XLAW |
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274 if (val == 0 || val == 32) |
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275 val = (1 << 4) | (1 << 5); |
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276 #endif |
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277 |
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278 xtal = val & 1; |
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279 as.freq = freqs[xtal][(val >> 1) & 7]; |
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280 |
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281 if (as.freq == -1) { |
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282 lerr ("unsupported frequency (val=%#x)\n", val); |
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283 goto error; |
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284 } |
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285 |
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286 as.nchannels = (val & (1 << 4)) ? 2 : 1; |
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287 as.endianness = 0; |
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288 s->tab = NULL; |
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289 |
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290 switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) { |
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291 case 0: |
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292 as.fmt = AUD_FMT_U8; |
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293 s->shift = as.nchannels == 2; |
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294 break; |
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295 |
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296 case 1: |
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297 s->tab = MuLawDecompressTable; |
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298 goto x_law; |
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299 case 3: |
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300 s->tab = ALawDecompressTable; |
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301 x_law: |
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302 as.fmt = AUD_FMT_S16; |
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303 as.endianness = AUDIO_HOST_ENDIANNESS; |
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304 s->shift = as.nchannels == 2; |
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305 break; |
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306 |
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307 case 6: |
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308 as.endianness = 1; |
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309 case 2: |
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310 as.fmt = AUD_FMT_S16; |
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311 s->shift = as.nchannels; |
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312 break; |
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313 |
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314 case 7: |
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315 case 4: |
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316 lerr ("attempt to use reserved format value (%#x)\n", val); |
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317 goto error; |
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318 |
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319 case 5: |
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320 lerr ("ADPCM 4 bit IMA compatible format is not supported\n"); |
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321 goto error; |
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322 } |
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323 |
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324 s->voice = AUD_open_out ( |
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325 &s->card, |
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326 s->voice, |
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327 "cs4231a", |
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328 s, |
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329 cs_audio_callback, |
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330 &as |
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331 ); |
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332 |
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333 if (s->dregs[Interface_Configuration] & PEN) { |
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334 if (!s->dma_running) { |
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335 DMA_hold_DREQ (s->dma); |
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336 AUD_set_active_out (s->voice, 1); |
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337 s->transferred = 0; |
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338 } |
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339 s->dma_running = 1; |
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340 } |
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341 else { |
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342 if (s->dma_running) { |
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343 DMA_release_DREQ (s->dma); |
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344 AUD_set_active_out (s->voice, 0); |
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345 } |
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346 s->dma_running = 0; |
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347 } |
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348 return; |
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349 |
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350 error: |
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351 if (s->dma_running) { |
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352 DMA_release_DREQ (s->dma); |
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353 AUD_set_active_out (s->voice, 0); |
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354 } |
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355 } |
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356 |
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357 IO_READ_PROTO (cs_read) |
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358 { |
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359 CSState *s = opaque; |
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360 uint32_t saddr, iaddr, ret; |
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361 |
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362 saddr = GET_SADDR (addr); |
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363 iaddr = ~0U; |
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364 |
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365 switch (saddr) { |
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366 case Index_Address: |
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367 ret = s->regs[saddr] & ~0x80; |
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368 break; |
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369 |
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370 case Index_Data: |
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371 if (!(s->dregs[MODE_And_ID] & MODE2)) |
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372 iaddr = s->regs[Index_Address] & 0x0f; |
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373 else |
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374 iaddr = s->regs[Index_Address] & 0x1f; |
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375 |
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376 ret = s->dregs[iaddr]; |
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377 if (iaddr == Error_Status_And_Initialization) { |
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378 /* keep SEAL happy */ |
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379 if (s->aci_counter) { |
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380 ret |= 1 << 5; |
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381 s->aci_counter -= 1; |
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382 } |
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383 } |
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384 break; |
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385 |
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386 default: |
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387 ret = s->regs[saddr]; |
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388 break; |
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389 } |
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390 dolog ("read %d:%d -> %d\n", saddr, iaddr, ret); |
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391 return ret; |
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392 } |
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393 |
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394 IO_WRITE_PROTO (cs_write) |
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395 { |
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396 CSState *s = opaque; |
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397 uint32_t saddr, iaddr; |
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398 |
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399 saddr = GET_SADDR (addr); |
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400 |
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401 switch (saddr) { |
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402 case Index_Address: |
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403 if (!(s->regs[Index_Address] & MCE) && (val & MCE) |
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404 && (s->dregs[Interface_Configuration] & (3 << 3))) |
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405 s->aci_counter = conf.aci_counter; |
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406 |
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407 s->regs[Index_Address] = val & ~(1 << 7); |
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408 break; |
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409 |
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410 case Index_Data: |
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411 if (!(s->dregs[MODE_And_ID] & MODE2)) |
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412 iaddr = s->regs[Index_Address] & 0x0f; |
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413 else |
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414 iaddr = s->regs[Index_Address] & 0x1f; |
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415 |
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416 switch (iaddr) { |
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417 case RESERVED: |
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418 case RESERVED_2: |
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419 case RESERVED_3: |
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420 lwarn ("attempt to write %#x to reserved indirect register %d\n", |
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421 val, iaddr); |
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422 break; |
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423 |
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424 case FS_And_Playback_Data_Format: |
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425 if (s->regs[Index_Address] & MCE) { |
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426 cs_reset_voices (s, val); |
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427 } |
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428 else { |
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429 if (s->dregs[Alternate_Feature_Status] & PMCE) { |
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430 val = (val & ~0x0f) | (s->dregs[iaddr] & 0x0f); |
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431 cs_reset_voices (s, val); |
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432 } |
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433 else { |
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434 lwarn ("[P]MCE(%#x, %#x) is not set, val=%#x\n", |
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435 s->regs[Index_Address], |
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436 s->dregs[Alternate_Feature_Status], |
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437 val); |
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438 break; |
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439 } |
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440 } |
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441 s->dregs[iaddr] = val; |
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442 break; |
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443 |
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444 case Interface_Configuration: |
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445 val &= ~(1 << 5); /* D5 is reserved */ |
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446 s->dregs[iaddr] = val; |
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447 if (val & PPIO) { |
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448 lwarn ("PIO is not supported (%#x)\n", val); |
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449 break; |
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450 } |
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451 if (val & PEN) { |
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452 if (!s->dma_running) { |
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453 cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]); |
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454 } |
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455 } |
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456 else { |
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457 if (s->dma_running) { |
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458 DMA_release_DREQ (s->dma); |
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459 AUD_set_active_out (s->voice, 0); |
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460 s->dma_running = 0; |
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461 } |
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462 } |
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463 break; |
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464 |
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465 case Error_Status_And_Initialization: |
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466 lwarn ("attempt to write to read only register %d\n", iaddr); |
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467 break; |
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468 |
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469 case MODE_And_ID: |
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470 dolog ("val=%#x\n", val); |
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471 if (val & MODE2) |
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472 s->dregs[iaddr] |= MODE2; |
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473 else |
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474 s->dregs[iaddr] &= ~MODE2; |
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475 break; |
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476 |
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477 case Alternate_Feature_Enable_I: |
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478 if (val & TE) |
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479 lerr ("timer is not yet supported\n"); |
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480 s->dregs[iaddr] = val; |
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481 break; |
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482 |
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483 case Alternate_Feature_Status: |
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484 if ((s->dregs[iaddr] & PI) && !(val & PI)) { |
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485 /* XXX: TI CI */ |
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486 qemu_irq_lower (s->pic[s->irq]); |
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487 s->regs[Status] &= ~INT; |
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488 } |
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489 s->dregs[iaddr] = val; |
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490 break; |
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491 |
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492 case Version_Chip_ID: |
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493 lwarn ("write to Version_Chip_ID register %#x\n", val); |
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494 s->dregs[iaddr] = val; |
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495 break; |
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496 |
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497 default: |
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498 s->dregs[iaddr] = val; |
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499 break; |
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500 } |
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501 dolog ("written value %#x to indirect register %d\n", val, iaddr); |
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502 break; |
|
503 |
|
504 case Status: |
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505 if (s->regs[Status] & INT) { |
|
506 qemu_irq_lower (s->pic[s->irq]); |
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507 } |
|
508 s->regs[Status] &= ~INT; |
|
509 s->dregs[Alternate_Feature_Status] &= ~(PI | CI | TI); |
|
510 break; |
|
511 |
|
512 case PIO_Data: |
|
513 lwarn ("attempt to write value %#x to PIO register\n", val); |
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514 break; |
|
515 } |
|
516 } |
|
517 |
|
518 static int cs_write_audio (CSState *s, int nchan, int dma_pos, |
|
519 int dma_len, int len) |
|
520 { |
|
521 int temp, net; |
|
522 uint8_t tmpbuf[4096]; |
|
523 |
|
524 temp = len; |
|
525 net = 0; |
|
526 |
|
527 while (temp) { |
|
528 int left = dma_len - dma_pos; |
|
529 int copied; |
|
530 size_t to_copy; |
|
531 |
|
532 to_copy = audio_MIN (temp, left); |
|
533 if (to_copy > sizeof (tmpbuf)) { |
|
534 to_copy = sizeof (tmpbuf); |
|
535 } |
|
536 |
|
537 copied = DMA_read_memory (nchan, tmpbuf, dma_pos, to_copy); |
|
538 if (s->tab) { |
|
539 int i; |
|
540 int16_t linbuf[4096]; |
|
541 |
|
542 for (i = 0; i < copied; ++i) |
|
543 linbuf[i] = s->tab[tmpbuf[i]]; |
|
544 copied = AUD_write (s->voice, linbuf, copied << 1); |
|
545 copied >>= 1; |
|
546 } |
|
547 else { |
|
548 copied = AUD_write (s->voice, tmpbuf, copied); |
|
549 } |
|
550 |
|
551 temp -= copied; |
|
552 dma_pos = (dma_pos + copied) % dma_len; |
|
553 net += copied; |
|
554 |
|
555 if (!copied) { |
|
556 break; |
|
557 } |
|
558 } |
|
559 |
|
560 return net; |
|
561 } |
|
562 |
|
563 static int cs_dma_read (void *opaque, int nchan, int dma_pos, int dma_len) |
|
564 { |
|
565 CSState *s = opaque; |
|
566 int copy, written; |
|
567 int till = -1; |
|
568 |
|
569 copy = s->voice ? (s->audio_free >> (s->tab != NULL)) : dma_len; |
|
570 |
|
571 if (s->dregs[Pin_Control] & IEN) { |
|
572 till = (s->dregs[Playback_Lower_Base_Count] |
|
573 | (s->dregs[Playback_Upper_Base_Count] << 8)) << s->shift; |
|
574 till -= s->transferred; |
|
575 copy = audio_MIN (till, copy); |
|
576 } |
|
577 |
|
578 if ((copy <= 0) || (dma_len <= 0)) { |
|
579 return dma_pos; |
|
580 } |
|
581 |
|
582 written = cs_write_audio (s, nchan, dma_pos, dma_len, copy); |
|
583 |
|
584 dma_pos = (dma_pos + written) % dma_len; |
|
585 s->audio_free -= (written << (s->tab != NULL)); |
|
586 |
|
587 if (written == till) { |
|
588 s->regs[Status] |= INT; |
|
589 s->dregs[Alternate_Feature_Status] |= PI; |
|
590 s->transferred = 0; |
|
591 qemu_irq_raise (s->pic[s->irq]); |
|
592 } |
|
593 else { |
|
594 s->transferred += written; |
|
595 } |
|
596 |
|
597 return dma_pos; |
|
598 } |
|
599 |
|
600 static void cs_save(QEMUFile *f, void *opaque) |
|
601 { |
|
602 CSState *s = opaque; |
|
603 unsigned int i; |
|
604 uint32_t val; |
|
605 |
|
606 for (i = 0; i < CS_REGS; i++) |
|
607 qemu_put_be32s(f, &s->regs[i]); |
|
608 |
|
609 qemu_put_buffer(f, s->dregs, CS_DREGS); |
|
610 val = s->dma_running; qemu_put_be32s(f, &val); |
|
611 val = s->audio_free; qemu_put_be32s(f, &val); |
|
612 val = s->transferred; qemu_put_be32s(f, &val); |
|
613 val = s->aci_counter; qemu_put_be32s(f, &val); |
|
614 } |
|
615 |
|
616 static int cs_load(QEMUFile *f, void *opaque, int version_id) |
|
617 { |
|
618 CSState *s = opaque; |
|
619 unsigned int i; |
|
620 uint32_t val, dma_running; |
|
621 |
|
622 if (version_id > 1) |
|
623 return -EINVAL; |
|
624 |
|
625 for (i = 0; i < CS_REGS; i++) |
|
626 qemu_get_be32s(f, &s->regs[i]); |
|
627 |
|
628 qemu_get_buffer(f, s->dregs, CS_DREGS); |
|
629 |
|
630 qemu_get_be32s(f, &dma_running); |
|
631 qemu_get_be32s(f, &val); s->audio_free = val; |
|
632 qemu_get_be32s(f, &val); s->transferred = val; |
|
633 qemu_get_be32s(f, &val); s->aci_counter = val; |
|
634 if (dma_running && (s->dregs[Interface_Configuration] & PEN)) |
|
635 cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]); |
|
636 return 0; |
|
637 } |
|
638 |
|
639 int cs4231a_init (AudioState *audio, qemu_irq *pic) |
|
640 { |
|
641 int i; |
|
642 CSState *s; |
|
643 |
|
644 if (!audio) { |
|
645 lerr ("No audio state\n"); |
|
646 return -1; |
|
647 } |
|
648 |
|
649 s = qemu_mallocz (sizeof (*s)); |
|
650 if (!s) { |
|
651 lerr ("Could not allocate memory for cs4231a (%zu bytes)\n", |
|
652 sizeof (*s)); |
|
653 return -1; |
|
654 } |
|
655 |
|
656 s->pic = pic; |
|
657 s->irq = conf.irq; |
|
658 s->dma = conf.dma; |
|
659 s->port = conf.port; |
|
660 |
|
661 for (i = 0; i < 4; i++) { |
|
662 register_ioport_write (s->port + i, 1, 1, cs_write, s); |
|
663 register_ioport_read (s->port + i, 1, 1, cs_read, s); |
|
664 } |
|
665 |
|
666 DMA_register_channel (s->dma, cs_dma_read, s); |
|
667 |
|
668 register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s); |
|
669 qemu_register_reset (cs_reset, s); |
|
670 cs_reset (s); |
|
671 |
|
672 AUD_register_card (audio,"cs4231a", &s->card); |
|
673 return 0; |
|
674 } |