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1 /* |
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2 * QEMU PowerMac CUDA device support |
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3 * |
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4 * Copyright (c) 2004-2007 Fabrice Bellard |
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5 * Copyright (c) 2007 Jocelyn Mayer |
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6 * |
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7 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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8 * of this software and associated documentation files (the "Software"), to deal |
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9 * in the Software without restriction, including without limitation the rights |
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10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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11 * copies of the Software, and to permit persons to whom the Software is |
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12 * furnished to do so, subject to the following conditions: |
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13 * |
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14 * The above copyright notice and this permission notice shall be included in |
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15 * all copies or substantial portions of the Software. |
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16 * |
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17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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23 * THE SOFTWARE. |
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24 */ |
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25 #include "hw.h" |
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26 #include "ppc_mac.h" |
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27 #include "qemu-timer.h" |
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28 #include "sysemu.h" |
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29 |
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30 /* XXX: implement all timer modes */ |
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31 |
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32 //#define DEBUG_CUDA |
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33 //#define DEBUG_CUDA_PACKET |
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34 |
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35 /* Bits in B data register: all active low */ |
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36 #define TREQ 0x08 /* Transfer request (input) */ |
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37 #define TACK 0x10 /* Transfer acknowledge (output) */ |
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38 #define TIP 0x20 /* Transfer in progress (output) */ |
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39 |
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40 /* Bits in ACR */ |
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41 #define SR_CTRL 0x1c /* Shift register control bits */ |
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42 #define SR_EXT 0x0c /* Shift on external clock */ |
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43 #define SR_OUT 0x10 /* Shift out if 1 */ |
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44 |
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45 /* Bits in IFR and IER */ |
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46 #define IER_SET 0x80 /* set bits in IER */ |
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47 #define IER_CLR 0 /* clear bits in IER */ |
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48 #define SR_INT 0x04 /* Shift register full/empty */ |
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49 #define T1_INT 0x40 /* Timer 1 interrupt */ |
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50 #define T2_INT 0x20 /* Timer 2 interrupt */ |
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51 |
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52 /* Bits in ACR */ |
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53 #define T1MODE 0xc0 /* Timer 1 mode */ |
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54 #define T1MODE_CONT 0x40 /* continuous interrupts */ |
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55 |
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56 /* commands (1st byte) */ |
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57 #define ADB_PACKET 0 |
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58 #define CUDA_PACKET 1 |
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59 #define ERROR_PACKET 2 |
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60 #define TIMER_PACKET 3 |
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61 #define POWER_PACKET 4 |
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62 #define MACIIC_PACKET 5 |
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63 #define PMU_PACKET 6 |
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64 |
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65 |
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66 /* CUDA commands (2nd byte) */ |
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67 #define CUDA_WARM_START 0x0 |
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68 #define CUDA_AUTOPOLL 0x1 |
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69 #define CUDA_GET_6805_ADDR 0x2 |
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70 #define CUDA_GET_TIME 0x3 |
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71 #define CUDA_GET_PRAM 0x7 |
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72 #define CUDA_SET_6805_ADDR 0x8 |
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73 #define CUDA_SET_TIME 0x9 |
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74 #define CUDA_POWERDOWN 0xa |
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75 #define CUDA_POWERUP_TIME 0xb |
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76 #define CUDA_SET_PRAM 0xc |
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77 #define CUDA_MS_RESET 0xd |
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78 #define CUDA_SEND_DFAC 0xe |
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79 #define CUDA_BATTERY_SWAP_SENSE 0x10 |
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80 #define CUDA_RESET_SYSTEM 0x11 |
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81 #define CUDA_SET_IPL 0x12 |
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82 #define CUDA_FILE_SERVER_FLAG 0x13 |
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83 #define CUDA_SET_AUTO_RATE 0x14 |
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84 #define CUDA_GET_AUTO_RATE 0x16 |
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85 #define CUDA_SET_DEVICE_LIST 0x19 |
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86 #define CUDA_GET_DEVICE_LIST 0x1a |
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87 #define CUDA_SET_ONE_SECOND_MODE 0x1b |
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88 #define CUDA_SET_POWER_MESSAGES 0x21 |
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89 #define CUDA_GET_SET_IIC 0x22 |
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90 #define CUDA_WAKEUP 0x23 |
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91 #define CUDA_TIMER_TICKLE 0x24 |
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92 #define CUDA_COMBINED_FORMAT_IIC 0x25 |
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93 |
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94 #define CUDA_TIMER_FREQ (4700000 / 6) |
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95 #define CUDA_ADB_POLL_FREQ 50 |
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96 |
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97 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ |
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98 #define RTC_OFFSET 2082844800 |
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99 |
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100 typedef struct CUDATimer { |
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101 int index; |
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102 uint16_t latch; |
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103 uint16_t counter_value; /* counter value at load time */ |
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104 int64_t load_time; |
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105 int64_t next_irq_time; |
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106 QEMUTimer *timer; |
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107 } CUDATimer; |
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108 |
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109 typedef struct CUDAState { |
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110 /* cuda registers */ |
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111 uint8_t b; /* B-side data */ |
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112 uint8_t a; /* A-side data */ |
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113 uint8_t dirb; /* B-side direction (1=output) */ |
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114 uint8_t dira; /* A-side direction (1=output) */ |
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115 uint8_t sr; /* Shift register */ |
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116 uint8_t acr; /* Auxiliary control register */ |
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117 uint8_t pcr; /* Peripheral control register */ |
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118 uint8_t ifr; /* Interrupt flag register */ |
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119 uint8_t ier; /* Interrupt enable register */ |
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120 uint8_t anh; /* A-side data, no handshake */ |
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121 |
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122 CUDATimer timers[2]; |
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123 |
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124 uint8_t last_b; /* last value of B register */ |
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125 uint8_t last_acr; /* last value of B register */ |
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126 |
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127 int data_in_size; |
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128 int data_in_index; |
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129 int data_out_index; |
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130 |
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131 qemu_irq irq; |
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132 uint8_t autopoll; |
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133 uint8_t data_in[128]; |
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134 uint8_t data_out[16]; |
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135 QEMUTimer *adb_poll_timer; |
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136 } CUDAState; |
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137 |
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138 static CUDAState cuda_state; |
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139 ADBBusState adb_bus; |
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140 |
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141 static void cuda_update(CUDAState *s); |
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142 static void cuda_receive_packet_from_host(CUDAState *s, |
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143 const uint8_t *data, int len); |
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144 static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
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145 int64_t current_time); |
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146 |
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147 static void cuda_update_irq(CUDAState *s) |
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148 { |
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149 if (s->ifr & s->ier & (SR_INT | T1_INT)) { |
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150 qemu_irq_raise(s->irq); |
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151 } else { |
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152 qemu_irq_lower(s->irq); |
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153 } |
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154 } |
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155 |
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156 static unsigned int get_counter(CUDATimer *s) |
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157 { |
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158 int64_t d; |
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159 unsigned int counter; |
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160 |
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161 d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
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162 CUDA_TIMER_FREQ, ticks_per_sec); |
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163 if (s->index == 0) { |
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164 /* the timer goes down from latch to -1 (period of latch + 2) */ |
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165 if (d <= (s->counter_value + 1)) { |
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166 counter = (s->counter_value - d) & 0xffff; |
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167 } else { |
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168 counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
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169 counter = (s->latch - counter) & 0xffff; |
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170 } |
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171 } else { |
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172 counter = (s->counter_value - d) & 0xffff; |
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173 } |
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174 return counter; |
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175 } |
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176 |
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177 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
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178 { |
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179 #ifdef DEBUG_CUDA |
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180 printf("cuda: T%d.counter=%d\n", |
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181 1 + (ti->timer == NULL), val); |
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182 #endif |
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183 ti->load_time = qemu_get_clock(vm_clock); |
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184 ti->counter_value = val; |
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185 cuda_timer_update(s, ti, ti->load_time); |
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186 } |
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187 |
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188 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) |
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189 { |
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190 int64_t d, next_time; |
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191 unsigned int counter; |
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192 |
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193 /* current counter value */ |
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194 d = muldiv64(current_time - s->load_time, |
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195 CUDA_TIMER_FREQ, ticks_per_sec); |
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196 /* the timer goes down from latch to -1 (period of latch + 2) */ |
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197 if (d <= (s->counter_value + 1)) { |
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198 counter = (s->counter_value - d) & 0xffff; |
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199 } else { |
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200 counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
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201 counter = (s->latch - counter) & 0xffff; |
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202 } |
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203 |
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204 /* Note: we consider the irq is raised on 0 */ |
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205 if (counter == 0xffff) { |
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206 next_time = d + s->latch + 1; |
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207 } else if (counter == 0) { |
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208 next_time = d + s->latch + 2; |
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209 } else { |
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210 next_time = d + counter; |
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211 } |
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212 #if 0 |
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213 #ifdef DEBUG_CUDA |
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214 printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", |
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215 s->latch, d, next_time - d); |
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216 #endif |
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217 #endif |
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218 next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
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219 s->load_time; |
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220 if (next_time <= current_time) |
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221 next_time = current_time + 1; |
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222 return next_time; |
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223 } |
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224 |
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225 static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
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226 int64_t current_time) |
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227 { |
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228 if (!ti->timer) |
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229 return; |
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230 if ((s->acr & T1MODE) != T1MODE_CONT) { |
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231 qemu_del_timer(ti->timer); |
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232 } else { |
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233 ti->next_irq_time = get_next_irq_time(ti, current_time); |
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234 qemu_mod_timer(ti->timer, ti->next_irq_time); |
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235 } |
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236 } |
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237 |
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238 static void cuda_timer1(void *opaque) |
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239 { |
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240 CUDAState *s = opaque; |
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241 CUDATimer *ti = &s->timers[0]; |
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242 |
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243 cuda_timer_update(s, ti, ti->next_irq_time); |
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244 s->ifr |= T1_INT; |
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245 cuda_update_irq(s); |
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246 } |
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247 |
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248 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
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249 { |
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250 CUDAState *s = opaque; |
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251 uint32_t val; |
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252 |
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253 addr = (addr >> 9) & 0xf; |
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254 switch(addr) { |
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255 case 0: |
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256 val = s->b; |
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257 break; |
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258 case 1: |
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259 val = s->a; |
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260 break; |
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261 case 2: |
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262 val = s->dirb; |
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263 break; |
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264 case 3: |
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265 val = s->dira; |
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266 break; |
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267 case 4: |
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268 val = get_counter(&s->timers[0]) & 0xff; |
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269 s->ifr &= ~T1_INT; |
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270 cuda_update_irq(s); |
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271 break; |
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272 case 5: |
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273 val = get_counter(&s->timers[0]) >> 8; |
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274 cuda_update_irq(s); |
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275 break; |
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276 case 6: |
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277 val = s->timers[0].latch & 0xff; |
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278 break; |
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279 case 7: |
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280 /* XXX: check this */ |
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281 val = (s->timers[0].latch >> 8) & 0xff; |
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282 break; |
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283 case 8: |
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284 val = get_counter(&s->timers[1]) & 0xff; |
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285 s->ifr &= ~T2_INT; |
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286 break; |
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287 case 9: |
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288 val = get_counter(&s->timers[1]) >> 8; |
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289 break; |
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290 case 10: |
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291 val = s->sr; |
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292 s->ifr &= ~SR_INT; |
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293 cuda_update_irq(s); |
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294 break; |
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295 case 11: |
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296 val = s->acr; |
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297 break; |
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298 case 12: |
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299 val = s->pcr; |
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300 break; |
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301 case 13: |
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302 val = s->ifr; |
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303 if (s->ifr & s->ier) |
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304 val |= 0x80; |
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305 break; |
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306 case 14: |
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307 val = s->ier | 0x80; |
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308 break; |
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309 default: |
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310 case 15: |
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311 val = s->anh; |
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312 break; |
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313 } |
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314 #ifdef DEBUG_CUDA |
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315 if (addr != 13 || val != 0) |
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316 printf("cuda: read: reg=0x%x val=%02x\n", addr, val); |
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317 #endif |
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318 return val; |
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319 } |
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320 |
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321 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
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322 { |
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323 CUDAState *s = opaque; |
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324 |
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325 addr = (addr >> 9) & 0xf; |
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326 #ifdef DEBUG_CUDA |
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327 printf("cuda: write: reg=0x%x val=%02x\n", addr, val); |
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328 #endif |
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329 |
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330 switch(addr) { |
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331 case 0: |
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332 s->b = val; |
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333 cuda_update(s); |
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334 break; |
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335 case 1: |
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336 s->a = val; |
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337 break; |
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338 case 2: |
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339 s->dirb = val; |
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340 break; |
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341 case 3: |
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342 s->dira = val; |
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343 break; |
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344 case 4: |
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345 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
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346 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
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347 break; |
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348 case 5: |
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349 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
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350 s->ifr &= ~T1_INT; |
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351 set_counter(s, &s->timers[0], s->timers[0].latch); |
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352 break; |
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353 case 6: |
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354 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
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355 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
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356 break; |
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357 case 7: |
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358 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
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359 s->ifr &= ~T1_INT; |
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360 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
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361 break; |
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362 case 8: |
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363 s->timers[1].latch = val; |
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364 set_counter(s, &s->timers[1], val); |
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365 break; |
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366 case 9: |
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367 set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
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368 break; |
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369 case 10: |
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370 s->sr = val; |
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371 break; |
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372 case 11: |
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373 s->acr = val; |
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374 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
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375 cuda_update(s); |
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376 break; |
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377 case 12: |
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378 s->pcr = val; |
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379 break; |
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380 case 13: |
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381 /* reset bits */ |
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382 s->ifr &= ~val; |
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383 cuda_update_irq(s); |
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384 break; |
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385 case 14: |
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386 if (val & IER_SET) { |
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387 /* set bits */ |
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388 s->ier |= val & 0x7f; |
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389 } else { |
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390 /* reset bits */ |
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391 s->ier &= ~val; |
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392 } |
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393 cuda_update_irq(s); |
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394 break; |
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395 default: |
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396 case 15: |
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397 s->anh = val; |
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398 break; |
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399 } |
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400 } |
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401 |
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402 /* NOTE: TIP and TREQ are negated */ |
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403 static void cuda_update(CUDAState *s) |
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404 { |
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405 int packet_received, len; |
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406 |
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407 packet_received = 0; |
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408 if (!(s->b & TIP)) { |
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409 /* transfer requested from host */ |
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410 |
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411 if (s->acr & SR_OUT) { |
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412 /* data output */ |
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413 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { |
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414 if (s->data_out_index < sizeof(s->data_out)) { |
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415 #ifdef DEBUG_CUDA |
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416 printf("cuda: send: %02x\n", s->sr); |
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417 #endif |
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418 s->data_out[s->data_out_index++] = s->sr; |
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419 s->ifr |= SR_INT; |
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420 cuda_update_irq(s); |
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421 } |
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422 } |
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423 } else { |
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424 if (s->data_in_index < s->data_in_size) { |
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425 /* data input */ |
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426 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { |
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427 s->sr = s->data_in[s->data_in_index++]; |
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428 #ifdef DEBUG_CUDA |
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429 printf("cuda: recv: %02x\n", s->sr); |
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430 #endif |
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431 /* indicate end of transfer */ |
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432 if (s->data_in_index >= s->data_in_size) { |
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433 s->b = (s->b | TREQ); |
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434 } |
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435 s->ifr |= SR_INT; |
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436 cuda_update_irq(s); |
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437 } |
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438 } |
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439 } |
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440 } else { |
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441 /* no transfer requested: handle sync case */ |
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442 if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) { |
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443 /* update TREQ state each time TACK change state */ |
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444 if (s->b & TACK) |
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445 s->b = (s->b | TREQ); |
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446 else |
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447 s->b = (s->b & ~TREQ); |
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448 s->ifr |= SR_INT; |
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449 cuda_update_irq(s); |
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450 } else { |
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451 if (!(s->last_b & TIP)) { |
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452 /* handle end of host to cuda transfer */ |
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453 packet_received = (s->data_out_index > 0); |
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454 /* always an IRQ at the end of transfer */ |
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455 s->ifr |= SR_INT; |
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456 cuda_update_irq(s); |
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457 } |
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458 /* signal if there is data to read */ |
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459 if (s->data_in_index < s->data_in_size) { |
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460 s->b = (s->b & ~TREQ); |
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461 } |
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462 } |
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463 } |
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464 |
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465 s->last_acr = s->acr; |
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466 s->last_b = s->b; |
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467 |
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468 /* NOTE: cuda_receive_packet_from_host() can call cuda_update() |
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469 recursively */ |
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470 if (packet_received) { |
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471 len = s->data_out_index; |
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472 s->data_out_index = 0; |
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473 cuda_receive_packet_from_host(s, s->data_out, len); |
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474 } |
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475 } |
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476 |
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477 static void cuda_send_packet_to_host(CUDAState *s, |
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478 const uint8_t *data, int len) |
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479 { |
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480 #ifdef DEBUG_CUDA_PACKET |
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481 { |
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482 int i; |
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483 printf("cuda_send_packet_to_host:\n"); |
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484 for(i = 0; i < len; i++) |
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485 printf(" %02x", data[i]); |
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486 printf("\n"); |
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487 } |
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488 #endif |
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489 memcpy(s->data_in, data, len); |
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490 s->data_in_size = len; |
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491 s->data_in_index = 0; |
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492 cuda_update(s); |
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493 s->ifr |= SR_INT; |
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494 cuda_update_irq(s); |
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495 } |
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496 |
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497 static void cuda_adb_poll(void *opaque) |
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498 { |
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499 CUDAState *s = opaque; |
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500 uint8_t obuf[ADB_MAX_OUT_LEN + 2]; |
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501 int olen; |
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502 |
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503 olen = adb_poll(&adb_bus, obuf + 2); |
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504 if (olen > 0) { |
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505 obuf[0] = ADB_PACKET; |
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506 obuf[1] = 0x40; /* polled data */ |
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507 cuda_send_packet_to_host(s, obuf, olen + 2); |
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508 } |
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509 qemu_mod_timer(s->adb_poll_timer, |
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510 qemu_get_clock(vm_clock) + |
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511 (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
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512 } |
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513 |
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514 static void cuda_receive_packet(CUDAState *s, |
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515 const uint8_t *data, int len) |
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516 { |
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517 uint8_t obuf[16]; |
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518 int ti, autopoll; |
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519 |
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520 switch(data[0]) { |
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521 case CUDA_AUTOPOLL: |
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522 autopoll = (data[1] != 0); |
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523 if (autopoll != s->autopoll) { |
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524 s->autopoll = autopoll; |
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525 if (autopoll) { |
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526 qemu_mod_timer(s->adb_poll_timer, |
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527 qemu_get_clock(vm_clock) + |
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528 (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
|
529 } else { |
|
530 qemu_del_timer(s->adb_poll_timer); |
|
531 } |
|
532 } |
|
533 obuf[0] = CUDA_PACKET; |
|
534 obuf[1] = data[1]; |
|
535 cuda_send_packet_to_host(s, obuf, 2); |
|
536 break; |
|
537 case CUDA_GET_TIME: |
|
538 case CUDA_SET_TIME: |
|
539 /* XXX: add time support ? */ |
|
540 ti = time(NULL) + RTC_OFFSET; |
|
541 obuf[0] = CUDA_PACKET; |
|
542 obuf[1] = 0; |
|
543 obuf[2] = 0; |
|
544 obuf[3] = ti >> 24; |
|
545 obuf[4] = ti >> 16; |
|
546 obuf[5] = ti >> 8; |
|
547 obuf[6] = ti; |
|
548 cuda_send_packet_to_host(s, obuf, 7); |
|
549 break; |
|
550 case CUDA_FILE_SERVER_FLAG: |
|
551 case CUDA_SET_DEVICE_LIST: |
|
552 case CUDA_SET_AUTO_RATE: |
|
553 case CUDA_SET_POWER_MESSAGES: |
|
554 obuf[0] = CUDA_PACKET; |
|
555 obuf[1] = 0; |
|
556 cuda_send_packet_to_host(s, obuf, 2); |
|
557 break; |
|
558 case CUDA_POWERDOWN: |
|
559 obuf[0] = CUDA_PACKET; |
|
560 obuf[1] = 0; |
|
561 cuda_send_packet_to_host(s, obuf, 2); |
|
562 qemu_system_shutdown_request(); |
|
563 break; |
|
564 case CUDA_RESET_SYSTEM: |
|
565 obuf[0] = CUDA_PACKET; |
|
566 obuf[1] = 0; |
|
567 cuda_send_packet_to_host(s, obuf, 2); |
|
568 qemu_system_reset_request(); |
|
569 break; |
|
570 default: |
|
571 break; |
|
572 } |
|
573 } |
|
574 |
|
575 static void cuda_receive_packet_from_host(CUDAState *s, |
|
576 const uint8_t *data, int len) |
|
577 { |
|
578 #ifdef DEBUG_CUDA_PACKET |
|
579 { |
|
580 int i; |
|
581 printf("cuda_receive_packet_from_host:\n"); |
|
582 for(i = 0; i < len; i++) |
|
583 printf(" %02x", data[i]); |
|
584 printf("\n"); |
|
585 } |
|
586 #endif |
|
587 switch(data[0]) { |
|
588 case ADB_PACKET: |
|
589 { |
|
590 uint8_t obuf[ADB_MAX_OUT_LEN + 2]; |
|
591 int olen; |
|
592 olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
|
593 if (olen > 0) { |
|
594 obuf[0] = ADB_PACKET; |
|
595 obuf[1] = 0x00; |
|
596 } else { |
|
597 /* error */ |
|
598 obuf[0] = ADB_PACKET; |
|
599 obuf[1] = -olen; |
|
600 olen = 0; |
|
601 } |
|
602 cuda_send_packet_to_host(s, obuf, olen + 2); |
|
603 } |
|
604 break; |
|
605 case CUDA_PACKET: |
|
606 cuda_receive_packet(s, data + 1, len - 1); |
|
607 break; |
|
608 } |
|
609 } |
|
610 |
|
611 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
612 { |
|
613 } |
|
614 |
|
615 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
616 { |
|
617 } |
|
618 |
|
619 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
|
620 { |
|
621 return 0; |
|
622 } |
|
623 |
|
624 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
|
625 { |
|
626 return 0; |
|
627 } |
|
628 |
|
629 static CPUWriteMemoryFunc *cuda_write[] = { |
|
630 &cuda_writeb, |
|
631 &cuda_writew, |
|
632 &cuda_writel, |
|
633 }; |
|
634 |
|
635 static CPUReadMemoryFunc *cuda_read[] = { |
|
636 &cuda_readb, |
|
637 &cuda_readw, |
|
638 &cuda_readl, |
|
639 }; |
|
640 |
|
641 void cuda_init (int *cuda_mem_index, qemu_irq irq) |
|
642 { |
|
643 CUDAState *s = &cuda_state; |
|
644 |
|
645 s->irq = irq; |
|
646 |
|
647 s->timers[0].index = 0; |
|
648 s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s); |
|
649 s->timers[0].latch = 0xffff; |
|
650 set_counter(s, &s->timers[0], 0xffff); |
|
651 |
|
652 s->timers[1].index = 1; |
|
653 s->timers[1].latch = 0; |
|
654 // s->ier = T1_INT | SR_INT; |
|
655 s->ier = 0; |
|
656 set_counter(s, &s->timers[1], 0xffff); |
|
657 |
|
658 s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
|
659 *cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s); |
|
660 } |