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1 /* |
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2 * QEMU Sparc Sun4m ECC memory controller emulation |
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3 * |
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4 * Copyright (c) 2007 Robert Reif |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "sun4m.h" |
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26 #include "sysemu.h" |
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27 |
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28 //#define DEBUG_ECC |
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29 |
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30 #ifdef DEBUG_ECC |
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31 #define DPRINTF(fmt, args...) \ |
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32 do { printf("ECC: " fmt , ##args); } while (0) |
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33 #else |
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34 #define DPRINTF(fmt, args...) |
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35 #endif |
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36 |
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37 /* There are 3 versions of this chip used in SMP sun4m systems: |
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38 * MCC (version 0, implementation 0) SS-600MP |
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39 * EMC (version 0, implementation 1) SS-10 |
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40 * SMC (version 0, implementation 2) SS-10SX and SS-20 |
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41 */ |
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42 |
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43 #define ECC_MCC 0x00000000 |
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44 #define ECC_EMC 0x10000000 |
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45 #define ECC_SMC 0x20000000 |
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46 |
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47 /* Register indexes */ |
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48 #define ECC_MER 0 /* Memory Enable Register */ |
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49 #define ECC_MDR 1 /* Memory Delay Register */ |
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50 #define ECC_MFSR 2 /* Memory Fault Status Register */ |
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51 #define ECC_VCR 3 /* Video Configuration Register */ |
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52 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ |
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53 #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ |
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54 #define ECC_DR 6 /* Diagnostic Register */ |
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55 #define ECC_ECR0 7 /* Event Count Register 0 */ |
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56 #define ECC_ECR1 8 /* Event Count Register 1 */ |
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57 |
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58 /* ECC fault control register */ |
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59 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
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60 #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
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61 correctable errors */ |
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62 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
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63 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ |
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64 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ |
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65 #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ |
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66 #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ |
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67 #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ |
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68 #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ |
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69 #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ |
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70 #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
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71 #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
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72 #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
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73 #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
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74 #define ECC_MER_VER 0x0f000000 /* Version */ |
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75 #define ECC_MER_IMPL 0xf0000000 /* Implementation */ |
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76 #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
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77 #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ |
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78 #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ |
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79 |
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80 /* ECC memory delay register */ |
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81 #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ |
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82 #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ |
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83 #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ |
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84 #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ |
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85 #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ |
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86 #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ |
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87 #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ |
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88 #define ECC_MDR_MASK 0x7fffffff |
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89 |
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90 /* ECC fault status register */ |
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91 #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
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92 #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ |
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93 #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ |
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94 #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ |
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95 #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ |
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96 #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ |
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97 #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ |
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98 #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ |
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99 |
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100 /* ECC fault address register 0 */ |
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101 #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
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102 #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ |
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103 #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ |
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104 #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ |
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105 #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ |
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106 #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ |
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107 #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ |
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108 #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ |
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109 #define ECC_MFARO_MID 0xf0000000 /* Module ID */ |
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110 |
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111 /* ECC diagnostic register */ |
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112 #define ECC_DR_CBX 0x00000001 |
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113 #define ECC_DR_CB0 0x00000002 |
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114 #define ECC_DR_CB1 0x00000004 |
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115 #define ECC_DR_CB2 0x00000008 |
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116 #define ECC_DR_CB4 0x00000010 |
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117 #define ECC_DR_CB8 0x00000020 |
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118 #define ECC_DR_CB16 0x00000040 |
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119 #define ECC_DR_CB32 0x00000080 |
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120 #define ECC_DR_DMODE 0x00000c00 |
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121 |
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122 #define ECC_NREGS 9 |
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123 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
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124 |
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125 #define ECC_DIAG_SIZE 4 |
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126 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
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127 |
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128 typedef struct ECCState { |
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129 qemu_irq irq; |
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130 uint32_t regs[ECC_NREGS]; |
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131 uint8_t diag[ECC_DIAG_SIZE]; |
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132 uint32_t version; |
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133 } ECCState; |
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134 |
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135 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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136 { |
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137 ECCState *s = opaque; |
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138 |
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139 switch (addr >> 2) { |
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140 case ECC_MER: |
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141 if (s->version == ECC_MCC) |
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142 s->regs[ECC_MER] = (val & ECC_MER_MASK_0); |
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143 else if (s->version == ECC_EMC) |
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144 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
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145 else if (s->version == ECC_SMC) |
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146 s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
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147 DPRINTF("Write memory enable %08x\n", val); |
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148 break; |
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149 case ECC_MDR: |
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150 s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
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151 DPRINTF("Write memory delay %08x\n", val); |
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152 break; |
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153 case ECC_MFSR: |
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154 s->regs[ECC_MFSR] = val; |
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155 qemu_irq_lower(s->irq); |
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156 DPRINTF("Write memory fault status %08x\n", val); |
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157 break; |
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158 case ECC_VCR: |
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159 s->regs[ECC_VCR] = val; |
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160 DPRINTF("Write slot configuration %08x\n", val); |
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161 break; |
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162 case ECC_DR: |
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163 s->regs[ECC_DR] = val; |
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164 DPRINTF("Write diagnostic %08x\n", val); |
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165 break; |
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166 case ECC_ECR0: |
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167 s->regs[ECC_ECR0] = val; |
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168 DPRINTF("Write event count 1 %08x\n", val); |
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169 break; |
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170 case ECC_ECR1: |
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171 s->regs[ECC_ECR0] = val; |
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172 DPRINTF("Write event count 2 %08x\n", val); |
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173 break; |
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174 } |
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175 } |
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176 |
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177 static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) |
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178 { |
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179 ECCState *s = opaque; |
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180 uint32_t ret = 0; |
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181 |
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182 switch (addr >> 2) { |
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183 case ECC_MER: |
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184 ret = s->regs[ECC_MER]; |
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185 DPRINTF("Read memory enable %08x\n", ret); |
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186 break; |
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187 case ECC_MDR: |
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188 ret = s->regs[ECC_MDR]; |
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189 DPRINTF("Read memory delay %08x\n", ret); |
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190 break; |
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191 case ECC_MFSR: |
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192 ret = s->regs[ECC_MFSR]; |
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193 DPRINTF("Read memory fault status %08x\n", ret); |
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194 break; |
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195 case ECC_VCR: |
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196 ret = s->regs[ECC_VCR]; |
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197 DPRINTF("Read slot configuration %08x\n", ret); |
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198 break; |
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199 case ECC_MFAR0: |
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200 ret = s->regs[ECC_MFAR0]; |
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201 DPRINTF("Read memory fault address 0 %08x\n", ret); |
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202 break; |
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203 case ECC_MFAR1: |
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204 ret = s->regs[ECC_MFAR1]; |
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205 DPRINTF("Read memory fault address 1 %08x\n", ret); |
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206 break; |
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207 case ECC_DR: |
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208 ret = s->regs[ECC_DR]; |
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209 DPRINTF("Read diagnostic %08x\n", ret); |
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210 break; |
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211 case ECC_ECR0: |
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212 ret = s->regs[ECC_ECR0]; |
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213 DPRINTF("Read event count 1 %08x\n", ret); |
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214 break; |
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215 case ECC_ECR1: |
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216 ret = s->regs[ECC_ECR0]; |
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217 DPRINTF("Read event count 2 %08x\n", ret); |
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218 break; |
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219 } |
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220 return ret; |
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221 } |
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222 |
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223 static CPUReadMemoryFunc *ecc_mem_read[3] = { |
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224 NULL, |
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225 NULL, |
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226 ecc_mem_readl, |
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227 }; |
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228 |
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229 static CPUWriteMemoryFunc *ecc_mem_write[3] = { |
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230 NULL, |
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231 NULL, |
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232 ecc_mem_writel, |
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233 }; |
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234 |
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235 static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
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236 uint32_t val) |
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237 { |
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238 ECCState *s = opaque; |
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239 |
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240 DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val); |
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241 s->diag[addr & ECC_DIAG_MASK] = val; |
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242 } |
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243 |
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244 static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
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245 { |
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246 ECCState *s = opaque; |
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247 uint32_t ret = s->diag[(int)addr]; |
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248 |
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249 DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret); |
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250 return ret; |
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251 } |
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252 |
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253 static CPUReadMemoryFunc *ecc_diag_mem_read[3] = { |
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254 ecc_diag_mem_readb, |
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255 NULL, |
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256 NULL, |
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257 }; |
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258 |
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259 static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = { |
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260 ecc_diag_mem_writeb, |
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261 NULL, |
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262 NULL, |
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263 }; |
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264 |
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265 static int ecc_load(QEMUFile *f, void *opaque, int version_id) |
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266 { |
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267 ECCState *s = opaque; |
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268 int i; |
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269 |
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270 if (version_id != 3) |
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271 return -EINVAL; |
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272 |
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273 for (i = 0; i < ECC_NREGS; i++) |
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274 qemu_get_be32s(f, &s->regs[i]); |
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275 |
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276 for (i = 0; i < ECC_DIAG_SIZE; i++) |
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277 qemu_get_8s(f, &s->diag[i]); |
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278 |
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279 qemu_get_be32s(f, &s->version); |
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280 |
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281 return 0; |
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282 } |
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283 |
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284 static void ecc_save(QEMUFile *f, void *opaque) |
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285 { |
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286 ECCState *s = opaque; |
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287 int i; |
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288 |
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289 for (i = 0; i < ECC_NREGS; i++) |
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290 qemu_put_be32s(f, &s->regs[i]); |
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291 |
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292 for (i = 0; i < ECC_DIAG_SIZE; i++) |
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293 qemu_put_8s(f, &s->diag[i]); |
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294 |
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295 qemu_put_be32s(f, &s->version); |
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296 } |
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297 |
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298 static void ecc_reset(void *opaque) |
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299 { |
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300 ECCState *s = opaque; |
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301 |
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302 if (s->version == ECC_MCC) |
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303 s->regs[ECC_MER] &= ECC_MER_REU; |
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304 else |
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305 s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | |
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306 ECC_MER_DCI); |
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307 s->regs[ECC_MDR] = 0x20; |
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308 s->regs[ECC_MFSR] = 0; |
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309 s->regs[ECC_VCR] = 0; |
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310 s->regs[ECC_MFAR0] = 0x07c00000; |
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311 s->regs[ECC_MFAR1] = 0; |
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312 s->regs[ECC_DR] = 0; |
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313 s->regs[ECC_ECR0] = 0; |
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314 s->regs[ECC_ECR1] = 0; |
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315 } |
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316 |
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317 void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
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318 { |
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319 int ecc_io_memory; |
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320 ECCState *s; |
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321 |
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322 s = qemu_mallocz(sizeof(ECCState)); |
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323 if (!s) |
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324 return NULL; |
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325 |
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326 s->version = version; |
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327 s->regs[0] = version; |
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328 s->irq = irq; |
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329 |
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330 ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s); |
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331 cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory); |
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332 if (version == ECC_MCC) { // SS-600MP only |
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333 ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read, |
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334 ecc_diag_mem_write, s); |
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335 cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE, |
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336 ecc_io_memory); |
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337 } |
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338 register_savevm("ECC", base, 3, ecc_save, ecc_load, s); |
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339 qemu_register_reset(ecc_reset, s); |
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340 ecc_reset(s); |
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341 return s; |
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342 } |