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1 /* |
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2 * QEMU ETRAX Timers |
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3 * |
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4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include <stdio.h> |
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25 #include <sys/time.h> |
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26 #include "hw.h" |
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27 #include "sysemu.h" |
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28 #include "qemu-timer.h" |
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29 |
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30 #define D(x) |
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31 |
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32 #define RW_TMR0_DIV 0x00 |
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33 #define R_TMR0_DATA 0x04 |
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34 #define RW_TMR0_CTRL 0x08 |
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35 #define RW_TMR1_DIV 0x10 |
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36 #define R_TMR1_DATA 0x14 |
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37 #define RW_TMR1_CTRL 0x18 |
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38 #define R_TIME 0x38 |
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39 #define RW_WD_CTRL 0x40 |
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40 #define R_WD_STAT 0x44 |
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41 #define RW_INTR_MASK 0x48 |
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42 #define RW_ACK_INTR 0x4c |
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43 #define R_INTR 0x50 |
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44 #define R_MASKED_INTR 0x54 |
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45 |
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46 struct fs_timer_t { |
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47 CPUState *env; |
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48 qemu_irq *irq; |
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49 qemu_irq *nmi; |
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50 |
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51 QEMUBH *bh_t0; |
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52 QEMUBH *bh_t1; |
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53 QEMUBH *bh_wd; |
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54 ptimer_state *ptimer_t0; |
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55 ptimer_state *ptimer_t1; |
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56 ptimer_state *ptimer_wd; |
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57 struct timeval last; |
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58 |
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59 int wd_hits; |
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60 |
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61 /* Control registers. */ |
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62 uint32_t rw_tmr0_div; |
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63 uint32_t r_tmr0_data; |
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64 uint32_t rw_tmr0_ctrl; |
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65 |
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66 uint32_t rw_tmr1_div; |
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67 uint32_t r_tmr1_data; |
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68 uint32_t rw_tmr1_ctrl; |
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69 |
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70 uint32_t rw_wd_ctrl; |
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71 |
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72 uint32_t rw_intr_mask; |
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73 uint32_t rw_ack_intr; |
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74 uint32_t r_intr; |
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75 uint32_t r_masked_intr; |
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76 }; |
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77 |
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78 static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr) |
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79 { |
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80 struct fs_timer_t *t = opaque; |
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81 CPUState *env = t->env; |
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82 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
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83 addr); |
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84 return 0; |
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85 } |
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86 |
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87 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) |
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88 { |
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89 struct fs_timer_t *t = opaque; |
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90 uint32_t r = 0; |
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91 |
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92 switch (addr) { |
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93 case R_TMR0_DATA: |
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94 break; |
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95 case R_TMR1_DATA: |
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96 D(printf ("R_TMR1_DATA\n")); |
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97 break; |
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98 case R_TIME: |
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99 r = qemu_get_clock(vm_clock) / 10; |
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100 break; |
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101 case RW_INTR_MASK: |
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102 r = t->rw_intr_mask; |
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103 break; |
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104 case R_MASKED_INTR: |
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105 r = t->r_intr & t->rw_intr_mask; |
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106 break; |
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107 default: |
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108 D(printf ("%s %x\n", __func__, addr)); |
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109 break; |
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110 } |
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111 return r; |
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112 } |
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113 |
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114 static void |
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115 timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value) |
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116 { |
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117 struct fs_timer_t *t = opaque; |
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118 CPUState *env = t->env; |
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119 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
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120 addr); |
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121 } |
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122 |
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123 #define TIMER_SLOWDOWN 1 |
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124 static void update_ctrl(struct fs_timer_t *t, int tnum) |
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125 { |
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126 unsigned int op; |
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127 unsigned int freq; |
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128 unsigned int freq_hz; |
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129 unsigned int div; |
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130 uint32_t ctrl; |
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131 |
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132 ptimer_state *timer; |
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133 |
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134 if (tnum == 0) { |
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135 ctrl = t->rw_tmr0_ctrl; |
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136 div = t->rw_tmr0_div; |
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137 timer = t->ptimer_t0; |
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138 } else { |
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139 ctrl = t->rw_tmr1_ctrl; |
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140 div = t->rw_tmr1_div; |
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141 timer = t->ptimer_t1; |
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142 } |
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143 |
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144 |
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145 op = ctrl & 3; |
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146 freq = ctrl >> 2; |
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147 freq_hz = 32000000; |
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148 |
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149 switch (freq) |
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150 { |
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151 case 0: |
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152 case 1: |
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153 D(printf ("extern or disabled timer clock?\n")); |
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154 break; |
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155 case 4: freq_hz = 29493000; break; |
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156 case 5: freq_hz = 32000000; break; |
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157 case 6: freq_hz = 32768000; break; |
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158 case 7: freq_hz = 100001000; break; |
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159 default: |
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160 abort(); |
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161 break; |
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162 } |
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163 |
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164 D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); |
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165 div = div * TIMER_SLOWDOWN; |
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166 div >>= 10; |
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167 freq_hz >>= 10; |
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168 ptimer_set_freq(timer, freq_hz); |
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169 ptimer_set_limit(timer, div, 0); |
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170 |
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171 switch (op) |
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172 { |
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173 case 0: |
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174 /* Load. */ |
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175 ptimer_set_limit(timer, div, 1); |
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176 break; |
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177 case 1: |
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178 /* Hold. */ |
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179 ptimer_stop(timer); |
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180 break; |
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181 case 2: |
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182 /* Run. */ |
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183 ptimer_run(timer, 0); |
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184 break; |
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185 default: |
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186 abort(); |
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187 break; |
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188 } |
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189 } |
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190 |
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191 static void timer_update_irq(struct fs_timer_t *t) |
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192 { |
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193 t->r_intr &= ~(t->rw_ack_intr); |
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194 t->r_masked_intr = t->r_intr & t->rw_intr_mask; |
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195 |
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196 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr)); |
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197 if (t->r_masked_intr) |
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198 qemu_irq_raise(t->irq[0]); |
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199 else |
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200 qemu_irq_lower(t->irq[0]); |
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201 } |
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202 |
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203 static void timer0_hit(void *opaque) |
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204 { |
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205 struct fs_timer_t *t = opaque; |
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206 t->r_intr |= 1; |
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207 timer_update_irq(t); |
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208 } |
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209 |
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210 static void timer1_hit(void *opaque) |
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211 { |
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212 struct fs_timer_t *t = opaque; |
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213 t->r_intr |= 2; |
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214 timer_update_irq(t); |
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215 } |
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216 |
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217 static void watchdog_hit(void *opaque) |
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218 { |
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219 struct fs_timer_t *t = opaque; |
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220 if (t->wd_hits == 0) { |
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221 /* real hw gives a single tick before reseting but we are |
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222 a bit friendlier to compensate for our slower execution. */ |
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223 ptimer_set_count(t->ptimer_wd, 10); |
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224 ptimer_run(t->ptimer_wd, 1); |
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225 qemu_irq_raise(t->nmi[0]); |
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226 } |
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227 else |
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228 qemu_system_reset_request(); |
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229 |
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230 t->wd_hits++; |
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231 } |
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232 |
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233 static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value) |
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234 { |
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235 unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); |
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236 unsigned int wd_key = t->rw_wd_ctrl >> 9; |
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237 unsigned int wd_cnt = t->rw_wd_ctrl & 511; |
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238 unsigned int new_key = value >> 9 & ((1 << 7) - 1); |
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239 unsigned int new_cmd = (value >> 8) & 1; |
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240 |
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241 /* If the watchdog is enabled, they written key must match the |
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242 complement of the previous. */ |
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243 wd_key = ~wd_key & ((1 << 7) - 1); |
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244 |
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245 if (wd_en && wd_key != new_key) |
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246 return; |
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247 |
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248 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", |
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249 wd_en, new_key, wd_key, new_cmd, wd_cnt)); |
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250 |
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251 if (t->wd_hits) |
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252 qemu_irq_lower(t->nmi[0]); |
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253 |
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254 t->wd_hits = 0; |
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255 |
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256 ptimer_set_freq(t->ptimer_wd, 760); |
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257 if (wd_cnt == 0) |
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258 wd_cnt = 256; |
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259 ptimer_set_count(t->ptimer_wd, wd_cnt); |
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260 if (new_cmd) |
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261 ptimer_run(t->ptimer_wd, 1); |
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262 else |
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263 ptimer_stop(t->ptimer_wd); |
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264 |
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265 t->rw_wd_ctrl = value; |
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266 } |
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267 |
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268 static void |
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269 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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270 { |
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271 struct fs_timer_t *t = opaque; |
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272 |
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273 switch (addr) |
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274 { |
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275 case RW_TMR0_DIV: |
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276 t->rw_tmr0_div = value; |
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277 break; |
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278 case RW_TMR0_CTRL: |
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279 D(printf ("RW_TMR0_CTRL=%x\n", value)); |
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280 t->rw_tmr0_ctrl = value; |
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281 update_ctrl(t, 0); |
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282 break; |
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283 case RW_TMR1_DIV: |
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284 t->rw_tmr1_div = value; |
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285 break; |
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286 case RW_TMR1_CTRL: |
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287 D(printf ("RW_TMR1_CTRL=%x\n", value)); |
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288 t->rw_tmr1_ctrl = value; |
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289 update_ctrl(t, 1); |
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290 break; |
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291 case RW_INTR_MASK: |
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292 D(printf ("RW_INTR_MASK=%x\n", value)); |
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293 t->rw_intr_mask = value; |
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294 timer_update_irq(t); |
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295 break; |
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296 case RW_WD_CTRL: |
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297 timer_watchdog_update(t, value); |
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298 break; |
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299 case RW_ACK_INTR: |
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300 t->rw_ack_intr = value; |
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301 timer_update_irq(t); |
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302 t->rw_ack_intr = 0; |
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303 break; |
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304 default: |
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305 printf ("%s " TARGET_FMT_plx " %x\n", |
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306 __func__, addr, value); |
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307 break; |
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308 } |
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309 } |
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310 |
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311 static CPUReadMemoryFunc *timer_read[] = { |
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312 &timer_rinvalid, |
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313 &timer_rinvalid, |
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314 &timer_readl, |
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315 }; |
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316 |
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317 static CPUWriteMemoryFunc *timer_write[] = { |
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318 &timer_winvalid, |
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319 &timer_winvalid, |
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320 &timer_writel, |
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321 }; |
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322 |
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323 static void etraxfs_timer_reset(void *opaque) |
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324 { |
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325 struct fs_timer_t *t = opaque; |
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326 |
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327 ptimer_stop(t->ptimer_t0); |
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328 ptimer_stop(t->ptimer_t1); |
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329 ptimer_stop(t->ptimer_wd); |
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330 t->rw_wd_ctrl = 0; |
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331 t->r_intr = 0; |
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332 t->rw_intr_mask = 0; |
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333 qemu_irq_lower(t->irq[0]); |
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334 } |
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335 |
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336 void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi, |
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337 target_phys_addr_t base) |
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338 { |
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339 static struct fs_timer_t *t; |
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340 int timer_regs; |
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341 |
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342 t = qemu_mallocz(sizeof *t); |
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343 if (!t) |
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344 return; |
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345 |
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346 t->bh_t0 = qemu_bh_new(timer0_hit, t); |
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347 t->bh_t1 = qemu_bh_new(timer1_hit, t); |
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348 t->bh_wd = qemu_bh_new(watchdog_hit, t); |
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349 t->ptimer_t0 = ptimer_init(t->bh_t0); |
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350 t->ptimer_t1 = ptimer_init(t->bh_t1); |
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351 t->ptimer_wd = ptimer_init(t->bh_wd); |
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352 t->irq = irqs; |
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353 t->nmi = nmi; |
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354 t->env = env; |
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355 |
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356 timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t); |
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357 cpu_register_physical_memory (base, 0x5c, timer_regs); |
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358 |
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359 qemu_register_reset(etraxfs_timer_reset, t); |
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360 } |