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1 #ifndef FIRMWARE_ABI_H |
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2 #define FIRMWARE_ABI_H |
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3 |
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4 #ifndef __ASSEMBLY__ |
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5 /* Open Hack'Ware NVRAM configuration structure */ |
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6 |
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7 /* Version 3 */ |
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8 typedef struct ohwcfg_v3_t ohwcfg_v3_t; |
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9 struct ohwcfg_v3_t { |
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10 /* 0x00: structure identifier */ |
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11 uint8_t struct_ident[0x10]; |
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12 /* 0x10: structure version and NVRAM description */ |
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13 uint32_t struct_version; |
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14 uint16_t nvram_size; |
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15 uint16_t pad0; |
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16 uint16_t nvram_arch_ptr; |
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17 uint16_t nvram_arch_size; |
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18 uint16_t nvram_arch_crc; |
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19 uint8_t pad1[0x02]; |
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20 /* 0x20: host architecture */ |
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21 uint8_t arch[0x10]; |
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22 /* 0x30: RAM/ROM description */ |
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23 uint64_t RAM0_base; |
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24 uint64_t RAM0_size; |
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25 uint64_t RAM1_base; |
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26 uint64_t RAM1_size; |
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27 uint64_t RAM2_base; |
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28 uint64_t RAM2_size; |
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29 uint64_t RAM3_base; |
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30 uint64_t RAM3_size; |
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31 uint64_t ROM_base; |
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32 uint64_t ROM_size; |
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33 /* 0x80: Kernel description */ |
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34 uint64_t kernel_image; |
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35 uint64_t kernel_size; |
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36 /* 0x90: Kernel command line */ |
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37 uint64_t cmdline; |
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38 uint64_t cmdline_size; |
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39 /* 0xA0: Kernel boot image */ |
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40 uint64_t initrd_image; |
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41 uint64_t initrd_size; |
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42 /* 0xB0: NVRAM image */ |
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43 uint64_t NVRAM_image; |
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44 uint8_t pad2[8]; |
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45 /* 0xC0: graphic configuration */ |
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46 uint16_t width; |
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47 uint16_t height; |
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48 uint16_t depth; |
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49 uint16_t graphic_flags; |
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50 /* 0xC8: CPUs description */ |
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51 uint8_t nb_cpus; |
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52 uint8_t boot_cpu; |
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53 uint8_t nboot_devices; |
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54 uint8_t pad3[5]; |
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55 /* 0xD0: boot devices */ |
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56 uint8_t boot_devices[0x10]; |
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57 /* 0xE0 */ |
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58 uint8_t pad4[0x1C]; /* 28 */ |
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59 /* 0xFC: checksum */ |
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60 uint16_t crc; |
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61 uint8_t pad5[0x02]; |
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62 } __attribute__ (( packed )); |
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63 |
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64 #define OHW_GF_NOGRAPHICS 0x0001 |
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65 |
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66 static inline uint16_t |
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67 OHW_crc_update (uint16_t prev, uint16_t value) |
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68 { |
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69 uint16_t tmp; |
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70 uint16_t pd, pd1, pd2; |
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71 |
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72 tmp = prev >> 8; |
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73 pd = prev ^ value; |
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74 pd1 = pd & 0x000F; |
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75 pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
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76 tmp ^= (pd1 << 3) | (pd1 << 8); |
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77 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
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78 |
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79 return tmp; |
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80 } |
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81 |
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82 static inline uint16_t |
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83 OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count) |
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84 { |
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85 uint32_t i; |
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86 uint16_t crc = 0xFFFF; |
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87 uint8_t *ptr = (uint8_t *)header; |
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88 int odd; |
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89 |
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90 odd = count & 1; |
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91 count &= ~1; |
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92 for (i = 0; i != count; i++) { |
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93 crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]); |
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94 } |
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95 if (odd) { |
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96 crc = OHW_crc_update(crc, ptr[start + i] << 8); |
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97 } |
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98 |
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99 return crc; |
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100 } |
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101 |
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102 /* Sparc32 runtime NVRAM structure for SMP CPU boot */ |
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103 struct sparc_arch_cfg { |
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104 uint32_t smp_ctx; |
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105 uint32_t smp_ctxtbl; |
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106 uint32_t smp_entry; |
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107 uint8_t valid; |
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108 uint8_t unused[51]; |
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109 }; |
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110 |
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111 /* OpenBIOS NVRAM partition */ |
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112 struct OpenBIOS_nvpart_v1 { |
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113 uint8_t signature; |
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114 uint8_t checksum; |
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115 uint16_t len; // BE, length divided by 16 |
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116 char name[12]; |
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117 }; |
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118 |
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119 #define OPENBIOS_PART_SYSTEM 0x70 |
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120 #define OPENBIOS_PART_FREE 0x7f |
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121 |
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122 static inline void |
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123 OpenBIOS_finish_partition(struct OpenBIOS_nvpart_v1 *header, uint32_t size) |
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124 { |
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125 unsigned int i, sum; |
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126 uint8_t *tmpptr; |
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127 |
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128 // Length divided by 16 |
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129 header->len = cpu_to_be16(size >> 4); |
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130 |
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131 // Checksum |
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132 tmpptr = (uint8_t *)header; |
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133 sum = *tmpptr; |
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134 for (i = 0; i < 14; i++) { |
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135 sum += tmpptr[2 + i]; |
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136 sum = (sum + ((sum & 0xff00) >> 8)) & 0xff; |
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137 } |
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138 header->checksum = sum & 0xff; |
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139 } |
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140 |
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141 static inline uint32_t |
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142 OpenBIOS_set_var(uint8_t *nvram, uint32_t addr, const char *str) |
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143 { |
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144 uint32_t len; |
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145 |
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146 len = strlen(str) + 1; |
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147 memcpy(&nvram[addr], str, len); |
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148 |
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149 return addr + len; |
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150 } |
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151 |
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152 /* Sun IDPROM structure at the end of NVRAM */ |
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153 struct Sun_nvram { |
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154 uint8_t type; |
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155 uint8_t machine_id; |
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156 uint8_t macaddr[6]; |
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157 uint8_t unused[7]; |
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158 uint8_t checksum; |
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159 }; |
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160 |
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161 static inline void |
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162 Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id) |
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163 { |
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164 uint8_t tmp, *tmpptr; |
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165 unsigned int i; |
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166 |
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167 header->type = 1; |
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168 header->machine_id = machine_id & 0xff; |
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169 memcpy(&header->macaddr, macaddr, 6); |
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170 /* Calculate checksum */ |
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171 tmp = 0; |
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172 tmpptr = (uint8_t *)header; |
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173 for (i = 0; i < 15; i++) |
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174 tmp ^= tmpptr[i]; |
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175 |
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176 header->checksum = tmp; |
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177 } |
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178 |
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179 #else /* __ASSEMBLY__ */ |
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180 |
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181 /* Structure offsets for asm use */ |
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182 |
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183 /* Open Hack'Ware NVRAM configuration structure */ |
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184 #define OHW_ARCH_PTR 0x18 |
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185 #define OHW_RAM_SIZE 0x38 |
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186 #define OHW_BOOT_CPU 0xC9 |
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187 |
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188 /* Sparc32 runtime NVRAM structure for SMP CPU boot */ |
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189 #define SPARC_SMP_CTX 0x0 |
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190 #define SPARC_SMP_CTXTBL 0x4 |
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191 #define SPARC_SMP_ENTRY 0x8 |
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192 #define SPARC_SMP_VALID 0xc |
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193 |
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194 /* Sun IDPROM structure at the end of NVRAM */ |
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195 #define SPARC_MACHINE_ID 0x1fd9 |
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196 |
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197 #endif /* __ASSEMBLY__ */ |
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198 #endif /* FIRMWARE_ABI_H */ |