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1 /* NOR flash devices */ |
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2 typedef struct pflash_t pflash_t; |
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3 |
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4 /* pflash_cfi01.c */ |
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5 pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
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6 BlockDriverState *bs, |
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7 uint32_t sector_len, int nb_blocs, int width, |
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8 uint16_t id0, uint16_t id1, |
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9 uint16_t id2, uint16_t id3); |
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10 |
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11 /* pflash_cfi02.c */ |
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12 pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
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13 BlockDriverState *bs, uint32_t sector_len, |
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14 int nb_blocs, int nb_mappings, int width, |
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15 uint16_t id0, uint16_t id1, |
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16 uint16_t id2, uint16_t id3, |
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17 uint16_t unlock_addr0, uint16_t unlock_addr1); |
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18 |
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19 /* nand.c */ |
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20 struct nand_flash_s; |
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21 struct nand_flash_s *nand_init(int manf_id, int chip_id); |
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22 void nand_done(struct nand_flash_s *s); |
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23 void nand_setpins(struct nand_flash_s *s, |
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24 int cle, int ale, int ce, int wp, int gnd); |
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25 void nand_getpins(struct nand_flash_s *s, int *rb); |
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26 void nand_setio(struct nand_flash_s *s, uint8_t value); |
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27 uint8_t nand_getio(struct nand_flash_s *s); |
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28 |
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29 #define NAND_MFR_TOSHIBA 0x98 |
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30 #define NAND_MFR_SAMSUNG 0xec |
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31 #define NAND_MFR_FUJITSU 0x04 |
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32 #define NAND_MFR_NATIONAL 0x8f |
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33 #define NAND_MFR_RENESAS 0x07 |
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34 #define NAND_MFR_STMICRO 0x20 |
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35 #define NAND_MFR_HYNIX 0xad |
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36 #define NAND_MFR_MICRON 0x2c |
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37 |
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38 /* onenand.c */ |
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39 void onenand_base_update(void *opaque, target_phys_addr_t new); |
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40 void onenand_base_unmap(void *opaque); |
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41 void *onenand_init(uint32_t id, int regshift, qemu_irq irq); |
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42 void *onenand_raw_otp(void *opaque); |
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43 |
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44 /* ecc.c */ |
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45 struct ecc_state_s { |
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46 uint8_t cp; /* Column parity */ |
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47 uint16_t lp[2]; /* Line parity */ |
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48 uint16_t count; |
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49 }; |
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50 |
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51 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample); |
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52 void ecc_reset(struct ecc_state_s *s); |
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53 void ecc_put(QEMUFile *f, struct ecc_state_s *s); |
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54 void ecc_get(QEMUFile *f, struct ecc_state_s *s); |