1 /*

     2  * QEMU Grackle PCI host (heathrow OldWorld PowerMac)

     3  *

     4  * Copyright (c) 2006-2007 Fabrice Bellard

     5  * Copyright (c) 2007 Jocelyn Mayer

     6  *

     7  * Permission is hereby granted, free of charge, to any person obtaining a copy

     8  * of this software and associated documentation files (the "Software"), to deal

     9  * in the Software without restriction, including without limitation the rights

    10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    11  * copies of the Software, and to permit persons to whom the Software is

    12  * furnished to do so, subject to the following conditions:

    13  *

    14  * The above copyright notice and this permission notice shall be included in

    15  * all copies or substantial portions of the Software.

    16  *

    17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    23  * THE SOFTWARE.

    24  */

    25 

    26 #include "hw.h"

    27 #include "ppc_mac.h"

    28 #include "pci.h"

    29 

    30 typedef target_phys_addr_t pci_addr_t;

    31 #include "pci_host.h"

    32 

    33 typedef PCIHostState GrackleState;

    34 

    35 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,

    36                                        uint32_t val)

    37 {

    38     GrackleState *s = opaque;

    39 #ifdef TARGET_WORDS_BIGENDIAN

    40     val = bswap32(val);

    41 #endif

    42     s->config_reg = val;

    43 }

    44 

    45 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)

    46 {

    47     GrackleState *s = opaque;

    48     uint32_t val;

    49 

    50     val = s->config_reg;

    51 #ifdef TARGET_WORDS_BIGENDIAN

    52     val = bswap32(val);

    53 #endif

    54     return val;

    55 }

    56 

    57 static CPUWriteMemoryFunc *pci_grackle_config_write[] = {

    58     &pci_grackle_config_writel,

    59     &pci_grackle_config_writel,

    60     &pci_grackle_config_writel,

    61 };

    62 

    63 static CPUReadMemoryFunc *pci_grackle_config_read[] = {

    64     &pci_grackle_config_readl,

    65     &pci_grackle_config_readl,

    66     &pci_grackle_config_readl,

    67 };

    68 

    69 static CPUWriteMemoryFunc *pci_grackle_write[] = {

    70     &pci_host_data_writeb,

    71     &pci_host_data_writew,

    72     &pci_host_data_writel,

    73 };

    74 

    75 static CPUReadMemoryFunc *pci_grackle_read[] = {

    76     &pci_host_data_readb,

    77     &pci_host_data_readw,

    78     &pci_host_data_readl,

    79 };

    80 

    81 /* Don't know if this matches real hardware, but it agrees with OHW.  */

    82 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)

    83 {

    84     return (irq_num + (pci_dev->devfn >> 3)) & 3;

    85 }

    86 

    87 static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)

    88 {

    89     qemu_set_irq(pic[irq_num + 0x15], level);

    90 }

    91 

    92 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)

    93 {

    94     GrackleState *s;

    95     PCIDevice *d;

    96     int pci_mem_config, pci_mem_data;

    97 

    98     s = qemu_mallocz(sizeof(GrackleState));

    99     s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq,

   100                               pic, 0, 4);

   101 

   102     pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,

   103                                             pci_grackle_config_write, s);

   104     pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,

   105                                           pci_grackle_write, s);

   106     cpu_register_physical_memory(base, 0x1000, pci_mem_config);

   107     cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);

   108     d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),

   109                             0, NULL, NULL);

   110     d->config[0x00] = 0x57; // vendor_id

   111     d->config[0x01] = 0x10;

   112     d->config[0x02] = 0x02; // device_id

   113     d->config[0x03] = 0x00;

   114     d->config[0x08] = 0x00; // revision

   115     d->config[0x09] = 0x01;

   116     d->config[0x0a] = 0x00; // class_sub = host

   117     d->config[0x0b] = 0x06; // class_base = PCI_bridge

   118     d->config[0x0e] = 0x00; // header_type

   119 

   120 #if 0

   121     /* PCI2PCI bridge same values as PearPC - check this */

   122     d->config[0x00] = 0x11; // vendor_id

   123     d->config[0x01] = 0x10;

   124     d->config[0x02] = 0x26; // device_id

   125     d->config[0x03] = 0x00;

   126     d->config[0x08] = 0x02; // revision

   127     d->config[0x0a] = 0x04; // class_sub = pci2pci

   128     d->config[0x0b] = 0x06; // class_base = PCI_bridge

   129     d->config[0x0e] = 0x01; // header_type

   130 

   131     d->config[0x18] = 0x0;  // primary_bus

   132     d->config[0x19] = 0x1;  // secondary_bus

   133     d->config[0x1a] = 0x1;  // subordinate_bus

   134     d->config[0x1c] = 0x10; // io_base

   135     d->config[0x1d] = 0x20; // io_limit

   136 

   137     d->config[0x20] = 0x80; // memory_base

   138     d->config[0x21] = 0x80;

   139     d->config[0x22] = 0x90; // memory_limit

   140     d->config[0x23] = 0x80;

   141 

   142     d->config[0x24] = 0x00; // prefetchable_memory_base

   143     d->config[0x25] = 0x84;

   144     d->config[0x26] = 0x00; // prefetchable_memory_limit

   145     d->config[0x27] = 0x85;

   146 #endif

   147     return s->bus;

   148 }