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1 /* |
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2 * QEMU SPARC iommu emulation |
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3 * |
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4 * Copyright (c) 2003-2005 Fabrice Bellard |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "sun4m.h" |
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26 |
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27 /* debug iommu */ |
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28 //#define DEBUG_IOMMU |
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29 |
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30 #ifdef DEBUG_IOMMU |
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31 #define DPRINTF(fmt, args...) \ |
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32 do { printf("IOMMU: " fmt , ##args); } while (0) |
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33 #else |
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34 #define DPRINTF(fmt, args...) |
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35 #endif |
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36 |
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37 #define IOMMU_NREGS (4*4096/4) |
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38 #define IOMMU_CTRL (0x0000 >> 2) |
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39 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
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40 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
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41 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
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42 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
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43 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
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44 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
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45 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
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46 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
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47 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
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48 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
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49 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
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50 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
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51 #define IOMMU_CTRL_MASK 0x0000001d |
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52 |
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53 #define IOMMU_BASE (0x0004 >> 2) |
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54 #define IOMMU_BASE_MASK 0x07fffc00 |
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55 |
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56 #define IOMMU_TLBFLUSH (0x0014 >> 2) |
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57 #define IOMMU_TLBFLUSH_MASK 0xffffffff |
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58 |
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59 #define IOMMU_PGFLUSH (0x0018 >> 2) |
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60 #define IOMMU_PGFLUSH_MASK 0xffffffff |
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61 |
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62 #define IOMMU_AFSR (0x1000 >> 2) |
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63 #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ |
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64 #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after |
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65 transaction */ |
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66 #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than |
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67 12.8 us. */ |
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68 #define IOMMU_AFSR_BE 0x10000000 /* Write access received error |
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69 acknowledge */ |
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70 #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
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71 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
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72 #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by |
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73 hardware */ |
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74 #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
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75 #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ |
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76 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ |
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77 #define IOMMU_AFSR_MASK 0xff0fffff |
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78 |
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79 #define IOMMU_AFAR (0x1004 >> 2) |
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80 |
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81 #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ |
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82 #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ |
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83 #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ |
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84 #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ |
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85 #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ |
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86 #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ |
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87 #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ |
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88 #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ |
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89 #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ |
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90 #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ |
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91 #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ |
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92 #define IOMMU_AER_MASK 0x801f000f |
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93 |
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94 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
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95 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
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96 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
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97 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
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98 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when |
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99 bypass enabled */ |
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100 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
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101 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
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102 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
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103 produced by this device as pure |
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104 physical. */ |
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105 #define IOMMU_SBCFG_MASK 0x00010003 |
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106 |
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107 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
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108 #define IOMMU_ARBEN_MASK 0x001f0000 |
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109 #define IOMMU_MID 0x00000008 |
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110 |
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111 #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ |
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112 #define IOMMU_MASK_ID_MASK 0x00ffffff |
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113 |
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114 #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ |
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115 #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ |
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116 |
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117 /* The format of an iopte in the page tables */ |
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118 #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ |
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119 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or |
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120 Viking/MXCC) */ |
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121 #define IOPTE_WRITE 0x00000004 /* Writeable */ |
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122 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
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123 #define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
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124 |
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125 #define IOMMU_PAGE_SHIFT 12 |
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126 #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) |
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127 #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) |
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128 |
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129 typedef struct IOMMUState { |
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130 uint32_t regs[IOMMU_NREGS]; |
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131 target_phys_addr_t iostart; |
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132 uint32_t version; |
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133 qemu_irq irq; |
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134 } IOMMUState; |
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135 |
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136 static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) |
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137 { |
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138 IOMMUState *s = opaque; |
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139 target_phys_addr_t saddr; |
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140 uint32_t ret; |
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141 |
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142 saddr = addr >> 2; |
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143 switch (saddr) { |
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144 default: |
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145 ret = s->regs[saddr]; |
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146 break; |
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147 case IOMMU_AFAR: |
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148 case IOMMU_AFSR: |
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149 ret = s->regs[saddr]; |
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150 qemu_irq_lower(s->irq); |
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151 break; |
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152 } |
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153 DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); |
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154 return ret; |
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155 } |
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156 |
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157 static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, |
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158 uint32_t val) |
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159 { |
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160 IOMMUState *s = opaque; |
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161 target_phys_addr_t saddr; |
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162 |
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163 saddr = addr >> 2; |
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164 DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
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165 switch (saddr) { |
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166 case IOMMU_CTRL: |
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167 switch (val & IOMMU_CTRL_RNGE) { |
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168 case IOMMU_RNGE_16MB: |
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169 s->iostart = 0xffffffffff000000ULL; |
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170 break; |
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171 case IOMMU_RNGE_32MB: |
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172 s->iostart = 0xfffffffffe000000ULL; |
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173 break; |
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174 case IOMMU_RNGE_64MB: |
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175 s->iostart = 0xfffffffffc000000ULL; |
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176 break; |
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177 case IOMMU_RNGE_128MB: |
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178 s->iostart = 0xfffffffff8000000ULL; |
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179 break; |
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180 case IOMMU_RNGE_256MB: |
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181 s->iostart = 0xfffffffff0000000ULL; |
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182 break; |
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183 case IOMMU_RNGE_512MB: |
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184 s->iostart = 0xffffffffe0000000ULL; |
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185 break; |
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186 case IOMMU_RNGE_1GB: |
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187 s->iostart = 0xffffffffc0000000ULL; |
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188 break; |
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189 default: |
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190 case IOMMU_RNGE_2GB: |
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191 s->iostart = 0xffffffff80000000ULL; |
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192 break; |
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193 } |
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194 DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); |
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195 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); |
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196 break; |
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197 case IOMMU_BASE: |
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198 s->regs[saddr] = val & IOMMU_BASE_MASK; |
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199 break; |
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200 case IOMMU_TLBFLUSH: |
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201 DPRINTF("tlb flush %x\n", val); |
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202 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
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203 break; |
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204 case IOMMU_PGFLUSH: |
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205 DPRINTF("page flush %x\n", val); |
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206 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
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207 break; |
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208 case IOMMU_AFAR: |
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209 s->regs[saddr] = val; |
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210 qemu_irq_lower(s->irq); |
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211 break; |
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212 case IOMMU_AER: |
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213 s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; |
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214 break; |
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215 case IOMMU_AFSR: |
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216 s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; |
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217 qemu_irq_lower(s->irq); |
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218 break; |
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219 case IOMMU_SBCFG0: |
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220 case IOMMU_SBCFG1: |
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221 case IOMMU_SBCFG2: |
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222 case IOMMU_SBCFG3: |
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223 s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
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224 break; |
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225 case IOMMU_ARBEN: |
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226 // XXX implement SBus probing: fault when reading unmapped |
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227 // addresses, fault cause and address stored to MMU/IOMMU |
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228 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
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229 break; |
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230 case IOMMU_MASK_ID: |
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231 s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; |
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232 break; |
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233 default: |
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234 s->regs[saddr] = val; |
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235 break; |
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236 } |
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237 } |
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238 |
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239 static CPUReadMemoryFunc *iommu_mem_read[3] = { |
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240 NULL, |
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241 NULL, |
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242 iommu_mem_readl, |
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243 }; |
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244 |
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245 static CPUWriteMemoryFunc *iommu_mem_write[3] = { |
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246 NULL, |
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247 NULL, |
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248 iommu_mem_writel, |
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249 }; |
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250 |
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251 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) |
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252 { |
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253 uint32_t ret; |
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254 target_phys_addr_t iopte; |
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255 #ifdef DEBUG_IOMMU |
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256 target_phys_addr_t pa = addr; |
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257 #endif |
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258 |
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259 iopte = s->regs[IOMMU_BASE] << 4; |
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260 addr &= ~s->iostart; |
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261 iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; |
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262 cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4); |
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263 tswap32s(&ret); |
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264 DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx |
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265 ", *pte = %x\n", pa, iopte, ret); |
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266 |
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267 return ret; |
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268 } |
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269 |
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270 static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr, |
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271 uint32_t pte) |
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272 { |
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273 uint32_t tmppte; |
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274 target_phys_addr_t pa; |
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275 |
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276 tmppte = pte; |
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277 pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); |
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278 DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx |
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279 " (iopte = %x)\n", addr, pa, tmppte); |
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280 |
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281 return pa; |
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282 } |
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283 |
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284 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, |
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285 int is_write) |
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286 { |
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287 DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); |
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288 s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | |
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289 IOMMU_AFSR_FAV; |
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290 if (!is_write) |
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291 s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; |
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292 s->regs[IOMMU_AFAR] = addr; |
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293 qemu_irq_raise(s->irq); |
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294 } |
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295 |
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296 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
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297 uint8_t *buf, int len, int is_write) |
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298 { |
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299 int l; |
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300 uint32_t flags; |
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301 target_phys_addr_t page, phys_addr; |
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302 |
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303 while (len > 0) { |
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304 page = addr & IOMMU_PAGE_MASK; |
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305 l = (page + IOMMU_PAGE_SIZE) - addr; |
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306 if (l > len) |
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307 l = len; |
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308 flags = iommu_page_get_flags(opaque, page); |
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309 if (!(flags & IOPTE_VALID)) { |
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310 iommu_bad_addr(opaque, page, is_write); |
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311 return; |
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312 } |
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313 phys_addr = iommu_translate_pa(addr, flags); |
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314 if (is_write) { |
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315 if (!(flags & IOPTE_WRITE)) { |
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316 iommu_bad_addr(opaque, page, is_write); |
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317 return; |
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318 } |
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319 cpu_physical_memory_write(phys_addr, buf, l); |
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320 } else { |
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321 cpu_physical_memory_read(phys_addr, buf, l); |
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322 } |
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323 len -= l; |
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324 buf += l; |
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325 addr += l; |
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326 } |
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327 } |
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328 |
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329 static void iommu_save(QEMUFile *f, void *opaque) |
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330 { |
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331 IOMMUState *s = opaque; |
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332 int i; |
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333 |
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334 for (i = 0; i < IOMMU_NREGS; i++) |
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335 qemu_put_be32s(f, &s->regs[i]); |
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336 qemu_put_be64s(f, &s->iostart); |
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337 } |
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338 |
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339 static int iommu_load(QEMUFile *f, void *opaque, int version_id) |
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340 { |
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341 IOMMUState *s = opaque; |
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342 int i; |
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343 |
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344 if (version_id != 2) |
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345 return -EINVAL; |
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346 |
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347 for (i = 0; i < IOMMU_NREGS; i++) |
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348 qemu_get_be32s(f, &s->regs[i]); |
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349 qemu_get_be64s(f, &s->iostart); |
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350 |
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351 return 0; |
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352 } |
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353 |
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354 static void iommu_reset(void *opaque) |
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355 { |
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356 IOMMUState *s = opaque; |
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357 |
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358 memset(s->regs, 0, IOMMU_NREGS * 4); |
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359 s->iostart = 0; |
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360 s->regs[IOMMU_CTRL] = s->version; |
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361 s->regs[IOMMU_ARBEN] = IOMMU_MID; |
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362 s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
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363 s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
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364 s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
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365 qemu_irq_lower(s->irq); |
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366 } |
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367 |
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368 void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
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369 { |
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370 IOMMUState *s; |
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371 int iommu_io_memory; |
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372 |
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373 s = qemu_mallocz(sizeof(IOMMUState)); |
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374 if (!s) |
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375 return NULL; |
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376 |
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377 s->version = version; |
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378 s->irq = irq; |
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379 |
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380 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, |
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381 iommu_mem_write, s); |
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382 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory); |
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383 |
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384 register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); |
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385 qemu_register_reset(iommu_reset, s); |
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386 iommu_reset(s); |
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387 return s; |
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388 } |