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1 /* |
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2 * Motorola ColdFire MCF5208 SoC emulation. |
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3 * |
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4 * Copyright (c) 2007 CodeSourcery. |
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5 * |
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6 * This code is licenced under the GPL |
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7 */ |
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8 #include "hw.h" |
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9 #include "mcf.h" |
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10 #include "qemu-timer.h" |
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11 #include "sysemu.h" |
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12 #include "net.h" |
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13 #include "boards.h" |
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14 |
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15 #define SYS_FREQ 66000000 |
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16 |
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17 #define PCSR_EN 0x0001 |
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18 #define PCSR_RLD 0x0002 |
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19 #define PCSR_PIF 0x0004 |
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20 #define PCSR_PIE 0x0008 |
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21 #define PCSR_OVW 0x0010 |
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22 #define PCSR_DBG 0x0020 |
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23 #define PCSR_DOZE 0x0040 |
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24 #define PCSR_PRE_SHIFT 8 |
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25 #define PCSR_PRE_MASK 0x0f00 |
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26 |
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27 typedef struct { |
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28 qemu_irq irq; |
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29 ptimer_state *timer; |
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30 uint16_t pcsr; |
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31 uint16_t pmr; |
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32 uint16_t pcntr; |
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33 } m5208_timer_state; |
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34 |
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35 static void m5208_timer_update(m5208_timer_state *s) |
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36 { |
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37 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) |
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38 qemu_irq_raise(s->irq); |
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39 else |
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40 qemu_irq_lower(s->irq); |
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41 } |
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42 |
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43 static void m5208_timer_write(void *opaque, target_phys_addr_t offset, |
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44 uint32_t value) |
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45 { |
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46 m5208_timer_state *s = (m5208_timer_state *)opaque; |
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47 int prescale; |
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48 int limit; |
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49 switch (offset) { |
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50 case 0: |
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51 /* The PIF bit is set-to-clear. */ |
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52 if (value & PCSR_PIF) { |
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53 s->pcsr &= ~PCSR_PIF; |
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54 value &= ~PCSR_PIF; |
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55 } |
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56 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ |
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57 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { |
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58 s->pcsr = value; |
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59 m5208_timer_update(s); |
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60 return; |
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61 } |
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62 |
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63 if (s->pcsr & PCSR_EN) |
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64 ptimer_stop(s->timer); |
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65 |
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66 s->pcsr = value; |
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67 |
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68 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); |
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69 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); |
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70 if (s->pcsr & PCSR_RLD) |
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71 limit = s->pmr; |
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72 else |
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73 limit = 0xffff; |
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74 ptimer_set_limit(s->timer, limit, 0); |
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75 |
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76 if (s->pcsr & PCSR_EN) |
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77 ptimer_run(s->timer, 0); |
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78 break; |
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79 case 2: |
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80 s->pmr = value; |
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81 s->pcsr &= ~PCSR_PIF; |
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82 if ((s->pcsr & PCSR_RLD) == 0) { |
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83 if (s->pcsr & PCSR_OVW) |
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84 ptimer_set_count(s->timer, value); |
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85 } else { |
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86 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); |
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87 } |
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88 break; |
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89 case 4: |
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90 break; |
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91 default: |
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92 cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n", |
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93 (int)offset); |
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94 break; |
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95 } |
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96 m5208_timer_update(s); |
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97 } |
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98 |
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99 static void m5208_timer_trigger(void *opaque) |
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100 { |
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101 m5208_timer_state *s = (m5208_timer_state *)opaque; |
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102 s->pcsr |= PCSR_PIF; |
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103 m5208_timer_update(s); |
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104 } |
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105 |
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106 static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr) |
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107 { |
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108 m5208_timer_state *s = (m5208_timer_state *)opaque; |
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109 switch (addr) { |
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110 case 0: |
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111 return s->pcsr; |
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112 case 2: |
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113 return s->pmr; |
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114 case 4: |
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115 return ptimer_get_count(s->timer); |
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116 default: |
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117 cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n", |
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118 (int)addr); |
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119 return 0; |
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120 } |
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121 } |
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122 |
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123 static CPUReadMemoryFunc *m5208_timer_readfn[] = { |
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124 m5208_timer_read, |
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125 m5208_timer_read, |
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126 m5208_timer_read |
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127 }; |
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128 |
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129 static CPUWriteMemoryFunc *m5208_timer_writefn[] = { |
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130 m5208_timer_write, |
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131 m5208_timer_write, |
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132 m5208_timer_write |
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133 }; |
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134 |
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135 static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
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136 { |
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137 switch (addr) { |
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138 case 0x110: /* SDCS0 */ |
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139 { |
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140 int n; |
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141 for (n = 0; n < 32; n++) { |
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142 if (ram_size < (2u << n)) |
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143 break; |
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144 } |
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145 return (n - 1) | 0x40000000; |
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146 } |
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147 case 0x114: /* SDCS1 */ |
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148 return 0; |
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149 |
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150 default: |
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151 cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n", |
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152 (int)addr); |
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153 return 0; |
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154 } |
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155 } |
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156 |
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157 static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
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158 uint32_t value) |
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159 { |
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160 cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n", |
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161 (int)addr); |
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162 } |
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163 |
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164 static CPUReadMemoryFunc *m5208_sys_readfn[] = { |
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165 m5208_sys_read, |
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166 m5208_sys_read, |
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167 m5208_sys_read |
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168 }; |
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169 |
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170 static CPUWriteMemoryFunc *m5208_sys_writefn[] = { |
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171 m5208_sys_write, |
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172 m5208_sys_write, |
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173 m5208_sys_write |
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174 }; |
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175 |
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176 static void mcf5208_sys_init(qemu_irq *pic) |
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177 { |
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178 int iomemtype; |
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179 m5208_timer_state *s; |
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180 QEMUBH *bh; |
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181 int i; |
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182 |
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183 iomemtype = cpu_register_io_memory(0, m5208_sys_readfn, |
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184 m5208_sys_writefn, NULL); |
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185 /* SDRAMC. */ |
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186 cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
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187 /* Timers. */ |
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188 for (i = 0; i < 2; i++) { |
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189 s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state)); |
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190 bh = qemu_bh_new(m5208_timer_trigger, s); |
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191 s->timer = ptimer_init(bh); |
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192 iomemtype = cpu_register_io_memory(0, m5208_timer_readfn, |
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193 m5208_timer_writefn, s); |
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194 cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, |
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195 iomemtype); |
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196 s->irq = pic[4 + i]; |
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197 } |
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198 } |
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199 |
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200 static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size, |
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201 const char *boot_device, DisplayState *ds, |
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202 const char *kernel_filename, const char *kernel_cmdline, |
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203 const char *initrd_filename, const char *cpu_model) |
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204 { |
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205 CPUState *env; |
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206 int kernel_size; |
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207 uint64_t elf_entry; |
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208 target_ulong entry; |
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209 qemu_irq *pic; |
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210 |
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211 if (!cpu_model) |
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212 cpu_model = "m5208"; |
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213 env = cpu_init(cpu_model); |
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214 if (!env) { |
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215 fprintf(stderr, "Unable to find m68k CPU definition\n"); |
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216 exit(1); |
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217 } |
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218 |
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219 /* Initialize CPU registers. */ |
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220 env->vbr = 0; |
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221 /* TODO: Configure BARs. */ |
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222 |
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223 /* DRAM at 0x20000000 */ |
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224 cpu_register_physical_memory(0x40000000, ram_size, |
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225 qemu_ram_alloc(ram_size) | IO_MEM_RAM); |
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226 |
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227 /* Internal SRAM. */ |
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228 cpu_register_physical_memory(0x80000000, 16384, |
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229 qemu_ram_alloc(16384) | IO_MEM_RAM); |
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230 |
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231 /* Internal peripherals. */ |
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232 pic = mcf_intc_init(0xfc048000, env); |
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233 |
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234 mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); |
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235 mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); |
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236 mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); |
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237 |
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238 mcf5208_sys_init(pic); |
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239 |
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240 if (nb_nics > 1) { |
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241 fprintf(stderr, "Too many NICs\n"); |
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242 exit(1); |
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243 } |
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244 if (nd_table[0].vlan) { |
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245 if (nd_table[0].model == NULL |
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246 || strcmp(nd_table[0].model, "mcf_fec") == 0) { |
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247 mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36); |
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248 } else if (strcmp(nd_table[0].model, "?") == 0) { |
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249 fprintf(stderr, "qemu: Supported NICs: mcf_fec\n"); |
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250 exit (1); |
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251 } else { |
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252 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
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253 exit (1); |
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254 } |
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255 } |
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256 |
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257 /* 0xfc000000 SCM. */ |
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258 /* 0xfc004000 XBS. */ |
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259 /* 0xfc008000 FlexBus CS. */ |
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260 /* 0xfc030000 FEC. */ |
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261 /* 0xfc040000 SCM + Power management. */ |
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262 /* 0xfc044000 eDMA. */ |
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263 /* 0xfc048000 INTC. */ |
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264 /* 0xfc058000 I2C. */ |
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265 /* 0xfc05c000 QSPI. */ |
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266 /* 0xfc060000 UART0. */ |
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267 /* 0xfc064000 UART0. */ |
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268 /* 0xfc068000 UART0. */ |
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269 /* 0xfc070000 DMA timers. */ |
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270 /* 0xfc080000 PIT0. */ |
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271 /* 0xfc084000 PIT1. */ |
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272 /* 0xfc088000 EPORT. */ |
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273 /* 0xfc08c000 Watchdog. */ |
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274 /* 0xfc090000 clock module. */ |
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275 /* 0xfc0a0000 CCM + reset. */ |
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276 /* 0xfc0a4000 GPIO. */ |
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277 /* 0xfc0a8000 SDRAM controller. */ |
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278 |
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279 /* Load kernel. */ |
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280 if (!kernel_filename) { |
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281 fprintf(stderr, "Kernel image must be specified\n"); |
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282 exit(1); |
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283 } |
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284 |
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285 kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
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286 entry = elf_entry; |
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287 if (kernel_size < 0) { |
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288 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL); |
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289 } |
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290 if (kernel_size < 0) { |
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291 kernel_size = load_image(kernel_filename, phys_ram_base); |
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292 entry = 0x20000000; |
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293 } |
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294 if (kernel_size < 0) { |
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295 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); |
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296 exit(1); |
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297 } |
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298 |
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299 env->pc = entry; |
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300 } |
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301 |
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302 QEMUMachine mcf5208evb_machine = { |
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303 .name = "mcf5208evb", |
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304 .desc = "MCF5206EVB", |
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305 .init = mcf5208evb_init, |
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306 .ram_require = 16384, |
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307 }; |