1 #include "hw.h"

     2 #include "mips.h"

     3 #include "cpu.h"

     4 

     5 /* Raise IRQ to CPU if necessary. It must be called every time the active

     6    IRQ may change */

     7 void cpu_mips_update_irq(CPUState *env)

     8 {

     9     if ((env->CP0_Status & (1 << CP0St_IE)) &&

    10         !(env->CP0_Status & (1 << CP0St_EXL)) &&

    11         !(env->CP0_Status & (1 << CP0St_ERL)) &&

    12         !(env->hflags & MIPS_HFLAG_DM)) {

    13         if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&

    14             !(env->interrupt_request & CPU_INTERRUPT_HARD)) {

    15             cpu_interrupt(env, CPU_INTERRUPT_HARD);

    16 	}

    17     } else

    18         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);

    19 }

    20 

    21 static void cpu_mips_irq_request(void *opaque, int irq, int level)

    22 {

    23     CPUState *env = (CPUState *)opaque;

    24 

    25     if (irq < 0 || irq > 7)

    26         return;

    27 

    28     if (level) {

    29         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);

    30     } else {

    31         env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));

    32     }

    33     cpu_mips_update_irq(env);

    34 }

    35 

    36 void cpu_mips_irq_init_cpu(CPUState *env)

    37 {

    38     qemu_irq *qi;

    39     int i;

    40 

    41     qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);

    42     for (i = 0; i < 8; i++) {

    43         env->irq[i] = qi[i];

    44     }

    45 }