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1 /* |
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2 * QEMU/MIPS pseudo-board |
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3 * |
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4 * emulates a simple machine with ISA-like bus. |
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5 * ISA IO space mapped to the 0x14000000 (PHYS) and |
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6 * ISA memory at the 0x10000000 (PHYS, 16Mb in size). |
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7 * All peripherial devices are attached to this "bus" with |
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8 * the standard PC ISA addresses. |
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9 */ |
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10 #include "hw.h" |
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11 #include "mips.h" |
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12 #include "pc.h" |
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13 #include "isa.h" |
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14 #include "net.h" |
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15 #include "sysemu.h" |
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16 #include "boards.h" |
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17 #include "flash.h" |
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18 #include "qemu-log.h" |
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19 |
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20 #ifdef TARGET_WORDS_BIGENDIAN |
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21 #define BIOS_FILENAME "mips_bios.bin" |
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22 #else |
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23 #define BIOS_FILENAME "mipsel_bios.bin" |
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24 #endif |
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25 |
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26 #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff) |
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27 |
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28 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
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29 |
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30 #define MAX_IDE_BUS 2 |
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31 |
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32 static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
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33 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
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34 static const int ide_irq[2] = { 14, 15 }; |
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35 |
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36 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
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37 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
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38 |
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39 static PITState *pit; /* PIT i8254 */ |
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40 |
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41 /* i8254 PIT is attached to the IRQ0 at PIC i8259 */ |
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42 |
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43 static struct _loaderparams { |
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44 int ram_size; |
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45 const char *kernel_filename; |
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46 const char *kernel_cmdline; |
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47 const char *initrd_filename; |
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48 } loaderparams; |
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49 |
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50 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
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51 uint32_t val) |
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52 { |
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53 if ((addr & 0xffff) == 0 && val == 42) |
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54 qemu_system_reset_request (); |
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55 else if ((addr & 0xffff) == 4 && val == 42) |
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56 qemu_system_shutdown_request (); |
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57 } |
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58 |
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59 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) |
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60 { |
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61 return 0; |
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62 } |
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63 |
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64 static CPUWriteMemoryFunc *mips_qemu_write[] = { |
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65 &mips_qemu_writel, |
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66 &mips_qemu_writel, |
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67 &mips_qemu_writel, |
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68 }; |
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69 |
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70 static CPUReadMemoryFunc *mips_qemu_read[] = { |
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71 &mips_qemu_readl, |
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72 &mips_qemu_readl, |
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73 &mips_qemu_readl, |
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74 }; |
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75 |
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76 static int mips_qemu_iomemtype = 0; |
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77 |
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78 static void load_kernel (CPUState *env) |
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79 { |
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80 int64_t entry, kernel_low, kernel_high; |
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81 long kernel_size, initrd_size; |
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82 ram_addr_t initrd_offset; |
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83 |
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84 kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
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85 (uint64_t *)&entry, (uint64_t *)&kernel_low, |
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86 (uint64_t *)&kernel_high); |
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87 if (kernel_size >= 0) { |
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88 if ((entry & ~0x7fffffffULL) == 0x80000000) |
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89 entry = (int32_t)entry; |
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90 env->active_tc.PC = entry; |
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91 } else { |
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92 fprintf(stderr, "qemu: could not load kernel '%s'\n", |
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93 loaderparams.kernel_filename); |
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94 exit(1); |
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95 } |
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96 |
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97 /* load initrd */ |
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98 initrd_size = 0; |
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99 initrd_offset = 0; |
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100 if (loaderparams.initrd_filename) { |
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101 initrd_size = get_image_size (loaderparams.initrd_filename); |
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102 if (initrd_size > 0) { |
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103 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
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104 if (initrd_offset + initrd_size > ram_size) { |
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105 fprintf(stderr, |
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106 "qemu: memory too small for initial ram disk '%s'\n", |
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107 loaderparams.initrd_filename); |
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108 exit(1); |
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109 } |
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110 initrd_size = load_image(loaderparams.initrd_filename, |
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111 phys_ram_base + initrd_offset); |
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112 } |
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113 if (initrd_size == (target_ulong) -1) { |
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114 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
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115 loaderparams.initrd_filename); |
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116 exit(1); |
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117 } |
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118 } |
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119 |
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120 /* Store command line. */ |
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121 if (initrd_size > 0) { |
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122 int ret; |
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123 ret = sprintf((char *)(phys_ram_base + (16 << 20) - 256), |
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124 "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
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125 PHYS_TO_VIRT((uint32_t)initrd_offset), |
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126 initrd_size); |
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127 strcpy ((char *)(phys_ram_base + (16 << 20) - 256 + ret), |
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128 loaderparams.kernel_cmdline); |
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129 } |
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130 else { |
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131 strcpy ((char *)(phys_ram_base + (16 << 20) - 256), |
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132 loaderparams.kernel_cmdline); |
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133 } |
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134 |
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135 *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
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136 *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
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137 } |
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138 |
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139 static void main_cpu_reset(void *opaque) |
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140 { |
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141 CPUState *env = opaque; |
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142 cpu_reset(env); |
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143 |
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144 if (loaderparams.kernel_filename) |
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145 load_kernel (env); |
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146 } |
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147 |
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148 static const int sector_len = 32 * 1024; |
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149 static |
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150 void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size, |
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151 const char *boot_device, DisplayState *ds, |
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152 const char *kernel_filename, const char *kernel_cmdline, |
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153 const char *initrd_filename, const char *cpu_model) |
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154 { |
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155 char buf[1024]; |
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156 unsigned long bios_offset; |
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157 int bios_size; |
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158 CPUState *env; |
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159 RTCState *rtc_state; |
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160 int i; |
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161 qemu_irq *i8259; |
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162 int index; |
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163 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
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164 |
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165 /* init CPUs */ |
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166 if (cpu_model == NULL) { |
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167 #ifdef TARGET_MIPS64 |
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168 cpu_model = "R4000"; |
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169 #else |
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170 cpu_model = "24Kf"; |
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171 #endif |
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172 } |
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173 env = cpu_init(cpu_model); |
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174 if (!env) { |
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175 fprintf(stderr, "Unable to find CPU definition\n"); |
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176 exit(1); |
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177 } |
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178 qemu_register_reset(main_cpu_reset, env); |
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179 |
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180 /* allocate RAM */ |
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181 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
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182 |
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183 if (!mips_qemu_iomemtype) { |
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184 mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read, |
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185 mips_qemu_write, NULL); |
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186 } |
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187 cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); |
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188 |
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189 /* Try to load a BIOS image. If this fails, we continue regardless, |
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190 but initialize the hardware ourselves. When a kernel gets |
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191 preloaded we also initialize the hardware, since the BIOS wasn't |
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192 run. */ |
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193 bios_offset = ram_size + vga_ram_size; |
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194 if (bios_name == NULL) |
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195 bios_name = BIOS_FILENAME; |
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196 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
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197 bios_size = load_image(buf, phys_ram_base + bios_offset); |
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198 if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
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199 cpu_register_physical_memory(0x1fc00000, |
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200 BIOS_SIZE, bios_offset | IO_MEM_ROM); |
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201 } else if ((index = drive_get_index(IF_PFLASH, 0, 0)) > -1) { |
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202 uint32_t mips_rom = 0x00400000; |
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203 cpu_register_physical_memory(0x1fc00000, mips_rom, |
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204 qemu_ram_alloc(mips_rom) | IO_MEM_ROM); |
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205 if (!pflash_cfi01_register(0x1fc00000, qemu_ram_alloc(mips_rom), |
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206 drives_table[index].bdrv, sector_len, mips_rom / sector_len, |
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207 4, 0, 0, 0, 0)) { |
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208 fprintf(stderr, "qemu: Error registering flash memory.\n"); |
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209 } |
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210 } |
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211 else { |
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212 /* not fatal */ |
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213 fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", |
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214 buf); |
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215 } |
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216 |
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217 if (kernel_filename) { |
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218 loaderparams.ram_size = ram_size; |
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219 loaderparams.kernel_filename = kernel_filename; |
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220 loaderparams.kernel_cmdline = kernel_cmdline; |
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221 loaderparams.initrd_filename = initrd_filename; |
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222 load_kernel (env); |
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223 } |
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224 |
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225 /* Init CPU internal devices */ |
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226 cpu_mips_irq_init_cpu(env); |
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227 cpu_mips_clock_init(env); |
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228 |
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229 /* The PIC is attached to the MIPS CPU INT0 pin */ |
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230 i8259 = i8259_init(env->irq[2]); |
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231 |
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232 rtc_state = rtc_init(0x70, i8259[8]); |
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233 |
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234 /* Register 64 KB of ISA IO space at 0x14000000 */ |
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235 isa_mmio_init(0x14000000, 0x00010000); |
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236 isa_mem_base = 0x10000000; |
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237 |
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238 pit = pit_init(0x40, i8259[0]); |
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239 |
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240 for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
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241 if (serial_hds[i]) { |
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242 serial_init(serial_io[i], i8259[serial_irq[i]], 115200, |
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243 serial_hds[i]); |
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244 } |
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245 } |
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246 |
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247 isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
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248 vga_ram_size); |
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249 |
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250 if (nd_table[0].vlan) { |
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251 if (nd_table[0].model == NULL |
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252 || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
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253 isa_ne2000_init(0x300, i8259[9], &nd_table[0]); |
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254 } else if (strcmp(nd_table[0].model, "?") == 0) { |
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255 fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n"); |
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256 exit (1); |
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257 } else { |
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258 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
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259 exit (1); |
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260 } |
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261 } |
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262 |
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263 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
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264 fprintf(stderr, "qemu: too many IDE bus\n"); |
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265 exit(1); |
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266 } |
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267 |
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268 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
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269 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
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270 if (index != -1) |
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271 hd[i] = drives_table[index].bdrv; |
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272 else |
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273 hd[i] = NULL; |
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274 } |
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275 |
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276 for(i = 0; i < MAX_IDE_BUS; i++) |
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277 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
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278 hd[MAX_IDE_DEVS * i], |
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279 hd[MAX_IDE_DEVS * i + 1]); |
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280 |
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281 i8042_init(i8259[1], i8259[12], 0x60); |
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282 } |
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283 |
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284 QEMUMachine mips_machine = { |
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285 .name = "mips", |
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286 .desc = "mips r4k platform", |
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287 .init = mips_r4k_init, |
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288 .ram_require = VGA_RAM_SIZE + BIOS_SIZE, |
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289 .nodisk_ok = 1, |
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290 }; |