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1 #include "hw.h" |
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2 #include "mips.h" |
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3 #include "qemu-timer.h" |
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4 |
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5 #define TIMER_FREQ 100 * 1000 * 1000 |
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6 |
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7 /* XXX: do not use a global */ |
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8 uint32_t cpu_mips_get_random (CPUState *env) |
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9 { |
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10 static uint32_t seed = 0; |
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11 uint32_t idx; |
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12 seed = seed * 314159 + 1; |
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13 idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired; |
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14 return idx; |
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15 } |
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16 |
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17 /* MIPS R4K timer */ |
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18 uint32_t cpu_mips_get_count (CPUState *env) |
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19 { |
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20 if (env->CP0_Cause & (1 << CP0Ca_DC)) |
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21 return env->CP0_Count; |
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22 else |
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23 return env->CP0_Count + |
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24 (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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25 TIMER_FREQ, ticks_per_sec); |
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26 } |
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27 |
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28 static void cpu_mips_timer_update(CPUState *env) |
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29 { |
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30 uint64_t now, next; |
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31 uint32_t wait; |
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32 |
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33 now = qemu_get_clock(vm_clock); |
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34 wait = env->CP0_Compare - env->CP0_Count - |
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35 (uint32_t)muldiv64(now, TIMER_FREQ, ticks_per_sec); |
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36 next = now + muldiv64(wait, ticks_per_sec, TIMER_FREQ); |
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37 qemu_mod_timer(env->timer, next); |
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38 } |
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39 |
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40 void cpu_mips_store_count (CPUState *env, uint32_t count) |
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41 { |
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42 if (env->CP0_Cause & (1 << CP0Ca_DC)) |
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43 env->CP0_Count = count; |
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44 else { |
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45 /* Store new count register */ |
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46 env->CP0_Count = |
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47 count - (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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48 TIMER_FREQ, ticks_per_sec); |
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49 /* Update timer timer */ |
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50 cpu_mips_timer_update(env); |
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51 } |
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52 } |
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53 |
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54 void cpu_mips_store_compare (CPUState *env, uint32_t value) |
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55 { |
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56 env->CP0_Compare = value; |
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57 if (!(env->CP0_Cause & (1 << CP0Ca_DC))) |
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58 cpu_mips_timer_update(env); |
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59 if (env->insn_flags & ISA_MIPS32R2) |
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60 env->CP0_Cause &= ~(1 << CP0Ca_TI); |
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61 qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); |
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62 } |
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63 |
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64 void cpu_mips_start_count(CPUState *env) |
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65 { |
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66 cpu_mips_store_count(env, env->CP0_Count); |
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67 } |
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68 |
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69 void cpu_mips_stop_count(CPUState *env) |
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70 { |
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71 /* Store the current value */ |
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72 env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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73 TIMER_FREQ, ticks_per_sec); |
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74 } |
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75 |
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76 static void mips_timer_cb (void *opaque) |
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77 { |
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78 CPUState *env; |
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79 |
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80 env = opaque; |
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81 #if 0 |
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82 if (logfile) { |
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83 fprintf(logfile, "%s\n", __func__); |
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84 } |
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85 #endif |
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86 |
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87 if (env->CP0_Cause & (1 << CP0Ca_DC)) |
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88 return; |
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89 |
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90 /* ??? This callback should occur when the counter is exactly equal to |
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91 the comparator value. Offset the count by one to avoid immediately |
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92 retriggering the callback before any virtual time has passed. */ |
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93 env->CP0_Count++; |
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94 cpu_mips_timer_update(env); |
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95 env->CP0_Count--; |
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96 if (env->insn_flags & ISA_MIPS32R2) |
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97 env->CP0_Cause |= 1 << CP0Ca_TI; |
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98 qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); |
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99 } |
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100 |
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101 void cpu_mips_clock_init (CPUState *env) |
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102 { |
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103 env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
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104 env->CP0_Compare = 0; |
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105 cpu_mips_store_count(env, 1); |
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106 } |