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1 #include "hw.h" |
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2 #include "mips.h" |
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3 #include "net.h" |
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4 #include "isa.h" |
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5 |
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6 //#define DEBUG_MIPSNET_SEND |
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7 //#define DEBUG_MIPSNET_RECEIVE |
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8 //#define DEBUG_MIPSNET_DATA |
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9 //#define DEBUG_MIPSNET_IRQ |
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10 |
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11 /* MIPSnet register offsets */ |
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12 |
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13 #define MIPSNET_DEV_ID 0x00 |
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14 #define MIPSNET_BUSY 0x08 |
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15 #define MIPSNET_RX_DATA_COUNT 0x0c |
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16 #define MIPSNET_TX_DATA_COUNT 0x10 |
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17 #define MIPSNET_INT_CTL 0x14 |
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18 # define MIPSNET_INTCTL_TXDONE 0x00000001 |
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19 # define MIPSNET_INTCTL_RXDONE 0x00000002 |
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20 # define MIPSNET_INTCTL_TESTBIT 0x80000000 |
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21 #define MIPSNET_INTERRUPT_INFO 0x18 |
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22 #define MIPSNET_RX_DATA_BUFFER 0x1c |
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23 #define MIPSNET_TX_DATA_BUFFER 0x20 |
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24 |
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25 #define MAX_ETH_FRAME_SIZE 1514 |
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26 |
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27 typedef struct MIPSnetState { |
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28 uint32_t busy; |
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29 uint32_t rx_count; |
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30 uint32_t rx_read; |
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31 uint32_t tx_count; |
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32 uint32_t tx_written; |
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33 uint32_t intctl; |
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34 uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; |
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35 uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; |
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36 qemu_irq irq; |
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37 VLANClientState *vc; |
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38 NICInfo *nd; |
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39 } MIPSnetState; |
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40 |
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41 static void mipsnet_reset(MIPSnetState *s) |
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42 { |
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43 s->busy = 1; |
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44 s->rx_count = 0; |
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45 s->rx_read = 0; |
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46 s->tx_count = 0; |
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47 s->tx_written = 0; |
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48 s->intctl = 0; |
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49 memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE); |
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50 memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE); |
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51 } |
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52 |
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53 static void mipsnet_update_irq(MIPSnetState *s) |
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54 { |
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55 int isr = !!s->intctl; |
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56 #ifdef DEBUG_MIPSNET_IRQ |
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57 printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl); |
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58 #endif |
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59 qemu_set_irq(s->irq, isr); |
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60 } |
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61 |
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62 static int mipsnet_buffer_full(MIPSnetState *s) |
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63 { |
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64 if (s->rx_count >= MAX_ETH_FRAME_SIZE) |
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65 return 1; |
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66 return 0; |
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67 } |
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68 |
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69 static int mipsnet_can_receive(void *opaque) |
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70 { |
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71 MIPSnetState *s = opaque; |
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72 |
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73 if (s->busy) |
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74 return 0; |
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75 return !mipsnet_buffer_full(s); |
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76 } |
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77 |
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78 static void mipsnet_receive(void *opaque, const uint8_t *buf, int size) |
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79 { |
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80 MIPSnetState *s = opaque; |
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81 |
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82 #ifdef DEBUG_MIPSNET_RECEIVE |
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83 printf("mipsnet: receiving len=%d\n", size); |
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84 #endif |
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85 if (!mipsnet_can_receive(opaque)) |
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86 return; |
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87 |
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88 s->busy = 1; |
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89 |
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90 /* Just accept everything. */ |
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91 |
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92 /* Write packet data. */ |
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93 memcpy(s->rx_buffer, buf, size); |
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94 |
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95 s->rx_count = size; |
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96 s->rx_read = 0; |
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97 |
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98 /* Now we can signal we have received something. */ |
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99 s->intctl |= MIPSNET_INTCTL_RXDONE; |
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100 mipsnet_update_irq(s); |
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101 } |
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102 |
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103 static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr) |
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104 { |
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105 MIPSnetState *s = opaque; |
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106 int ret = 0; |
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107 |
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108 addr &= 0x3f; |
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109 switch (addr) { |
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110 case MIPSNET_DEV_ID: |
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111 ret = be32_to_cpu(0x4d495053); /* MIPS */ |
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112 break; |
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113 case MIPSNET_DEV_ID + 4: |
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114 ret = be32_to_cpu(0x4e455430); /* NET0 */ |
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115 break; |
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116 case MIPSNET_BUSY: |
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117 ret = s->busy; |
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118 break; |
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119 case MIPSNET_RX_DATA_COUNT: |
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120 ret = s->rx_count; |
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121 break; |
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122 case MIPSNET_TX_DATA_COUNT: |
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123 ret = s->tx_count; |
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124 break; |
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125 case MIPSNET_INT_CTL: |
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126 ret = s->intctl; |
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127 s->intctl &= ~MIPSNET_INTCTL_TESTBIT; |
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128 break; |
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129 case MIPSNET_INTERRUPT_INFO: |
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130 /* XXX: This seems to be a per-VPE interrupt number. */ |
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131 ret = 0; |
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132 break; |
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133 case MIPSNET_RX_DATA_BUFFER: |
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134 if (s->rx_count) { |
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135 s->rx_count--; |
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136 ret = s->rx_buffer[s->rx_read++]; |
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137 } |
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138 break; |
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139 /* Reads as zero. */ |
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140 case MIPSNET_TX_DATA_BUFFER: |
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141 default: |
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142 break; |
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143 } |
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144 #ifdef DEBUG_MIPSNET_DATA |
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145 printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret); |
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146 #endif |
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147 return ret; |
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148 } |
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149 |
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150 static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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151 { |
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152 MIPSnetState *s = opaque; |
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153 |
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154 addr &= 0x3f; |
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155 #ifdef DEBUG_MIPSNET_DATA |
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156 printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val); |
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157 #endif |
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158 switch (addr) { |
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159 case MIPSNET_TX_DATA_COUNT: |
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160 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; |
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161 s->tx_written = 0; |
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162 break; |
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163 case MIPSNET_INT_CTL: |
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164 if (val & MIPSNET_INTCTL_TXDONE) { |
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165 s->intctl &= ~MIPSNET_INTCTL_TXDONE; |
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166 } else if (val & MIPSNET_INTCTL_RXDONE) { |
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167 s->intctl &= ~MIPSNET_INTCTL_RXDONE; |
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168 } else if (val & MIPSNET_INTCTL_TESTBIT) { |
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169 mipsnet_reset(s); |
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170 s->intctl |= MIPSNET_INTCTL_TESTBIT; |
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171 } else if (!val) { |
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172 /* ACK testbit interrupt, flag was cleared on read. */ |
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173 } |
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174 s->busy = !!s->intctl; |
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175 mipsnet_update_irq(s); |
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176 break; |
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177 case MIPSNET_TX_DATA_BUFFER: |
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178 s->tx_buffer[s->tx_written++] = val; |
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179 if (s->tx_written == s->tx_count) { |
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180 /* Send buffer. */ |
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181 #ifdef DEBUG_MIPSNET_SEND |
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182 printf("mipsnet: sending len=%d\n", s->tx_count); |
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183 #endif |
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184 qemu_send_packet(s->vc, s->tx_buffer, s->tx_count); |
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185 s->tx_count = s->tx_written = 0; |
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186 s->intctl |= MIPSNET_INTCTL_TXDONE; |
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187 s->busy = 1; |
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188 mipsnet_update_irq(s); |
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189 } |
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190 break; |
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191 /* Read-only registers */ |
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192 case MIPSNET_DEV_ID: |
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193 case MIPSNET_BUSY: |
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194 case MIPSNET_RX_DATA_COUNT: |
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195 case MIPSNET_INTERRUPT_INFO: |
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196 case MIPSNET_RX_DATA_BUFFER: |
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197 default: |
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198 break; |
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199 } |
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200 } |
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201 |
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202 static void mipsnet_save(QEMUFile *f, void *opaque) |
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203 { |
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204 MIPSnetState *s = opaque; |
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205 |
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206 qemu_put_be32s(f, &s->busy); |
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207 qemu_put_be32s(f, &s->rx_count); |
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208 qemu_put_be32s(f, &s->rx_read); |
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209 qemu_put_be32s(f, &s->tx_count); |
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210 qemu_put_be32s(f, &s->tx_written); |
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211 qemu_put_be32s(f, &s->intctl); |
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212 qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE); |
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213 qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE); |
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214 } |
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215 |
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216 static int mipsnet_load(QEMUFile *f, void *opaque, int version_id) |
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217 { |
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218 MIPSnetState *s = opaque; |
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219 |
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220 if (version_id > 0) |
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221 return -EINVAL; |
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222 |
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223 qemu_get_be32s(f, &s->busy); |
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224 qemu_get_be32s(f, &s->rx_count); |
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225 qemu_get_be32s(f, &s->rx_read); |
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226 qemu_get_be32s(f, &s->tx_count); |
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227 qemu_get_be32s(f, &s->tx_written); |
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228 qemu_get_be32s(f, &s->intctl); |
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229 qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE); |
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230 qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE); |
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231 |
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232 return 0; |
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233 } |
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234 |
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235 void mipsnet_init (int base, qemu_irq irq, NICInfo *nd) |
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236 { |
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237 MIPSnetState *s; |
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238 |
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239 s = qemu_mallocz(sizeof(MIPSnetState)); |
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240 if (!s) |
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241 return; |
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242 |
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243 register_ioport_write(base, 36, 1, mipsnet_ioport_write, s); |
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244 register_ioport_read(base, 36, 1, mipsnet_ioport_read, s); |
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245 register_ioport_write(base, 36, 2, mipsnet_ioport_write, s); |
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246 register_ioport_read(base, 36, 2, mipsnet_ioport_read, s); |
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247 register_ioport_write(base, 36, 4, mipsnet_ioport_write, s); |
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248 register_ioport_read(base, 36, 4, mipsnet_ioport_read, s); |
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249 |
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250 s->irq = irq; |
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251 s->nd = nd; |
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252 if (nd && nd->vlan) { |
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253 s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive, |
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254 mipsnet_can_receive, s); |
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255 } else { |
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256 s->vc = NULL; |
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257 } |
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258 |
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259 snprintf(s->vc->info_str, sizeof(s->vc->info_str), |
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260 "mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x", |
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261 s->nd->macaddr[0], |
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262 s->nd->macaddr[1], |
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263 s->nd->macaddr[2], |
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264 s->nd->macaddr[3], |
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265 s->nd->macaddr[4], |
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266 s->nd->macaddr[5]); |
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267 |
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268 mipsnet_reset(s); |
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269 register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s); |
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270 } |