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1 /* |
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2 * QEMU NE2000 emulation |
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3 * |
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4 * Copyright (c) 2003-2004 Fabrice Bellard |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "pci.h" |
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26 #include "pc.h" |
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27 #include "net.h" |
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28 |
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29 /* debug NE2000 card */ |
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30 //#define DEBUG_NE2000 |
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31 |
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32 #define MAX_ETH_FRAME_SIZE 1514 |
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33 |
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34 #define E8390_CMD 0x00 /* The command register (for all pages) */ |
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35 /* Page 0 register offsets. */ |
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36 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
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37 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
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38 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
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39 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
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40 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
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41 #define EN0_TSR 0x04 /* Transmit status reg RD */ |
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42 #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
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43 #define EN0_NCR 0x05 /* Number of collision reg RD */ |
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44 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
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45 #define EN0_FIFO 0x06 /* FIFO RD */ |
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46 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
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47 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
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48 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
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49 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
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50 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
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51 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
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52 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
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53 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
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54 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
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55 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
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56 #define EN0_RSR 0x0c /* rx status reg RD */ |
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57 #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
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58 #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
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59 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
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60 #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
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61 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
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62 #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
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63 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
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64 |
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65 #define EN1_PHYS 0x11 |
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66 #define EN1_CURPAG 0x17 |
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67 #define EN1_MULT 0x18 |
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68 |
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69 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
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70 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
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71 |
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72 #define EN3_CONFIG0 0x33 |
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73 #define EN3_CONFIG1 0x34 |
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74 #define EN3_CONFIG2 0x35 |
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75 #define EN3_CONFIG3 0x36 |
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76 |
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77 /* Register accessed at EN_CMD, the 8390 base addr. */ |
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78 #define E8390_STOP 0x01 /* Stop and reset the chip */ |
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79 #define E8390_START 0x02 /* Start the chip, clear reset */ |
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80 #define E8390_TRANS 0x04 /* Transmit a frame */ |
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81 #define E8390_RREAD 0x08 /* Remote read */ |
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82 #define E8390_RWRITE 0x10 /* Remote write */ |
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83 #define E8390_NODMA 0x20 /* Remote DMA */ |
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84 #define E8390_PAGE0 0x00 /* Select page chip registers */ |
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85 #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
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86 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
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87 |
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88 /* Bits in EN0_ISR - Interrupt status register */ |
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89 #define ENISR_RX 0x01 /* Receiver, no error */ |
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90 #define ENISR_TX 0x02 /* Transmitter, no error */ |
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91 #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
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92 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
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93 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
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94 #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
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95 #define ENISR_RDC 0x40 /* remote dma complete */ |
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96 #define ENISR_RESET 0x80 /* Reset completed */ |
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97 #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
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98 |
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99 /* Bits in received packet status byte and EN0_RSR*/ |
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100 #define ENRSR_RXOK 0x01 /* Received a good packet */ |
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101 #define ENRSR_CRC 0x02 /* CRC error */ |
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102 #define ENRSR_FAE 0x04 /* frame alignment error */ |
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103 #define ENRSR_FO 0x08 /* FIFO overrun */ |
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104 #define ENRSR_MPA 0x10 /* missed pkt */ |
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105 #define ENRSR_PHY 0x20 /* physical/multicast address */ |
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106 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
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107 #define ENRSR_DEF 0x80 /* deferring */ |
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108 |
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109 /* Transmitted packet status, EN0_TSR. */ |
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110 #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
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111 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
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112 #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
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113 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
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114 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
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115 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
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116 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
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117 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
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118 |
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119 #define NE2000_PMEM_SIZE (32*1024) |
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120 #define NE2000_PMEM_START (16*1024) |
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121 #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START) |
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122 #define NE2000_MEM_SIZE NE2000_PMEM_END |
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123 |
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124 typedef struct NE2000State { |
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125 uint8_t cmd; |
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126 uint32_t start; |
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127 uint32_t stop; |
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128 uint8_t boundary; |
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129 uint8_t tsr; |
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130 uint8_t tpsr; |
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131 uint16_t tcnt; |
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132 uint16_t rcnt; |
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133 uint32_t rsar; |
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134 uint8_t rsr; |
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135 uint8_t rxcr; |
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136 uint8_t isr; |
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137 uint8_t dcfg; |
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138 uint8_t imr; |
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139 uint8_t phys[6]; /* mac address */ |
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140 uint8_t curpag; |
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141 uint8_t mult[8]; /* multicast mask array */ |
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142 qemu_irq irq; |
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143 PCIDevice *pci_dev; |
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144 VLANClientState *vc; |
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145 uint8_t macaddr[6]; |
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146 uint8_t mem[NE2000_MEM_SIZE]; |
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147 } NE2000State; |
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148 |
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149 static void ne2000_reset(NE2000State *s) |
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150 { |
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151 int i; |
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152 |
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153 s->isr = ENISR_RESET; |
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154 memcpy(s->mem, s->macaddr, 6); |
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155 s->mem[14] = 0x57; |
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156 s->mem[15] = 0x57; |
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157 |
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158 /* duplicate prom data */ |
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159 for(i = 15;i >= 0; i--) { |
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160 s->mem[2 * i] = s->mem[i]; |
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161 s->mem[2 * i + 1] = s->mem[i]; |
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162 } |
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163 } |
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164 |
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165 static void ne2000_update_irq(NE2000State *s) |
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166 { |
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167 int isr; |
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168 isr = (s->isr & s->imr) & 0x7f; |
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169 #if defined(DEBUG_NE2000) |
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170 printf("NE2000: Set IRQ to %d (%02x %02x)\n", |
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171 isr ? 1 : 0, s->isr, s->imr); |
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172 #endif |
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173 qemu_set_irq(s->irq, (isr != 0)); |
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174 } |
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175 |
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176 #define POLYNOMIAL 0x04c11db6 |
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177 |
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178 /* From FreeBSD */ |
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179 /* XXX: optimize */ |
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180 static int compute_mcast_idx(const uint8_t *ep) |
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181 { |
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182 uint32_t crc; |
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183 int carry, i, j; |
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184 uint8_t b; |
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185 |
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186 crc = 0xffffffff; |
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187 for (i = 0; i < 6; i++) { |
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188 b = *ep++; |
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189 for (j = 0; j < 8; j++) { |
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190 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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191 crc <<= 1; |
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192 b >>= 1; |
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193 if (carry) |
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194 crc = ((crc ^ POLYNOMIAL) | carry); |
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195 } |
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196 } |
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197 return (crc >> 26); |
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198 } |
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199 |
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200 static int ne2000_buffer_full(NE2000State *s) |
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201 { |
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202 int avail, index, boundary; |
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203 |
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204 index = s->curpag << 8; |
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205 boundary = s->boundary << 8; |
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206 if (index < boundary) |
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207 avail = boundary - index; |
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208 else |
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209 avail = (s->stop - s->start) - (index - boundary); |
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210 if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
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211 return 1; |
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212 return 0; |
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213 } |
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214 |
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215 static int ne2000_can_receive(void *opaque) |
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216 { |
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217 NE2000State *s = opaque; |
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218 |
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219 if (s->cmd & E8390_STOP) |
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220 return 1; |
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221 return !ne2000_buffer_full(s); |
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222 } |
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223 |
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224 #define MIN_BUF_SIZE 60 |
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225 |
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226 static void ne2000_receive(void *opaque, const uint8_t *buf, int size) |
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227 { |
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228 NE2000State *s = opaque; |
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229 uint8_t *p; |
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230 unsigned int total_len, next, avail, len, index, mcast_idx; |
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231 uint8_t buf1[60]; |
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232 static const uint8_t broadcast_macaddr[6] = |
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233 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
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234 |
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235 #if defined(DEBUG_NE2000) |
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236 printf("NE2000: received len=%d\n", size); |
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237 #endif |
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238 |
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239 if (s->cmd & E8390_STOP || ne2000_buffer_full(s)) |
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240 return; |
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241 |
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242 /* XXX: check this */ |
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243 if (s->rxcr & 0x10) { |
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244 /* promiscuous: receive all */ |
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245 } else { |
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246 if (!memcmp(buf, broadcast_macaddr, 6)) { |
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247 /* broadcast address */ |
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248 if (!(s->rxcr & 0x04)) |
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249 return; |
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250 } else if (buf[0] & 0x01) { |
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251 /* multicast */ |
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252 if (!(s->rxcr & 0x08)) |
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253 return; |
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254 mcast_idx = compute_mcast_idx(buf); |
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255 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
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256 return; |
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257 } else if (s->mem[0] == buf[0] && |
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258 s->mem[2] == buf[1] && |
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259 s->mem[4] == buf[2] && |
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260 s->mem[6] == buf[3] && |
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261 s->mem[8] == buf[4] && |
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262 s->mem[10] == buf[5]) { |
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263 /* match */ |
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264 } else { |
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265 return; |
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266 } |
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267 } |
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268 |
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269 |
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270 /* if too small buffer, then expand it */ |
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271 if (size < MIN_BUF_SIZE) { |
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272 memcpy(buf1, buf, size); |
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273 memset(buf1 + size, 0, MIN_BUF_SIZE - size); |
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274 buf = buf1; |
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275 size = MIN_BUF_SIZE; |
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276 } |
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277 |
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278 index = s->curpag << 8; |
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279 /* 4 bytes for header */ |
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280 total_len = size + 4; |
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281 /* address for next packet (4 bytes for CRC) */ |
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282 next = index + ((total_len + 4 + 255) & ~0xff); |
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283 if (next >= s->stop) |
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284 next -= (s->stop - s->start); |
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285 /* prepare packet header */ |
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286 p = s->mem + index; |
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287 s->rsr = ENRSR_RXOK; /* receive status */ |
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288 /* XXX: check this */ |
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289 if (buf[0] & 0x01) |
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290 s->rsr |= ENRSR_PHY; |
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291 p[0] = s->rsr; |
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292 p[1] = next >> 8; |
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293 p[2] = total_len; |
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294 p[3] = total_len >> 8; |
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295 index += 4; |
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296 |
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297 /* write packet data */ |
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298 while (size > 0) { |
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299 if (index <= s->stop) |
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300 avail = s->stop - index; |
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301 else |
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302 avail = 0; |
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303 len = size; |
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304 if (len > avail) |
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305 len = avail; |
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306 memcpy(s->mem + index, buf, len); |
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307 buf += len; |
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308 index += len; |
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309 if (index == s->stop) |
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310 index = s->start; |
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311 size -= len; |
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312 } |
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313 s->curpag = next >> 8; |
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314 |
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315 /* now we can signal we have received something */ |
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316 s->isr |= ENISR_RX; |
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317 ne2000_update_irq(s); |
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318 } |
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319 |
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320 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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321 { |
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322 NE2000State *s = opaque; |
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323 int offset, page, index; |
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324 |
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325 addr &= 0xf; |
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326 #ifdef DEBUG_NE2000 |
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327 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val); |
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328 #endif |
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329 if (addr == E8390_CMD) { |
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330 /* control register */ |
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331 s->cmd = val; |
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332 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
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333 s->isr &= ~ENISR_RESET; |
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334 /* test specific case: zero length transfer */ |
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335 if ((val & (E8390_RREAD | E8390_RWRITE)) && |
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336 s->rcnt == 0) { |
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337 s->isr |= ENISR_RDC; |
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338 ne2000_update_irq(s); |
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339 } |
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340 if (val & E8390_TRANS) { |
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341 index = (s->tpsr << 8); |
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342 /* XXX: next 2 lines are a hack to make netware 3.11 work */ |
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343 if (index >= NE2000_PMEM_END) |
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344 index -= NE2000_PMEM_SIZE; |
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345 /* fail safe: check range on the transmitted length */ |
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346 if (index + s->tcnt <= NE2000_PMEM_END) { |
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347 qemu_send_packet(s->vc, s->mem + index, s->tcnt); |
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348 } |
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349 /* signal end of transfer */ |
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350 s->tsr = ENTSR_PTX; |
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351 s->isr |= ENISR_TX; |
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352 s->cmd &= ~E8390_TRANS; |
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353 ne2000_update_irq(s); |
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354 } |
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355 } |
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356 } else { |
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357 page = s->cmd >> 6; |
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358 offset = addr | (page << 4); |
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359 switch(offset) { |
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360 case EN0_STARTPG: |
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361 s->start = val << 8; |
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362 break; |
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363 case EN0_STOPPG: |
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364 s->stop = val << 8; |
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365 break; |
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366 case EN0_BOUNDARY: |
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367 s->boundary = val; |
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368 break; |
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369 case EN0_IMR: |
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370 s->imr = val; |
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371 ne2000_update_irq(s); |
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372 break; |
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373 case EN0_TPSR: |
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374 s->tpsr = val; |
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375 break; |
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376 case EN0_TCNTLO: |
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377 s->tcnt = (s->tcnt & 0xff00) | val; |
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378 break; |
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379 case EN0_TCNTHI: |
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380 s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
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381 break; |
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382 case EN0_RSARLO: |
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383 s->rsar = (s->rsar & 0xff00) | val; |
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384 break; |
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385 case EN0_RSARHI: |
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386 s->rsar = (s->rsar & 0x00ff) | (val << 8); |
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387 break; |
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388 case EN0_RCNTLO: |
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389 s->rcnt = (s->rcnt & 0xff00) | val; |
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390 break; |
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391 case EN0_RCNTHI: |
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392 s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
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393 break; |
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394 case EN0_RXCR: |
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395 s->rxcr = val; |
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396 break; |
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397 case EN0_DCFG: |
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398 s->dcfg = val; |
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399 break; |
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400 case EN0_ISR: |
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401 s->isr &= ~(val & 0x7f); |
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402 ne2000_update_irq(s); |
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403 break; |
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404 case EN1_PHYS ... EN1_PHYS + 5: |
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405 s->phys[offset - EN1_PHYS] = val; |
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406 break; |
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407 case EN1_CURPAG: |
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408 s->curpag = val; |
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409 break; |
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410 case EN1_MULT ... EN1_MULT + 7: |
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411 s->mult[offset - EN1_MULT] = val; |
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412 break; |
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413 } |
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414 } |
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415 } |
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416 |
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417 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
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418 { |
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419 NE2000State *s = opaque; |
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420 int offset, page, ret; |
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421 |
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422 addr &= 0xf; |
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423 if (addr == E8390_CMD) { |
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424 ret = s->cmd; |
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425 } else { |
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426 page = s->cmd >> 6; |
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427 offset = addr | (page << 4); |
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428 switch(offset) { |
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429 case EN0_TSR: |
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430 ret = s->tsr; |
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431 break; |
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432 case EN0_BOUNDARY: |
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433 ret = s->boundary; |
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434 break; |
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435 case EN0_ISR: |
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436 ret = s->isr; |
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437 break; |
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438 case EN0_RSARLO: |
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439 ret = s->rsar & 0x00ff; |
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440 break; |
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441 case EN0_RSARHI: |
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442 ret = s->rsar >> 8; |
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443 break; |
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444 case EN1_PHYS ... EN1_PHYS + 5: |
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445 ret = s->phys[offset - EN1_PHYS]; |
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446 break; |
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447 case EN1_CURPAG: |
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448 ret = s->curpag; |
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449 break; |
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450 case EN1_MULT ... EN1_MULT + 7: |
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451 ret = s->mult[offset - EN1_MULT]; |
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452 break; |
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453 case EN0_RSR: |
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454 ret = s->rsr; |
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455 break; |
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456 case EN2_STARTPG: |
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457 ret = s->start >> 8; |
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458 break; |
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459 case EN2_STOPPG: |
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460 ret = s->stop >> 8; |
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461 break; |
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462 case EN0_RTL8029ID0: |
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463 ret = 0x50; |
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464 break; |
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465 case EN0_RTL8029ID1: |
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466 ret = 0x43; |
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467 break; |
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468 case EN3_CONFIG0: |
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469 ret = 0; /* 10baseT media */ |
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470 break; |
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471 case EN3_CONFIG2: |
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472 ret = 0x40; /* 10baseT active */ |
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473 break; |
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474 case EN3_CONFIG3: |
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475 ret = 0x40; /* Full duplex */ |
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476 break; |
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477 default: |
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478 ret = 0x00; |
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479 break; |
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480 } |
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481 } |
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482 #ifdef DEBUG_NE2000 |
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483 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret); |
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484 #endif |
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485 return ret; |
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486 } |
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487 |
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488 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
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489 uint32_t val) |
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490 { |
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491 if (addr < 32 || |
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492 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
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493 s->mem[addr] = val; |
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494 } |
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495 } |
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496 |
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497 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
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498 uint32_t val) |
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499 { |
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500 addr &= ~1; /* XXX: check exact behaviour if not even */ |
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501 if (addr < 32 || |
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502 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
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503 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
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504 } |
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505 } |
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506 |
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507 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
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508 uint32_t val) |
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509 { |
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510 addr &= ~1; /* XXX: check exact behaviour if not even */ |
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511 if (addr < 32 || |
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512 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
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513 cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
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514 } |
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515 } |
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516 |
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517 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
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518 { |
|
519 if (addr < 32 || |
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520 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
|
521 return s->mem[addr]; |
|
522 } else { |
|
523 return 0xff; |
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524 } |
|
525 } |
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526 |
|
527 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
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528 { |
|
529 addr &= ~1; /* XXX: check exact behaviour if not even */ |
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530 if (addr < 32 || |
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531 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
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532 return le16_to_cpu(*(uint16_t *)(s->mem + addr)); |
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533 } else { |
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534 return 0xffff; |
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535 } |
|
536 } |
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537 |
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538 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
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539 { |
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540 addr &= ~1; /* XXX: check exact behaviour if not even */ |
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541 if (addr < 32 || |
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542 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
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543 return le32_to_cpupu((uint32_t *)(s->mem + addr)); |
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544 } else { |
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545 return 0xffffffff; |
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546 } |
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547 } |
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548 |
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549 static inline void ne2000_dma_update(NE2000State *s, int len) |
|
550 { |
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551 s->rsar += len; |
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552 /* wrap */ |
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553 /* XXX: check what to do if rsar > stop */ |
|
554 if (s->rsar == s->stop) |
|
555 s->rsar = s->start; |
|
556 |
|
557 if (s->rcnt <= len) { |
|
558 s->rcnt = 0; |
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559 /* signal end of transfer */ |
|
560 s->isr |= ENISR_RDC; |
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561 ne2000_update_irq(s); |
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562 } else { |
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563 s->rcnt -= len; |
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564 } |
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565 } |
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566 |
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567 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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568 { |
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569 NE2000State *s = opaque; |
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570 |
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571 #ifdef DEBUG_NE2000 |
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572 printf("NE2000: asic write val=0x%04x\n", val); |
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573 #endif |
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574 if (s->rcnt == 0) |
|
575 return; |
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576 if (s->dcfg & 0x01) { |
|
577 /* 16 bit access */ |
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578 ne2000_mem_writew(s, s->rsar, val); |
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579 ne2000_dma_update(s, 2); |
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580 } else { |
|
581 /* 8 bit access */ |
|
582 ne2000_mem_writeb(s, s->rsar, val); |
|
583 ne2000_dma_update(s, 1); |
|
584 } |
|
585 } |
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586 |
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587 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
|
588 { |
|
589 NE2000State *s = opaque; |
|
590 int ret; |
|
591 |
|
592 if (s->dcfg & 0x01) { |
|
593 /* 16 bit access */ |
|
594 ret = ne2000_mem_readw(s, s->rsar); |
|
595 ne2000_dma_update(s, 2); |
|
596 } else { |
|
597 /* 8 bit access */ |
|
598 ret = ne2000_mem_readb(s, s->rsar); |
|
599 ne2000_dma_update(s, 1); |
|
600 } |
|
601 #ifdef DEBUG_NE2000 |
|
602 printf("NE2000: asic read val=0x%04x\n", ret); |
|
603 #endif |
|
604 return ret; |
|
605 } |
|
606 |
|
607 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
|
608 { |
|
609 NE2000State *s = opaque; |
|
610 |
|
611 #ifdef DEBUG_NE2000 |
|
612 printf("NE2000: asic writel val=0x%04x\n", val); |
|
613 #endif |
|
614 if (s->rcnt == 0) |
|
615 return; |
|
616 /* 32 bit access */ |
|
617 ne2000_mem_writel(s, s->rsar, val); |
|
618 ne2000_dma_update(s, 4); |
|
619 } |
|
620 |
|
621 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
|
622 { |
|
623 NE2000State *s = opaque; |
|
624 int ret; |
|
625 |
|
626 /* 32 bit access */ |
|
627 ret = ne2000_mem_readl(s, s->rsar); |
|
628 ne2000_dma_update(s, 4); |
|
629 #ifdef DEBUG_NE2000 |
|
630 printf("NE2000: asic readl val=0x%04x\n", ret); |
|
631 #endif |
|
632 return ret; |
|
633 } |
|
634 |
|
635 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
|
636 { |
|
637 /* nothing to do (end of reset pulse) */ |
|
638 } |
|
639 |
|
640 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
|
641 { |
|
642 NE2000State *s = opaque; |
|
643 ne2000_reset(s); |
|
644 return 0; |
|
645 } |
|
646 |
|
647 static void ne2000_save(QEMUFile* f,void* opaque) |
|
648 { |
|
649 NE2000State* s=(NE2000State*)opaque; |
|
650 uint32_t tmp; |
|
651 |
|
652 if (s->pci_dev) |
|
653 pci_device_save(s->pci_dev, f); |
|
654 |
|
655 qemu_put_8s(f, &s->rxcr); |
|
656 |
|
657 qemu_put_8s(f, &s->cmd); |
|
658 qemu_put_be32s(f, &s->start); |
|
659 qemu_put_be32s(f, &s->stop); |
|
660 qemu_put_8s(f, &s->boundary); |
|
661 qemu_put_8s(f, &s->tsr); |
|
662 qemu_put_8s(f, &s->tpsr); |
|
663 qemu_put_be16s(f, &s->tcnt); |
|
664 qemu_put_be16s(f, &s->rcnt); |
|
665 qemu_put_be32s(f, &s->rsar); |
|
666 qemu_put_8s(f, &s->rsr); |
|
667 qemu_put_8s(f, &s->isr); |
|
668 qemu_put_8s(f, &s->dcfg); |
|
669 qemu_put_8s(f, &s->imr); |
|
670 qemu_put_buffer(f, s->phys, 6); |
|
671 qemu_put_8s(f, &s->curpag); |
|
672 qemu_put_buffer(f, s->mult, 8); |
|
673 tmp = 0; |
|
674 qemu_put_be32s(f, &tmp); /* ignored, was irq */ |
|
675 qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
|
676 } |
|
677 |
|
678 static int ne2000_load(QEMUFile* f,void* opaque,int version_id) |
|
679 { |
|
680 NE2000State* s=(NE2000State*)opaque; |
|
681 int ret; |
|
682 uint32_t tmp; |
|
683 |
|
684 if (version_id > 3) |
|
685 return -EINVAL; |
|
686 |
|
687 if (s->pci_dev && version_id >= 3) { |
|
688 ret = pci_device_load(s->pci_dev, f); |
|
689 if (ret < 0) |
|
690 return ret; |
|
691 } |
|
692 |
|
693 if (version_id >= 2) { |
|
694 qemu_get_8s(f, &s->rxcr); |
|
695 } else { |
|
696 s->rxcr = 0x0c; |
|
697 } |
|
698 |
|
699 qemu_get_8s(f, &s->cmd); |
|
700 qemu_get_be32s(f, &s->start); |
|
701 qemu_get_be32s(f, &s->stop); |
|
702 qemu_get_8s(f, &s->boundary); |
|
703 qemu_get_8s(f, &s->tsr); |
|
704 qemu_get_8s(f, &s->tpsr); |
|
705 qemu_get_be16s(f, &s->tcnt); |
|
706 qemu_get_be16s(f, &s->rcnt); |
|
707 qemu_get_be32s(f, &s->rsar); |
|
708 qemu_get_8s(f, &s->rsr); |
|
709 qemu_get_8s(f, &s->isr); |
|
710 qemu_get_8s(f, &s->dcfg); |
|
711 qemu_get_8s(f, &s->imr); |
|
712 qemu_get_buffer(f, s->phys, 6); |
|
713 qemu_get_8s(f, &s->curpag); |
|
714 qemu_get_buffer(f, s->mult, 8); |
|
715 qemu_get_be32s(f, &tmp); /* ignored */ |
|
716 qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
|
717 |
|
718 return 0; |
|
719 } |
|
720 |
|
721 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd) |
|
722 { |
|
723 NE2000State *s; |
|
724 |
|
725 s = qemu_mallocz(sizeof(NE2000State)); |
|
726 if (!s) |
|
727 return; |
|
728 |
|
729 register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
|
730 register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
|
731 |
|
732 register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
|
733 register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
|
734 register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
|
735 register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
|
736 |
|
737 register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
|
738 register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
|
739 s->irq = irq; |
|
740 memcpy(s->macaddr, nd->macaddr, 6); |
|
741 |
|
742 ne2000_reset(s); |
|
743 |
|
744 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, |
|
745 ne2000_can_receive, s); |
|
746 |
|
747 snprintf(s->vc->info_str, sizeof(s->vc->info_str), |
|
748 "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x", |
|
749 s->macaddr[0], |
|
750 s->macaddr[1], |
|
751 s->macaddr[2], |
|
752 s->macaddr[3], |
|
753 s->macaddr[4], |
|
754 s->macaddr[5]); |
|
755 |
|
756 register_savevm("ne2000", -1, 2, ne2000_save, ne2000_load, s); |
|
757 } |
|
758 |
|
759 /***********************************************************/ |
|
760 /* PCI NE2000 definitions */ |
|
761 |
|
762 typedef struct PCINE2000State { |
|
763 PCIDevice dev; |
|
764 NE2000State ne2000; |
|
765 } PCINE2000State; |
|
766 |
|
767 static void ne2000_map(PCIDevice *pci_dev, int region_num, |
|
768 uint32_t addr, uint32_t size, int type) |
|
769 { |
|
770 PCINE2000State *d = (PCINE2000State *)pci_dev; |
|
771 NE2000State *s = &d->ne2000; |
|
772 |
|
773 register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
|
774 register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
|
775 |
|
776 register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
|
777 register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
|
778 register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
|
779 register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
|
780 register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
|
781 register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
|
782 |
|
783 register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
|
784 register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
|
785 } |
|
786 |
|
787 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn) |
|
788 { |
|
789 PCINE2000State *d; |
|
790 NE2000State *s; |
|
791 uint8_t *pci_conf; |
|
792 |
|
793 d = (PCINE2000State *)pci_register_device(bus, |
|
794 "NE2000", sizeof(PCINE2000State), |
|
795 devfn, |
|
796 NULL, NULL); |
|
797 pci_conf = d->dev.config; |
|
798 pci_conf[0x00] = 0xec; // Realtek 8029 |
|
799 pci_conf[0x01] = 0x10; |
|
800 pci_conf[0x02] = 0x29; |
|
801 pci_conf[0x03] = 0x80; |
|
802 pci_conf[0x0a] = 0x00; // ethernet network controller |
|
803 pci_conf[0x0b] = 0x02; |
|
804 pci_conf[0x0e] = 0x00; // header_type |
|
805 pci_conf[0x3d] = 1; // interrupt pin 0 |
|
806 |
|
807 pci_register_io_region(&d->dev, 0, 0x100, |
|
808 PCI_ADDRESS_SPACE_IO, ne2000_map); |
|
809 s = &d->ne2000; |
|
810 s->irq = d->dev.irq[0]; |
|
811 s->pci_dev = (PCIDevice *)d; |
|
812 memcpy(s->macaddr, nd->macaddr, 6); |
|
813 ne2000_reset(s); |
|
814 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, |
|
815 ne2000_can_receive, s); |
|
816 |
|
817 snprintf(s->vc->info_str, sizeof(s->vc->info_str), |
|
818 "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x", |
|
819 s->macaddr[0], |
|
820 s->macaddr[1], |
|
821 s->macaddr[2], |
|
822 s->macaddr[3], |
|
823 s->macaddr[4], |
|
824 s->macaddr[5]); |
|
825 |
|
826 register_savevm("ne2000", -1, 3, ne2000_save, ne2000_load, s); |
|
827 } |