1 /*

     2  * TI OMAP processors emulation.

     3  *

     4  * Copyright (C) 2007-2008 Nokia Corporation

     5  * Written by Andrzej Zaborowski <andrew@openedhand.com>

     6  *

     7  * This program is free software; you can redistribute it and/or

     8  * modify it under the terms of the GNU General Public License as

     9  * published by the Free Software Foundation; either version 2 or

    10  * (at your option) version 3 of the License.

    11  *

    12  * This program is distributed in the hope that it will be useful,

    13  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    15  * GNU General Public License for more details.

    16  *

    17  * You should have received a copy of the GNU General Public License

    18  * along with this program; if not, write to the Free Software

    19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

    20  * MA 02111-1307 USA

    21  */

    22 #include "hw.h"

    23 #include "arm-misc.h"

    24 #include "omap.h"

    25 #include "sysemu.h"

    26 #include "qemu-timer.h"

    27 #include "qemu-char.h"

    28 #include "flash.h"

    29 #include "soc_dma.h"

    30 #include "audio/audio.h"

    31 

    32 /* GP timers */

    33 struct omap_gp_timer_s {

    34     qemu_irq irq;

    35     qemu_irq wkup;

    36     qemu_irq in;

    37     qemu_irq out;

    38     omap_clk clk;

    39     QEMUTimer *timer;

    40     QEMUTimer *match;

    41     struct omap_target_agent_s *ta;

    42 

    43     int in_val;

    44     int out_val;

    45     int64_t time;

    46     int64_t rate;

    47     int64_t ticks_per_sec;

    48 

    49     int16_t config;

    50     int status;

    51     int it_ena;

    52     int wu_ena;

    53     int enable;

    54     int inout;

    55     int capt2;

    56     int pt;

    57     enum {

    58         gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both

    59     } trigger;

    60     enum {

    61         gpt_capture_none, gpt_capture_rising,

    62         gpt_capture_falling, gpt_capture_both

    63     } capture;

    64     int scpwm;

    65     int ce;

    66     int pre;

    67     int ptv;

    68     int ar;

    69     int st;

    70     int posted;

    71     uint32_t val;

    72     uint32_t load_val;

    73     uint32_t capture_val[2];

    74     uint32_t match_val;

    75     int capt_num;

    76 

    77     uint16_t writeh;	/* LSB */

    78     uint16_t readh;	/* MSB */

    79 };

    80 

    81 #define GPT_TCAR_IT	(1 << 2)

    82 #define GPT_OVF_IT	(1 << 1)

    83 #define GPT_MAT_IT	(1 << 0)

    84 

    85 static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)

    86 {

    87     if (timer->it_ena & it) {

    88         if (!timer->status)

    89             qemu_irq_raise(timer->irq);

    90 

    91         timer->status |= it;

    92         /* Or are the status bits set even when masked?

    93          * i.e. is masking applied before or after the status register?  */

    94     }

    95 

    96     if (timer->wu_ena & it)

    97         qemu_irq_pulse(timer->wkup);

    98 }

    99 

   100 static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)

   101 {

   102     if (!timer->inout && timer->out_val != level) {

   103         timer->out_val = level;

   104         qemu_set_irq(timer->out, level);

   105     }

   106 }

   107 

   108 static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)

   109 {

   110     uint64_t distance;

   111 

   112     if (timer->st && timer->rate) {

   113         distance = qemu_get_clock(vm_clock) - timer->time;

   114         distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);

   115 

   116         if (distance >= 0xffffffff - timer->val)

   117             return 0xffffffff;

   118         else

   119             return timer->val + distance;

   120     } else

   121         return timer->val;

   122 }

   123 

   124 static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)

   125 {

   126     if (timer->st) {

   127         timer->val = omap_gp_timer_read(timer);

   128         timer->time = qemu_get_clock(vm_clock);

   129     }

   130 }

   131 

   132 static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)

   133 {

   134     int64_t expires, matches;

   135 

   136     if (timer->st && timer->rate) {

   137         expires = muldiv64(0x100000000ll - timer->val,

   138                         timer->ticks_per_sec, timer->rate);

   139         qemu_mod_timer(timer->timer, timer->time + expires);

   140 

   141         if (timer->ce && timer->match_val >= timer->val) {

   142             matches = muldiv64(timer->match_val - timer->val,

   143                             timer->ticks_per_sec, timer->rate);

   144             qemu_mod_timer(timer->match, timer->time + matches);

   145         } else

   146             qemu_del_timer(timer->match);

   147     } else {

   148         qemu_del_timer(timer->timer);

   149         qemu_del_timer(timer->match);

   150         omap_gp_timer_out(timer, timer->scpwm);

   151     }

   152 }

   153 

   154 static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)

   155 {

   156     if (timer->pt)

   157         /* TODO in overflow-and-match mode if the first event to

   158          * occur is the match, don't toggle.  */

   159         omap_gp_timer_out(timer, !timer->out_val);

   160     else

   161         /* TODO inverted pulse on timer->out_val == 1?  */

   162         qemu_irq_pulse(timer->out);

   163 }

   164 

   165 static void omap_gp_timer_tick(void *opaque)

   166 {

   167     struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;

   168 

   169     if (!timer->ar) {

   170         timer->st = 0;

   171         timer->val = 0;

   172     } else {

   173         timer->val = timer->load_val;

   174         timer->time = qemu_get_clock(vm_clock);

   175     }

   176 

   177     if (timer->trigger == gpt_trigger_overflow ||

   178                     timer->trigger == gpt_trigger_both)

   179         omap_gp_timer_trigger(timer);

   180 

   181     omap_gp_timer_intr(timer, GPT_OVF_IT);

   182     omap_gp_timer_update(timer);

   183 }

   184 

   185 static void omap_gp_timer_match(void *opaque)

   186 {

   187     struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;

   188 

   189     if (timer->trigger == gpt_trigger_both)

   190         omap_gp_timer_trigger(timer);

   191 

   192     omap_gp_timer_intr(timer, GPT_MAT_IT);

   193 }

   194 

   195 static void omap_gp_timer_input(void *opaque, int line, int on)

   196 {

   197     struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;

   198     int trigger;

   199 

   200     switch (s->capture) {

   201     default:

   202     case gpt_capture_none:

   203         trigger = 0;

   204         break;

   205     case gpt_capture_rising:

   206         trigger = !s->in_val && on;

   207         break;

   208     case gpt_capture_falling:

   209         trigger = s->in_val && !on;

   210         break;

   211     case gpt_capture_both:

   212         trigger = (s->in_val == !on);

   213         break;

   214     }

   215     s->in_val = on;

   216 

   217     if (s->inout && trigger && s->capt_num < 2) {

   218         s->capture_val[s->capt_num] = omap_gp_timer_read(s);

   219 

   220         if (s->capt2 == s->capt_num ++)

   221             omap_gp_timer_intr(s, GPT_TCAR_IT);

   222     }

   223 }

   224 

   225 static void omap_gp_timer_clk_update(void *opaque, int line, int on)

   226 {

   227     struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;

   228 

   229     omap_gp_timer_sync(timer);

   230     timer->rate = on ? omap_clk_getrate(timer->clk) : 0;

   231     omap_gp_timer_update(timer);

   232 }

   233 

   234 static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)

   235 {

   236     omap_clk_adduser(timer->clk,

   237                     qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]);

   238     timer->rate = omap_clk_getrate(timer->clk);

   239 }

   240 

   241 static void omap_gp_timer_reset(struct omap_gp_timer_s *s)

   242 {

   243     s->config = 0x000;

   244     s->status = 0;

   245     s->it_ena = 0;

   246     s->wu_ena = 0;

   247     s->inout = 0;

   248     s->capt2 = 0;

   249     s->capt_num = 0;

   250     s->pt = 0;

   251     s->trigger = gpt_trigger_none;

   252     s->capture = gpt_capture_none;

   253     s->scpwm = 0;

   254     s->ce = 0;

   255     s->pre = 0;

   256     s->ptv = 0;

   257     s->ar = 0;

   258     s->st = 0;

   259     s->posted = 1;

   260     s->val = 0x00000000;

   261     s->load_val = 0x00000000;

   262     s->capture_val[0] = 0x00000000;

   263     s->capture_val[1] = 0x00000000;

   264     s->match_val = 0x00000000;

   265     omap_gp_timer_update(s);

   266 }

   267 

   268 static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)

   269 {

   270     struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;

   271 

   272     switch (addr) {

   273     case 0x00:	/* TIDR */

   274         return 0x21;

   275 

   276     case 0x10:	/* TIOCP_CFG */

   277         return s->config;

   278 

   279     case 0x14:	/* TISTAT */

   280         /* ??? When's this bit reset? */

   281         return 1;						/* RESETDONE */

   282 

   283     case 0x18:	/* TISR */

   284         return s->status;

   285 

   286     case 0x1c:	/* TIER */

   287         return s->it_ena;

   288 

   289     case 0x20:	/* TWER */

   290         return s->wu_ena;

   291 

   292     case 0x24:	/* TCLR */

   293         return (s->inout << 14) |

   294                 (s->capt2 << 13) |

   295                 (s->pt << 12) |

   296                 (s->trigger << 10) |

   297                 (s->capture << 8) |

   298                 (s->scpwm << 7) |

   299                 (s->ce << 6) |

   300                 (s->pre << 5) |

   301                 (s->ptv << 2) |

   302                 (s->ar << 1) |

   303                 (s->st << 0);

   304 

   305     case 0x28:	/* TCRR */

   306         return omap_gp_timer_read(s);

   307 

   308     case 0x2c:	/* TLDR */

   309         return s->load_val;

   310 

   311     case 0x30:	/* TTGR */

   312         return 0xffffffff;

   313 

   314     case 0x34:	/* TWPS */

   315         return 0x00000000;	/* No posted writes pending.  */

   316 

   317     case 0x38:	/* TMAR */

   318         return s->match_val;

   319 

   320     case 0x3c:	/* TCAR1 */

   321         return s->capture_val[0];

   322 

   323     case 0x40:	/* TSICR */

   324         return s->posted << 2;

   325 

   326     case 0x44:	/* TCAR2 */

   327         return s->capture_val[1];

   328     }

   329 

   330     OMAP_BAD_REG(addr);

   331     return 0;

   332 }

   333 

   334 static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)

   335 {

   336     struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;

   337     uint32_t ret;

   338 

   339     if (addr & 2)

   340         return s->readh;

   341     else {

   342         ret = omap_gp_timer_readw(opaque, addr);

   343         s->readh = ret >> 16;

   344         return ret & 0xffff;

   345     }

   346 }

   347 

   348 static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {

   349     omap_badwidth_read32,

   350     omap_gp_timer_readh,

   351     omap_gp_timer_readw,

   352 };

   353 

   354 static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,

   355                 uint32_t value)

   356 {

   357     struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;

   358 

   359     switch (addr) {

   360     case 0x00:	/* TIDR */

   361     case 0x14:	/* TISTAT */

   362     case 0x34:	/* TWPS */

   363     case 0x3c:	/* TCAR1 */

   364     case 0x44:	/* TCAR2 */

   365         OMAP_RO_REG(addr);

   366         break;

   367 

   368     case 0x10:	/* TIOCP_CFG */

   369         s->config = value & 0x33d;

   370         if (((value >> 3) & 3) == 3)				/* IDLEMODE */

   371             fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",

   372                             __FUNCTION__);

   373         if (value & 2)						/* SOFTRESET */

   374             omap_gp_timer_reset(s);

   375         break;

   376 

   377     case 0x18:	/* TISR */

   378         if (value & GPT_TCAR_IT)

   379             s->capt_num = 0;

   380         if (s->status && !(s->status &= ~value))

   381             qemu_irq_lower(s->irq);

   382         break;

   383 

   384     case 0x1c:	/* TIER */

   385         s->it_ena = value & 7;

   386         break;

   387 

   388     case 0x20:	/* TWER */

   389         s->wu_ena = value & 7;

   390         break;

   391 

   392     case 0x24:	/* TCLR */

   393         omap_gp_timer_sync(s);

   394         s->inout = (value >> 14) & 1;

   395         s->capt2 = (value >> 13) & 1;

   396         s->pt = (value >> 12) & 1;

   397         s->trigger = (value >> 10) & 3;

   398         if (s->capture == gpt_capture_none &&

   399                         ((value >> 8) & 3) != gpt_capture_none)

   400             s->capt_num = 0;

   401         s->capture = (value >> 8) & 3;

   402         s->scpwm = (value >> 7) & 1;

   403         s->ce = (value >> 6) & 1;

   404         s->pre = (value >> 5) & 1;

   405         s->ptv = (value >> 2) & 7;

   406         s->ar = (value >> 1) & 1;

   407         s->st = (value >> 0) & 1;

   408         if (s->inout && s->trigger != gpt_trigger_none)

   409             fprintf(stderr, "%s: GP timer pin must be an output "

   410                             "for this trigger mode\n", __FUNCTION__);

   411         if (!s->inout && s->capture != gpt_capture_none)

   412             fprintf(stderr, "%s: GP timer pin must be an input "

   413                             "for this capture mode\n", __FUNCTION__);

   414         if (s->trigger == gpt_trigger_none)

   415             omap_gp_timer_out(s, s->scpwm);

   416         /* TODO: make sure this doesn't overflow 32-bits */

   417         s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0);

   418         omap_gp_timer_update(s);

   419         break;

   420 

   421     case 0x28:	/* TCRR */

   422         s->time = qemu_get_clock(vm_clock);

   423         s->val = value;

   424         omap_gp_timer_update(s);

   425         break;

   426 

   427     case 0x2c:	/* TLDR */

   428         s->load_val = value;

   429         break;

   430 

   431     case 0x30:	/* TTGR */

   432         s->time = qemu_get_clock(vm_clock);

   433         s->val = s->load_val;

   434         omap_gp_timer_update(s);

   435         break;

   436 

   437     case 0x38:	/* TMAR */

   438         omap_gp_timer_sync(s);

   439         s->match_val = value;

   440         omap_gp_timer_update(s);

   441         break;

   442 

   443     case 0x40:	/* TSICR */

   444         s->posted = (value >> 2) & 1;

   445         if (value & 2)	/* How much exactly are we supposed to reset? */

   446             omap_gp_timer_reset(s);

   447         break;

   448 

   449     default:

   450         OMAP_BAD_REG(addr);

   451     }

   452 }

   453 

   454 static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,

   455                 uint32_t value)

   456 {

   457     struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;

   458 

   459     if (addr & 2)

   460         return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);

   461     else

   462         s->writeh = (uint16_t) value;

   463 }

   464 

   465 static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {

   466     omap_badwidth_write32,

   467     omap_gp_timer_writeh,

   468     omap_gp_timer_write,

   469 };

   470 

   471 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,

   472                 qemu_irq irq, omap_clk fclk, omap_clk iclk)

   473 {

   474     int iomemtype;

   475     struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)

   476             qemu_mallocz(sizeof(struct omap_gp_timer_s));

   477 

   478     s->ta = ta;

   479     s->irq = irq;

   480     s->clk = fclk;

   481     s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s);

   482     s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s);

   483     s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];

   484     omap_gp_timer_reset(s);

   485     omap_gp_timer_clk_setup(s);

   486 

   487     iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,

   488                     omap_gp_timer_writefn, s);

   489     omap_l4_attach(ta, 0, iomemtype);

   490 

   491     return s;

   492 }

   493 

   494 /* 32-kHz Sync Timer of the OMAP2 */

   495 static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {

   496     return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec);

   497 }

   498 

   499 static void omap_synctimer_reset(struct omap_synctimer_s *s)

   500 {

   501     s->val = omap_synctimer_read(s);

   502 }

   503 

   504 static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)

   505 {

   506     struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;

   507 

   508     switch (addr) {

   509     case 0x00:	/* 32KSYNCNT_REV */

   510         return 0x21;

   511 

   512     case 0x10:	/* CR */

   513         return omap_synctimer_read(s) - s->val;

   514     }

   515 

   516     OMAP_BAD_REG(addr);

   517     return 0;

   518 }

   519 

   520 static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)

   521 {

   522     struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;

   523     uint32_t ret;

   524 

   525     if (addr & 2)

   526         return s->readh;

   527     else {

   528         ret = omap_synctimer_readw(opaque, addr);

   529         s->readh = ret >> 16;

   530         return ret & 0xffff;

   531     }

   532 }

   533 

   534 static CPUReadMemoryFunc *omap_synctimer_readfn[] = {

   535     omap_badwidth_read32,

   536     omap_synctimer_readh,

   537     omap_synctimer_readw,

   538 };

   539 

   540 static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,

   541                 uint32_t value)

   542 {

   543     OMAP_BAD_REG(addr);

   544 }

   545 

   546 static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {

   547     omap_badwidth_write32,

   548     omap_synctimer_write,

   549     omap_synctimer_write,

   550 };

   551 

   552 void omap_synctimer_init(struct omap_target_agent_s *ta,

   553                 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)

   554 {

   555     struct omap_synctimer_s *s = &mpu->synctimer;

   556 

   557     omap_synctimer_reset(s);

   558     omap_l4_attach(ta, 0, l4_register_io_memory(0,

   559                       omap_synctimer_readfn, omap_synctimer_writefn, s));

   560 }

   561 

   562 /* General-Purpose Interface of OMAP2 */

   563 struct omap2_gpio_s {

   564     qemu_irq irq[2];

   565     qemu_irq wkup;

   566     qemu_irq *in;

   567     qemu_irq handler[32];

   568 

   569     uint8_t config[2];

   570     uint32_t inputs;

   571     uint32_t outputs;

   572     uint32_t dir;

   573     uint32_t level[2];

   574     uint32_t edge[2];

   575     uint32_t mask[2];

   576     uint32_t wumask;

   577     uint32_t ints[2];

   578     uint32_t debounce;

   579     uint8_t delay;

   580 };

   581 

   582 static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s,

   583                 int line)

   584 {

   585     qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);

   586 }

   587 

   588 static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line)

   589 {

   590     if (!(s->config[0] & (1 << 2)))			/* ENAWAKEUP */

   591         return;

   592     if (!(s->config[0] & (3 << 3)))			/* Force Idle */

   593         return;

   594     if (!(s->wumask & (1 << line)))

   595         return;

   596 

   597     qemu_irq_raise(s->wkup);

   598 }

   599 

   600 static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s,

   601                 uint32_t diff)

   602 {

   603     int ln;

   604 

   605     s->outputs ^= diff;

   606     diff &= ~s->dir;

   607     while ((ln = ffs(diff))) {

   608         ln --;

   609         qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);

   610         diff &= ~(1 << ln);

   611     }

   612 }

   613 

   614 static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line)

   615 {

   616     s->ints[line] |= s->dir &

   617             ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));

   618     omap_gpio_module_int_update(s, line);

   619 }

   620 

   621 static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)

   622 {

   623     s->ints[0] |= 1 << line;

   624     omap_gpio_module_int_update(s, 0);

   625     s->ints[1] |= 1 << line;

   626     omap_gpio_module_int_update(s, 1);

   627     omap_gpio_module_wake(s, line);

   628 }

   629 

   630 static void omap_gpio_module_set(void *opaque, int line, int level)

   631 {

   632     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;

   633 

   634     if (level) {

   635         if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))

   636             omap_gpio_module_int(s, line);

   637         s->inputs |= 1 << line;

   638     } else {

   639         if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))

   640             omap_gpio_module_int(s, line);

   641         s->inputs &= ~(1 << line);

   642     }

   643 }

   644 

   645 static void omap_gpio_module_reset(struct omap2_gpio_s *s)

   646 {

   647     s->config[0] = 0;

   648     s->config[1] = 2;

   649     s->ints[0] = 0;

   650     s->ints[1] = 0;

   651     s->mask[0] = 0;

   652     s->mask[1] = 0;

   653     s->wumask = 0;

   654     s->dir = ~0;

   655     s->level[0] = 0;

   656     s->level[1] = 0;

   657     s->edge[0] = 0;

   658     s->edge[1] = 0;

   659     s->debounce = 0;

   660     s->delay = 0;

   661 }

   662 

   663 static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)

   664 {

   665     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;

   666 

   667     switch (addr) {

   668     case 0x00:	/* GPIO_REVISION */

   669         return 0x18;

   670 

   671     case 0x10:	/* GPIO_SYSCONFIG */

   672         return s->config[0];

   673 

   674     case 0x14:	/* GPIO_SYSSTATUS */

   675         return 0x01;

   676 

   677     case 0x18:	/* GPIO_IRQSTATUS1 */

   678         return s->ints[0];

   679 

   680     case 0x1c:	/* GPIO_IRQENABLE1 */

   681     case 0x60:	/* GPIO_CLEARIRQENABLE1 */

   682     case 0x64:	/* GPIO_SETIRQENABLE1 */

   683         return s->mask[0];

   684 

   685     case 0x20:	/* GPIO_WAKEUPENABLE */

   686     case 0x80:	/* GPIO_CLEARWKUENA */

   687     case 0x84:	/* GPIO_SETWKUENA */

   688         return s->wumask;

   689 

   690     case 0x28:	/* GPIO_IRQSTATUS2 */

   691         return s->ints[1];

   692 

   693     case 0x2c:	/* GPIO_IRQENABLE2 */

   694     case 0x70:	/* GPIO_CLEARIRQENABLE2 */

   695     case 0x74:	/* GPIO_SETIREQNEABLE2 */

   696         return s->mask[1];

   697 

   698     case 0x30:	/* GPIO_CTRL */

   699         return s->config[1];

   700 

   701     case 0x34:	/* GPIO_OE */

   702         return s->dir;

   703 

   704     case 0x38:	/* GPIO_DATAIN */

   705         return s->inputs;

   706 

   707     case 0x3c:	/* GPIO_DATAOUT */

   708     case 0x90:	/* GPIO_CLEARDATAOUT */

   709     case 0x94:	/* GPIO_SETDATAOUT */

   710         return s->outputs;

   711 

   712     case 0x40:	/* GPIO_LEVELDETECT0 */

   713         return s->level[0];

   714 

   715     case 0x44:	/* GPIO_LEVELDETECT1 */

   716         return s->level[1];

   717 

   718     case 0x48:	/* GPIO_RISINGDETECT */

   719         return s->edge[0];

   720 

   721     case 0x4c:	/* GPIO_FALLINGDETECT */

   722         return s->edge[1];

   723 

   724     case 0x50:	/* GPIO_DEBOUNCENABLE */

   725         return s->debounce;

   726 

   727     case 0x54:	/* GPIO_DEBOUNCINGTIME */

   728         return s->delay;

   729     }

   730 

   731     OMAP_BAD_REG(addr);

   732     return 0;

   733 }

   734 

   735 static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,

   736                 uint32_t value)

   737 {

   738     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;

   739     uint32_t diff;

   740     int ln;

   741 

   742     switch (addr) {

   743     case 0x00:	/* GPIO_REVISION */

   744     case 0x14:	/* GPIO_SYSSTATUS */

   745     case 0x38:	/* GPIO_DATAIN */

   746         OMAP_RO_REG(addr);

   747         break;

   748 

   749     case 0x10:	/* GPIO_SYSCONFIG */

   750         if (((value >> 3) & 3) == 3)

   751             fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);

   752         if (value & 2)

   753             omap_gpio_module_reset(s);

   754         s->config[0] = value & 0x1d;

   755         break;

   756 

   757     case 0x18:	/* GPIO_IRQSTATUS1 */

   758         if (s->ints[0] & value) {

   759             s->ints[0] &= ~value;

   760             omap_gpio_module_level_update(s, 0);

   761         }

   762         break;

   763 

   764     case 0x1c:	/* GPIO_IRQENABLE1 */

   765         s->mask[0] = value;

   766         omap_gpio_module_int_update(s, 0);

   767         break;

   768 

   769     case 0x20:	/* GPIO_WAKEUPENABLE */

   770         s->wumask = value;

   771         break;

   772 

   773     case 0x28:	/* GPIO_IRQSTATUS2 */

   774         if (s->ints[1] & value) {

   775             s->ints[1] &= ~value;

   776             omap_gpio_module_level_update(s, 1);

   777         }

   778         break;

   779 

   780     case 0x2c:	/* GPIO_IRQENABLE2 */

   781         s->mask[1] = value;

   782         omap_gpio_module_int_update(s, 1);

   783         break;

   784 

   785     case 0x30:	/* GPIO_CTRL */

   786         s->config[1] = value & 7;

   787         break;

   788 

   789     case 0x34:	/* GPIO_OE */

   790         diff = s->outputs & (s->dir ^ value);

   791         s->dir = value;

   792 

   793         value = s->outputs & ~s->dir;

   794         while ((ln = ffs(diff))) {

   795             diff &= ~(1 <<-- ln);

   796             qemu_set_irq(s->handler[ln], (value >> ln) & 1);

   797         }

   798 

   799         omap_gpio_module_level_update(s, 0);

   800         omap_gpio_module_level_update(s, 1);

   801         break;

   802 

   803     case 0x3c:	/* GPIO_DATAOUT */

   804         omap_gpio_module_out_update(s, s->outputs ^ value);

   805         break;

   806 

   807     case 0x40:	/* GPIO_LEVELDETECT0 */

   808         s->level[0] = value;

   809         omap_gpio_module_level_update(s, 0);

   810         omap_gpio_module_level_update(s, 1);

   811         break;

   812 

   813     case 0x44:	/* GPIO_LEVELDETECT1 */

   814         s->level[1] = value;

   815         omap_gpio_module_level_update(s, 0);

   816         omap_gpio_module_level_update(s, 1);

   817         break;

   818 

   819     case 0x48:	/* GPIO_RISINGDETECT */

   820         s->edge[0] = value;

   821         break;

   822 

   823     case 0x4c:	/* GPIO_FALLINGDETECT */

   824         s->edge[1] = value;

   825         break;

   826 

   827     case 0x50:	/* GPIO_DEBOUNCENABLE */

   828         s->debounce = value;

   829         break;

   830 

   831     case 0x54:	/* GPIO_DEBOUNCINGTIME */

   832         s->delay = value;

   833         break;

   834 

   835     case 0x60:	/* GPIO_CLEARIRQENABLE1 */

   836         s->mask[0] &= ~value;

   837         omap_gpio_module_int_update(s, 0);

   838         break;

   839 

   840     case 0x64:	/* GPIO_SETIRQENABLE1 */

   841         s->mask[0] |= value;

   842         omap_gpio_module_int_update(s, 0);

   843         break;

   844 

   845     case 0x70:	/* GPIO_CLEARIRQENABLE2 */

   846         s->mask[1] &= ~value;

   847         omap_gpio_module_int_update(s, 1);

   848         break;

   849 

   850     case 0x74:	/* GPIO_SETIREQNEABLE2 */

   851         s->mask[1] |= value;

   852         omap_gpio_module_int_update(s, 1);

   853         break;

   854 

   855     case 0x80:	/* GPIO_CLEARWKUENA */

   856         s->wumask &= ~value;

   857         break;

   858 

   859     case 0x84:	/* GPIO_SETWKUENA */

   860         s->wumask |= value;

   861         break;

   862 

   863     case 0x90:	/* GPIO_CLEARDATAOUT */

   864         omap_gpio_module_out_update(s, s->outputs & value);

   865         break;

   866 

   867     case 0x94:	/* GPIO_SETDATAOUT */

   868         omap_gpio_module_out_update(s, ~s->outputs & value);

   869         break;

   870 

   871     default:

   872         OMAP_BAD_REG(addr);

   873         return;

   874     }

   875 }

   876 

   877 static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)

   878 {

   879     return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);

   880 }

   881 

   882 static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,

   883                 uint32_t value)

   884 {

   885     uint32_t cur = 0;

   886     uint32_t mask = 0xffff;

   887 

   888     switch (addr & ~3) {

   889     case 0x00:	/* GPIO_REVISION */

   890     case 0x14:	/* GPIO_SYSSTATUS */

   891     case 0x38:	/* GPIO_DATAIN */

   892         OMAP_RO_REG(addr);

   893         break;

   894 

   895     case 0x10:	/* GPIO_SYSCONFIG */

   896     case 0x1c:	/* GPIO_IRQENABLE1 */

   897     case 0x20:	/* GPIO_WAKEUPENABLE */

   898     case 0x2c:	/* GPIO_IRQENABLE2 */

   899     case 0x30:	/* GPIO_CTRL */

   900     case 0x34:	/* GPIO_OE */

   901     case 0x3c:	/* GPIO_DATAOUT */

   902     case 0x40:	/* GPIO_LEVELDETECT0 */

   903     case 0x44:	/* GPIO_LEVELDETECT1 */

   904     case 0x48:	/* GPIO_RISINGDETECT */

   905     case 0x4c:	/* GPIO_FALLINGDETECT */

   906     case 0x50:	/* GPIO_DEBOUNCENABLE */

   907     case 0x54:	/* GPIO_DEBOUNCINGTIME */

   908         cur = omap_gpio_module_read(opaque, addr & ~3) &

   909                 ~(mask << ((addr & 3) << 3));

   910 

   911         /* Fall through.  */

   912     case 0x18:	/* GPIO_IRQSTATUS1 */

   913     case 0x28:	/* GPIO_IRQSTATUS2 */

   914     case 0x60:	/* GPIO_CLEARIRQENABLE1 */

   915     case 0x64:	/* GPIO_SETIRQENABLE1 */

   916     case 0x70:	/* GPIO_CLEARIRQENABLE2 */

   917     case 0x74:	/* GPIO_SETIREQNEABLE2 */

   918     case 0x80:	/* GPIO_CLEARWKUENA */

   919     case 0x84:	/* GPIO_SETWKUENA */

   920     case 0x90:	/* GPIO_CLEARDATAOUT */

   921     case 0x94:	/* GPIO_SETDATAOUT */

   922         value <<= (addr & 3) << 3;

   923         omap_gpio_module_write(opaque, addr, cur | value);

   924         break;

   925 

   926     default:

   927         OMAP_BAD_REG(addr);

   928         return;

   929     }

   930 }

   931 

   932 static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {

   933     omap_gpio_module_readp,

   934     omap_gpio_module_readp,

   935     omap_gpio_module_read,

   936 };

   937 

   938 static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {

   939     omap_gpio_module_writep,

   940     omap_gpio_module_writep,

   941     omap_gpio_module_write,

   942 };

   943 

   944 static void omap_gpio_module_init(struct omap2_gpio_s *s,

   945                 struct omap_target_agent_s *ta, int region,

   946                 qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,

   947                 omap_clk fclk, omap_clk iclk)

   948 {

   949     int iomemtype;

   950 

   951     s->irq[0] = mpu;

   952     s->irq[1] = dsp;

   953     s->wkup = wkup;

   954     s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);

   955 

   956     iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,

   957                     omap_gpio_module_writefn, s);

   958     omap_l4_attach(ta, region, iomemtype);

   959 }

   960 

   961 struct omap_gpif_s {

   962     struct omap2_gpio_s module[5];

   963     int modules;

   964 

   965     int autoidle;

   966     int gpo;

   967 };

   968 

   969 static void omap_gpif_reset(struct omap_gpif_s *s)

   970 {

   971     int i;

   972 

   973     for (i = 0; i < s->modules; i ++)

   974         omap_gpio_module_reset(s->module + i);

   975 

   976     s->autoidle = 0;

   977     s->gpo = 0;

   978 }

   979 

   980 static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)

   981 {

   982     struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;

   983 

   984     switch (addr) {

   985     case 0x00:	/* IPGENERICOCPSPL_REVISION */

   986         return 0x18;

   987 

   988     case 0x10:	/* IPGENERICOCPSPL_SYSCONFIG */

   989         return s->autoidle;

   990 

   991     case 0x14:	/* IPGENERICOCPSPL_SYSSTATUS */

   992         return 0x01;

   993 

   994     case 0x18:	/* IPGENERICOCPSPL_IRQSTATUS */

   995         return 0x00;

   996 

   997     case 0x40:	/* IPGENERICOCPSPL_GPO */

   998         return s->gpo;

   999 

  1000     case 0x50:	/* IPGENERICOCPSPL_GPI */

  1001         return 0x00;

  1002     }

  1003 

  1004     OMAP_BAD_REG(addr);

  1005     return 0;

  1006 }

  1007 

  1008 static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,

  1009                 uint32_t value)

  1010 {

  1011     struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;

  1012 

  1013     switch (addr) {

  1014     case 0x00:	/* IPGENERICOCPSPL_REVISION */

  1015     case 0x14:	/* IPGENERICOCPSPL_SYSSTATUS */

  1016     case 0x18:	/* IPGENERICOCPSPL_IRQSTATUS */

  1017     case 0x50:	/* IPGENERICOCPSPL_GPI */

  1018         OMAP_RO_REG(addr);

  1019         break;

  1020 

  1021     case 0x10:	/* IPGENERICOCPSPL_SYSCONFIG */

  1022         if (value & (1 << 1))					/* SOFTRESET */

  1023             omap_gpif_reset(s);

  1024         s->autoidle = value & 1;

  1025         break;

  1026 

  1027     case 0x40:	/* IPGENERICOCPSPL_GPO */

  1028         s->gpo = value & 1;

  1029         break;

  1030 

  1031     default:

  1032         OMAP_BAD_REG(addr);

  1033         return;

  1034     }

  1035 }

  1036 

  1037 static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {

  1038     omap_gpif_top_read,

  1039     omap_gpif_top_read,

  1040     omap_gpif_top_read,

  1041 };

  1042 

  1043 static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {

  1044     omap_gpif_top_write,

  1045     omap_gpif_top_write,

  1046     omap_gpif_top_write,

  1047 };

  1048 

  1049 struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,

  1050                 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)

  1051 {

  1052     int iomemtype, i;

  1053     struct omap_gpif_s *s = (struct omap_gpif_s *)

  1054             qemu_mallocz(sizeof(struct omap_gpif_s));

  1055     int region[4] = { 0, 2, 4, 5 };

  1056 

  1057     s->modules = modules;

  1058     for (i = 0; i < modules; i ++)

  1059         omap_gpio_module_init(s->module + i, ta, region[i],

  1060                         irq[i], 0, 0, fclk[i], iclk);

  1061 

  1062     omap_gpif_reset(s);

  1063 

  1064     iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,

  1065                     omap_gpif_top_writefn, s);

  1066     omap_l4_attach(ta, 1, iomemtype);

  1067 

  1068     return s;

  1069 }

  1070 

  1071 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)

  1072 {

  1073     if (start >= s->modules * 32 || start < 0)

  1074         cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",

  1075                         __FUNCTION__, start);

  1076     return s->module[start >> 5].in + (start & 31);

  1077 }

  1078 

  1079 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)

  1080 {

  1081     if (line >= s->modules * 32 || line < 0)

  1082         cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);

  1083     s->module[line >> 5].handler[line & 31] = handler;

  1084 }

  1085 

  1086 /* Multichannel SPI */

  1087 struct omap_mcspi_s {

  1088     qemu_irq irq;

  1089     int chnum;

  1090 

  1091     uint32_t sysconfig;

  1092     uint32_t systest;

  1093     uint32_t irqst;

  1094     uint32_t irqen;

  1095     uint32_t wken;

  1096     uint32_t control;

  1097 

  1098     struct omap_mcspi_ch_s {

  1099         qemu_irq txdrq;

  1100         qemu_irq rxdrq;

  1101         uint32_t (*txrx)(void *opaque, uint32_t, int);

  1102         void *opaque;

  1103 

  1104         uint32_t tx;

  1105         uint32_t rx;

  1106 

  1107         uint32_t config;

  1108         uint32_t status;

  1109         uint32_t control;

  1110     } ch[4];

  1111 };

  1112 

  1113 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)

  1114 {

  1115     qemu_set_irq(s->irq, s->irqst & s->irqen);

  1116 }

  1117 

  1118 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)

  1119 {

  1120     qemu_set_irq(ch->txdrq,

  1121                     (ch->control & 1) &&		/* EN */

  1122                     (ch->config & (1 << 14)) &&		/* DMAW */

  1123                     (ch->status & (1 << 1)) &&		/* TXS */

  1124                     ((ch->config >> 12) & 3) != 1);	/* TRM */

  1125     qemu_set_irq(ch->rxdrq,

  1126                     (ch->control & 1) &&		/* EN */

  1127                     (ch->config & (1 << 15)) &&		/* DMAW */

  1128                     (ch->status & (1 << 0)) &&		/* RXS */

  1129                     ((ch->config >> 12) & 3) != 2);	/* TRM */

  1130 }

  1131 

  1132 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)

  1133 {

  1134     struct omap_mcspi_ch_s *ch = s->ch + chnum;

  1135