1 /*

     2  * TI OMAP DMA gigacell.

     3  *

     4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>

     5  * Copyright (C) 2007-2008 Lauro Ramos Venancio  <lauro.venancio@indt.org.br>

     6  *

     7  * This program is free software; you can redistribute it and/or

     8  * modify it under the terms of the GNU General Public License as

     9  * published by the Free Software Foundation; either version 2 of

    10  * the License, or (at your option) any later version.

    11  *

    12  * This program is distributed in the hope that it will be useful,

    13  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    15  * GNU General Public License for more details.

    16  *

    17  * You should have received a copy of the GNU General Public License

    18  * along with this program; if not, write to the Free Software

    19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

    20  * MA 02111-1307 USA

    21  */

    22 #include "qemu-common.h"

    23 #include "qemu-timer.h"

    24 #include "omap.h"

    25 #include "irq.h"

    26 #include "soc_dma.h"

    27 

    28 struct omap_dma_channel_s {

    29     /* transfer data */

    30     int burst[2];

    31     int pack[2];

    32     int endian[2];

    33     int endian_lock[2];

    34     int translate[2];

    35     enum omap_dma_port port[2];

    36     target_phys_addr_t addr[2];

    37     omap_dma_addressing_t mode[2];

    38     uint32_t elements;

    39     uint16_t frames;

    40     int32_t frame_index[2];

    41     int16_t element_index[2];

    42     int data_type;

    43 

    44     /* transfer type */

    45     int transparent_copy;

    46     int constant_fill;

    47     uint32_t color;

    48     int prefetch;

    49 

    50     /* auto init and linked channel data */

    51     int end_prog;

    52     int repeat;

    53     int auto_init;

    54     int link_enabled;

    55     int link_next_ch;

    56 

    57     /* interruption data */

    58     int interrupts;

    59     int status;

    60     int cstatus;

    61 

    62     /* state data */

    63     int active;

    64     int enable;

    65     int sync;

    66     int src_sync;

    67     int pending_request;

    68     int waiting_end_prog;

    69     uint16_t cpc;

    70     int set_update;

    71 

    72     /* sync type */

    73     int fs;

    74     int bs;

    75 

    76     /* compatibility */

    77     int omap_3_1_compatible_disable;

    78 

    79     qemu_irq irq;

    80     struct omap_dma_channel_s *sibling;

    81 

    82     struct omap_dma_reg_set_s {

    83         target_phys_addr_t src, dest;

    84         int frame;

    85         int element;

    86         int pck_element;

    87         int frame_delta[2];

    88         int elem_delta[2];

    89         int frames;

    90         int elements;

    91         int pck_elements;

    92     } active_set;

    93 

    94     struct soc_dma_ch_s *dma;

    95 

    96     /* unused parameters */

    97     int write_mode;

    98     int priority;

    99     int interleave_disabled;

   100     int type;

   101     int suspend;

   102     int buf_disable;

   103 };

   104 

   105 struct omap_dma_s {

   106     struct soc_dma_s *dma;

   107 

   108     struct omap_mpu_state_s *mpu;

   109     omap_clk clk;

   110     qemu_irq irq[4];

   111     void (*intr_update)(struct omap_dma_s *s);

   112     enum omap_dma_model model;

   113     int omap_3_1_mapping_disabled;

   114 

   115     uint32_t gcr;

   116     uint32_t ocp;

   117     uint32_t caps[5];

   118     uint32_t irqen[4];

   119     uint32_t irqstat[4];

   120 

   121     int chans;

   122     struct omap_dma_channel_s ch[32];

   123     struct omap_dma_lcd_channel_s lcd_ch;

   124 };

   125 

   126 /* Interrupts */

   127 #define TIMEOUT_INTR    (1 << 0)

   128 #define EVENT_DROP_INTR (1 << 1)

   129 #define HALF_FRAME_INTR (1 << 2)

   130 #define END_FRAME_INTR  (1 << 3)

   131 #define LAST_FRAME_INTR (1 << 4)

   132 #define END_BLOCK_INTR  (1 << 5)

   133 #define SYNC            (1 << 6)

   134 #define END_PKT_INTR	(1 << 7)

   135 #define TRANS_ERR_INTR	(1 << 8)

   136 #define MISALIGN_INTR	(1 << 11)

   137 

   138 static inline void omap_dma_interrupts_update(struct omap_dma_s *s)

   139 {

   140     return s->intr_update(s);

   141 }

   142 

   143 static void omap_dma_channel_load(struct omap_dma_channel_s *ch)

   144 {

   145     struct omap_dma_reg_set_s *a = &ch->active_set;

   146     int i, normal;

   147     int omap_3_1 = !ch->omap_3_1_compatible_disable;

   148 

   149     /*

   150      * TODO: verify address ranges and alignment

   151      * TODO: port endianness

   152      */

   153 

   154     a->src = ch->addr[0];

   155     a->dest = ch->addr[1];

   156     a->frames = ch->frames;

   157     a->elements = ch->elements;

   158     a->pck_elements = ch->frame_index[!ch->src_sync];

   159     a->frame = 0;

   160     a->element = 0;

   161     a->pck_element = 0;

   162 

   163     if (unlikely(!ch->elements || !ch->frames)) {

   164         printf("%s: bad DMA request\n", __FUNCTION__);

   165         return;

   166     }

   167 

   168     for (i = 0; i < 2; i ++)

   169         switch (ch->mode[i]) {

   170         case constant:

   171             a->elem_delta[i] = 0;

   172             a->frame_delta[i] = 0;

   173             break;

   174         case post_incremented:

   175             a->elem_delta[i] = ch->data_type;

   176             a->frame_delta[i] = 0;

   177             break;

   178         case single_index:

   179             a->elem_delta[i] = ch->data_type +

   180                     ch->element_index[omap_3_1 ? 0 : i] - 1;

   181             a->frame_delta[i] = 0;

   182             break;

   183         case double_index:

   184             a->elem_delta[i] = ch->data_type +

   185                     ch->element_index[omap_3_1 ? 0 : i] - 1;

   186             a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -

   187                     ch->element_index[omap_3_1 ? 0 : i];

   188             break;

   189         default:

   190             break;

   191         }

   192 

   193     normal = !ch->transparent_copy && !ch->constant_fill &&

   194             /* FIFO is big-endian so either (ch->endian[n] == 1) OR

   195              * (ch->endian_lock[n] == 1) mean no endianism conversion.  */

   196             (ch->endian[0] | ch->endian_lock[0]) ==

   197             (ch->endian[1] | ch->endian_lock[1]);

   198     for (i = 0; i < 2; i ++) {

   199         /* TODO: for a->frame_delta[i] > 0 still use the fast path, just

   200          * limit min_elems in omap_dma_transfer_setup to the nearest frame

   201          * end.  */

   202         if (!a->elem_delta[i] && normal &&

   203                         (a->frames == 1 || !a->frame_delta[i]))

   204             ch->dma->type[i] = soc_dma_access_const;

   205         else if (a->elem_delta[i] == ch->data_type && normal &&

   206                         (a->frames == 1 || !a->frame_delta[i]))

   207             ch->dma->type[i] = soc_dma_access_linear;

   208         else

   209             ch->dma->type[i] = soc_dma_access_other;

   210 

   211         ch->dma->vaddr[i] = ch->addr[i];

   212     }

   213     soc_dma_ch_update(ch->dma);

   214 }

   215 

   216 static void omap_dma_activate_channel(struct omap_dma_s *s,

   217                 struct omap_dma_channel_s *ch)

   218 {

   219     if (!ch->active) {

   220         if (ch->set_update) {

   221             /* It's not clear when the active set is supposed to be

   222              * loaded from registers.  We're already loading it when the

   223              * channel is enabled, and for some guests this is not enough

   224              * but that may be also because of a race condition (no

   225              * delays in qemu) in the guest code, which we're just

   226              * working around here.  */

   227             omap_dma_channel_load(ch);

   228             ch->set_update = 0;

   229         }

   230 

   231         ch->active = 1;

   232         soc_dma_set_request(ch->dma, 1);

   233         if (ch->sync)

   234             ch->status |= SYNC;

   235     }

   236 }

   237 

   238 static void omap_dma_deactivate_channel(struct omap_dma_s *s,

   239                 struct omap_dma_channel_s *ch)

   240 {

   241     /* Update cpc */

   242     ch->cpc = ch->active_set.dest & 0xffff;

   243 

   244     if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {

   245         /* Don't deactivate the channel */

   246         ch->pending_request = 0;

   247         return;

   248     }

   249 

   250     /* Don't deactive the channel if it is synchronized and the DMA request is

   251        active */

   252     if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))

   253         return;

   254 

   255     if (ch->active) {

   256         ch->active = 0;

   257         ch->status &= ~SYNC;

   258         soc_dma_set_request(ch->dma, 0);

   259     }

   260 }

   261 

   262 static void omap_dma_enable_channel(struct omap_dma_s *s,

   263                 struct omap_dma_channel_s *ch)

   264 {

   265     if (!ch->enable) {

   266         ch->enable = 1;

   267         ch->waiting_end_prog = 0;

   268         omap_dma_channel_load(ch);

   269         /* TODO: theoretically if ch->sync && ch->prefetch &&

   270          * !s->dma->drqbmp[ch->sync], we should also activate and fetch

   271          * from source and then stall until signalled.  */

   272         if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))

   273             omap_dma_activate_channel(s, ch);

   274     }

   275 }

   276 

   277 static void omap_dma_disable_channel(struct omap_dma_s *s,

   278                 struct omap_dma_channel_s *ch)

   279 {

   280     if (ch->enable) {

   281         ch->enable = 0;

   282         /* Discard any pending request */

   283         ch->pending_request = 0;

   284         omap_dma_deactivate_channel(s, ch);

   285     }

   286 }

   287 

   288 static void omap_dma_channel_end_prog(struct omap_dma_s *s,

   289                 struct omap_dma_channel_s *ch)

   290 {

   291     if (ch->waiting_end_prog) {

   292         ch->waiting_end_prog = 0;

   293         if (!ch->sync || ch->pending_request) {

   294             ch->pending_request = 0;

   295             omap_dma_activate_channel(s, ch);

   296         }

   297     }

   298 }

   299 

   300 static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)

   301 {

   302     struct omap_dma_channel_s *ch = s->ch;

   303 

   304     /* First three interrupts are shared between two channels each. */

   305     if (ch[0].status | ch[6].status)

   306         qemu_irq_raise(ch[0].irq);

   307     if (ch[1].status | ch[7].status)

   308         qemu_irq_raise(ch[1].irq);

   309     if (ch[2].status | ch[8].status)

   310         qemu_irq_raise(ch[2].irq);

   311     if (ch[3].status)

   312         qemu_irq_raise(ch[3].irq);

   313     if (ch[4].status)

   314         qemu_irq_raise(ch[4].irq);

   315     if (ch[5].status)

   316         qemu_irq_raise(ch[5].irq);

   317 }

   318 

   319 static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)

   320 {

   321     struct omap_dma_channel_s *ch = s->ch;

   322     int i;

   323 

   324     for (i = s->chans; i; ch ++, i --)

   325         if (ch->status)

   326             qemu_irq_raise(ch->irq);

   327 }

   328 

   329 static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)

   330 {

   331     s->omap_3_1_mapping_disabled = 0;

   332     s->chans = 9;

   333     s->intr_update = omap_dma_interrupts_3_1_update;

   334 }

   335 

   336 static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)

   337 {

   338     s->omap_3_1_mapping_disabled = 1;

   339     s->chans = 16;

   340     s->intr_update = omap_dma_interrupts_3_2_update;

   341 }

   342 

   343 static void omap_dma_process_request(struct omap_dma_s *s, int request)

   344 {

   345     int channel;

   346     int drop_event = 0;

   347     struct omap_dma_channel_s *ch = s->ch;

   348 

   349     for (channel = 0; channel < s->chans; channel ++, ch ++) {

   350         if (ch->enable && ch->sync == request) {

   351             if (!ch->active)

   352                 omap_dma_activate_channel(s, ch);

   353             else if (!ch->pending_request)

   354                 ch->pending_request = 1;

   355             else {

   356                 /* Request collision */

   357                 /* Second request received while processing other request */

   358                 ch->status |= EVENT_DROP_INTR;

   359                 drop_event = 1;

   360             }

   361         }

   362     }

   363 

   364     if (drop_event)

   365         omap_dma_interrupts_update(s);

   366 }

   367 

   368 static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)

   369 {

   370     uint8_t value[4];

   371     struct omap_dma_channel_s *ch = dma->opaque;

   372     struct omap_dma_reg_set_s *a = &ch->active_set;

   373     int bytes = dma->bytes;

   374 #ifdef MULTI_REQ

   375     uint16_t status = ch->status;

   376 #endif

   377 

   378     do {

   379         /* Transfer a single element */

   380         /* FIXME: check the endianness */

   381         if (!ch->constant_fill)

   382             cpu_physical_memory_read(a->src, value, ch->data_type);

   383         else

   384             *(uint32_t *) value = ch->color;

   385 

   386         if (!ch->transparent_copy || *(uint32_t *) value != ch->color)

   387             cpu_physical_memory_write(a->dest, value, ch->data_type);

   388 

   389         a->src += a->elem_delta[0];

   390         a->dest += a->elem_delta[1];

   391         a->element ++;

   392 

   393 #ifndef MULTI_REQ

   394         if (a->element == a->elements) {

   395             /* End of Frame */

   396             a->element = 0;

   397             a->src += a->frame_delta[0];

   398             a->dest += a->frame_delta[1];

   399             a->frame ++;

   400 

   401             /* If the channel is async, update cpc */

   402             if (!ch->sync)

   403                 ch->cpc = a->dest & 0xffff;

   404         }

   405     } while ((bytes -= ch->data_type));

   406 #else

   407         /* If the channel is element synchronized, deactivate it */

   408         if (ch->sync && !ch->fs && !ch->bs)

   409             omap_dma_deactivate_channel(s, ch);

   410 

   411         /* If it is the last frame, set the LAST_FRAME interrupt */

   412         if (a->element == 1 && a->frame == a->frames - 1)

   413             if (ch->interrupts & LAST_FRAME_INTR)

   414                 ch->status |= LAST_FRAME_INTR;

   415 

   416         /* If the half of the frame was reached, set the HALF_FRAME

   417            interrupt */

   418         if (a->element == (a->elements >> 1))

   419             if (ch->interrupts & HALF_FRAME_INTR)

   420                 ch->status |= HALF_FRAME_INTR;

   421 

   422         if (ch->fs && ch->bs) {

   423             a->pck_element ++;

   424             /* Check if a full packet has beed transferred.  */

   425             if (a->pck_element == a->pck_elements) {

   426                 a->pck_element = 0;

   427 

   428                 /* Set the END_PKT interrupt */

   429                 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)

   430                     ch->status |= END_PKT_INTR;

   431 

   432                 /* If the channel is packet-synchronized, deactivate it */

   433                 if (ch->sync)

   434                     omap_dma_deactivate_channel(s, ch);

   435             }

   436         }

   437 

   438         if (a->element == a->elements) {

   439             /* End of Frame */

   440             a->element = 0;

   441             a->src += a->frame_delta[0];

   442             a->dest += a->frame_delta[1];

   443             a->frame ++;

   444 

   445             /* If the channel is frame synchronized, deactivate it */

   446             if (ch->sync && ch->fs && !ch->bs)

   447                 omap_dma_deactivate_channel(s, ch);

   448 

   449             /* If the channel is async, update cpc */

   450             if (!ch->sync)

   451                 ch->cpc = a->dest & 0xffff;

   452 

   453             /* Set the END_FRAME interrupt */

   454             if (ch->interrupts & END_FRAME_INTR)

   455                 ch->status |= END_FRAME_INTR;

   456 

   457             if (a->frame == a->frames) {

   458                 /* End of Block */

   459                 /* Disable the channel */

   460 

   461                 if (ch->omap_3_1_compatible_disable) {

   462                     omap_dma_disable_channel(s, ch);

   463                     if (ch->link_enabled)

   464                         omap_dma_enable_channel(s,

   465                                         &s->ch[ch->link_next_ch]);

   466                 } else {

   467                     if (!ch->auto_init)

   468                         omap_dma_disable_channel(s, ch);

   469                     else if (ch->repeat || ch->end_prog)

   470                         omap_dma_channel_load(ch);

   471                     else {

   472                         ch->waiting_end_prog = 1;

   473                         omap_dma_deactivate_channel(s, ch);

   474                     }

   475                 }

   476 

   477                 if (ch->interrupts & END_BLOCK_INTR)

   478                     ch->status |= END_BLOCK_INTR;

   479             }

   480         }

   481     } while (status == ch->status && ch->active);

   482 

   483     omap_dma_interrupts_update(s);

   484 #endif

   485 }

   486 

   487 enum {

   488     omap_dma_intr_element_sync,

   489     omap_dma_intr_last_frame,

   490     omap_dma_intr_half_frame,

   491     omap_dma_intr_frame,

   492     omap_dma_intr_frame_sync,

   493     omap_dma_intr_packet,

   494     omap_dma_intr_packet_sync,

   495     omap_dma_intr_block,

   496     __omap_dma_intr_last,

   497 };

   498 

   499 static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)

   500 {

   501     struct omap_dma_port_if_s *src_p, *dest_p;

   502     struct omap_dma_reg_set_s *a;

   503     struct omap_dma_channel_s *ch = dma->opaque;

   504     struct omap_dma_s *s = dma->dma->opaque;

   505     int frames, min_elems, elements[__omap_dma_intr_last];

   506 

   507     a = &ch->active_set;

   508 

   509     src_p = &s->mpu->port[ch->port[0]];

   510     dest_p = &s->mpu->port[ch->port[1]];

   511     if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||

   512                     (!dest_p->addr_valid(s->mpu, a->dest))) {

   513 #if 0

   514         /* Bus time-out */

   515         if (ch->interrupts & TIMEOUT_INTR)

   516             ch->status |= TIMEOUT_INTR;

   517         omap_dma_deactivate_channel(s, ch);

   518         continue;

   519 #endif

   520         printf("%s: Bus time-out in DMA%i operation\n",

   521                         __FUNCTION__, dma->num);

   522     }

   523 

   524     min_elems = INT_MAX;

   525 

   526     /* Check all the conditions that terminate the transfer starting

   527      * with those that can occur the soonest.  */

   528 #define INTR_CHECK(cond, id, nelements)	\

   529     if (cond) {			\

   530         elements[id] = nelements;	\

   531         if (elements[id] < min_elems)	\

   532             min_elems = elements[id];	\

   533     } else				\

   534         elements[id] = INT_MAX;

   535 

   536     /* Elements */

   537     INTR_CHECK(

   538                     ch->sync && !ch->fs && !ch->bs,

   539                     omap_dma_intr_element_sync,

   540                     1)

   541 

   542     /* Frames */

   543     /* TODO: for transfers where entire frames can be read and written

   544      * using memcpy() but a->frame_delta is non-zero, try to still do

   545      * transfers using soc_dma but limit min_elems to a->elements - ...

   546      * See also the TODO in omap_dma_channel_load.  */

   547     INTR_CHECK(

   548                     (ch->interrupts & LAST_FRAME_INTR) &&

   549                     ((a->frame < a->frames - 1) || !a->element),

   550                     omap_dma_intr_last_frame,

   551                     (a->frames - a->frame - 2) * a->elements +

   552                     (a->elements - a->element + 1))

   553     INTR_CHECK(

   554                     ch->interrupts & HALF_FRAME_INTR,

   555                     omap_dma_intr_half_frame,

   556                     (a->elements >> 1) +

   557                     (a->element >= (a->elements >> 1) ? a->elements : 0) -

   558                     a->element)

   559     INTR_CHECK(

   560                     ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),

   561                     omap_dma_intr_frame,

   562                     a->elements - a->element)

   563     INTR_CHECK(

   564                     ch->sync && ch->fs && !ch->bs,

   565                     omap_dma_intr_frame_sync,

   566                     a->elements - a->element)

   567 

   568     /* Packets */

   569     INTR_CHECK(

   570                     ch->fs && ch->bs &&

   571                     (ch->interrupts & END_PKT_INTR) && !ch->src_sync,

   572                     omap_dma_intr_packet,

   573                     a->pck_elements - a->pck_element)

   574     INTR_CHECK(

   575                     ch->fs && ch->bs && ch->sync,

   576                     omap_dma_intr_packet_sync,

   577                     a->pck_elements - a->pck_element)

   578 

   579     /* Blocks */

   580     INTR_CHECK(

   581                     1,

   582                     omap_dma_intr_block,

   583                     (a->frames - a->frame - 1) * a->elements +

   584                     (a->elements - a->element))

   585 

   586     dma->bytes = min_elems * ch->data_type;

   587 

   588     /* Set appropriate interrupts and/or deactivate channels */

   589 

   590 #ifdef MULTI_REQ

   591     /* TODO: should all of this only be done if dma->update, and otherwise

   592      * inside omap_dma_transfer_generic below - check what's faster.  */

   593     if (dma->update) {

   594 #endif

   595 

   596     /* If the channel is element synchronized, deactivate it */

   597     if (min_elems == elements[omap_dma_intr_element_sync])

   598         omap_dma_deactivate_channel(s, ch);

   599 

   600     /* If it is the last frame, set the LAST_FRAME interrupt */

   601     if (min_elems == elements[omap_dma_intr_last_frame])

   602         ch->status |= LAST_FRAME_INTR;

   603 

   604     /* If exactly half of the frame was reached, set the HALF_FRAME

   605        interrupt */

   606     if (min_elems == elements[omap_dma_intr_half_frame])

   607         ch->status |= HALF_FRAME_INTR;

   608 

   609     /* If a full packet has been transferred, set the END_PKT interrupt */

   610     if (min_elems == elements[omap_dma_intr_packet])

   611         ch->status |= END_PKT_INTR;

   612 

   613     /* If the channel is packet-synchronized, deactivate it */

   614     if (min_elems == elements[omap_dma_intr_packet_sync])

   615         omap_dma_deactivate_channel(s, ch);

   616 

   617     /* If the channel is frame synchronized, deactivate it */

   618     if (min_elems == elements[omap_dma_intr_frame_sync])

   619         omap_dma_deactivate_channel(s, ch);

   620 

   621     /* Set the END_FRAME interrupt */

   622     if (min_elems == elements[omap_dma_intr_frame])

   623         ch->status |= END_FRAME_INTR;

   624 

   625     if (min_elems == elements[omap_dma_intr_block]) {

   626         /* End of Block */

   627         /* Disable the channel */

   628 

   629         if (ch->omap_3_1_compatible_disable) {

   630             omap_dma_disable_channel(s, ch);

   631             if (ch->link_enabled)

   632                 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);

   633         } else {

   634             if (!ch->auto_init)

   635                 omap_dma_disable_channel(s, ch);

   636             else if (ch->repeat || ch->end_prog)

   637                 omap_dma_channel_load(ch);

   638             else {

   639                 ch->waiting_end_prog = 1;

   640                 omap_dma_deactivate_channel(s, ch);

   641             }

   642         }

   643 

   644         if (ch->interrupts & END_BLOCK_INTR)

   645             ch->status |= END_BLOCK_INTR;

   646     }

   647 

   648     /* Update packet number */

   649     if (ch->fs && ch->bs) {

   650         a->pck_element += min_elems;

   651         a->pck_element %= a->pck_elements;

   652     }

   653 

   654     /* TODO: check if we really need to update anything here or perhaps we

   655      * can skip part of this.  */

   656 #ifndef MULTI_REQ

   657     if (dma->update) {

   658 #endif

   659         a->element += min_elems;

   660 

   661         frames     = a->element / a->elements;

   662         a->element = a->element % a->elements;

   663         a->frame  += frames;

   664         a->src    += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];

   665         a->dest   += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];

   666 

   667         /* If the channel is async, update cpc */

   668         if (!ch->sync && frames)

   669             ch->cpc = a->dest & 0xffff;

   670 

   671         /* TODO: if the destination port is IMIF or EMIFF, set the dirty

   672          * bits on it.  */

   673     }

   674 

   675     omap_dma_interrupts_update(s);

   676 }

   677 

   678 void omap_dma_reset(struct soc_dma_s *dma)

   679 {

   680     int i;

   681     struct omap_dma_s *s = dma->opaque;

   682 

   683     soc_dma_reset(s->dma);

   684     if (s->model < omap_dma_4)

   685         s->gcr = 0x0004;

   686     else

   687         s->gcr = 0x00010010;

   688     s->ocp = 0x00000000;

   689     memset(&s->irqstat, 0, sizeof(s->irqstat));

   690     memset(&s->irqen, 0, sizeof(s->irqen));

   691     s->lcd_ch.src = emiff;

   692     s->lcd_ch.condition = 0;

   693     s->lcd_ch.interrupts = 0;

   694     s->lcd_ch.dual = 0;

   695     if (s->model < omap_dma_4)

   696         omap_dma_enable_3_1_mapping(s);

   697     for (i = 0; i < s->chans; i ++) {

   698         s->ch[i].suspend = 0;

   699         s->ch[i].prefetch = 0;

   700         s->ch[i].buf_disable = 0;

   701         s->ch[i].src_sync = 0;

   702         memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));

   703         memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));

   704         memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));

   705         memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));

   706         memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));

   707         memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));

   708         memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));

   709         memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));

   710         s->ch[i].write_mode = 0;

   711         s->ch[i].data_type = 0;

   712         s->ch[i].transparent_copy = 0;

   713         s->ch[i].constant_fill = 0;

   714         s->ch[i].color = 0x00000000;

   715         s->ch[i].end_prog = 0;

   716         s->ch[i].repeat = 0;

   717         s->ch[i].auto_init = 0;

   718         s->ch[i].link_enabled = 0;

   719         if (s->model < omap_dma_4)

   720             s->ch[i].interrupts = 0x0003;

   721         else

   722             s->ch[i].interrupts = 0x0000;

   723         s->ch[i].status = 0;

   724         s->ch[i].cstatus = 0;

   725         s->ch[i].active = 0;

   726         s->ch[i].enable = 0;

   727         s->ch[i].sync = 0;

   728         s->ch[i].pending_request = 0;

   729         s->ch[i].waiting_end_prog = 0;

   730         s->ch[i].cpc = 0x0000;

   731         s->ch[i].fs = 0;

   732         s->ch[i].bs = 0;

   733         s->ch[i].omap_3_1_compatible_disable = 0;

   734         memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));

   735         s->ch[i].priority = 0;

   736         s->ch[i].interleave_disabled = 0;

   737         s->ch[i].type = 0;

   738     }

   739 }

   740 

   741 static int omap_dma_ch_reg_read(struct omap_dma_s *s,

   742                 struct omap_dma_channel_s *ch, int reg, uint16_t *value)

   743 {

   744     switch (reg) {

   745     case 0x00:	/* SYS_DMA_CSDP_CH0 */

   746         *value = (ch->burst[1] << 14) |

   747                 (ch->pack[1] << 13) |

   748                 (ch->port[1] << 9) |

   749                 (ch->burst[0] << 7) |

   750                 (ch->pack[0] << 6) |

   751                 (ch->port[0] << 2) |

   752                 (ch->data_type >> 1);

   753         break;

   754 

   755     case 0x02:	/* SYS_DMA_CCR_CH0 */

   756         if (s->model <= omap_dma_3_1)

   757             *value = 0 << 10;			/* FIFO_FLUSH reads as 0 */

   758         else

   759             *value = ch->omap_3_1_compatible_disable << 10;

   760         *value |= (ch->mode[1] << 14) |

   761                 (ch->mode[0] << 12) |

   762                 (ch->end_prog << 11) |

   763                 (ch->repeat << 9) |

   764                 (ch->auto_init << 8) |

   765                 (ch->enable << 7) |

   766                 (ch->priority << 6) |

   767                 (ch->fs << 5) | ch->sync;

   768         break;

   769 

   770     case 0x04:	/* SYS_DMA_CICR_CH0 */

   771         *value = ch->interrupts;

   772         break;

   773 

   774     case 0x06:	/* SYS_DMA_CSR_CH0 */

   775         *value = ch->status;

   776         ch->status &= SYNC;

   777         if (!ch->omap_3_1_compatible_disable && ch->sibling) {

   778             *value |= (ch->sibling->status & 0x3f) << 6;

   779             ch->sibling->status &= SYNC;

   780         }

   781         qemu_irq_lower(ch->irq);

   782         break;

   783 

   784     case 0x08:	/* SYS_DMA_CSSA_L_CH0 */

   785         *value = ch->addr[0] & 0x0000ffff;

   786         break;

   787 

   788     case 0x0a:	/* SYS_DMA_CSSA_U_CH0 */

   789         *value = ch->addr[0] >> 16;

   790         break;

   791 

   792     case 0x0c:	/* SYS_DMA_CDSA_L_CH0 */

   793         *value = ch->addr[1] & 0x0000ffff;

   794         break;

   795 

   796     case 0x0e:	/* SYS_DMA_CDSA_U_CH0 */

   797         *value = ch->addr[1] >> 16;

   798         break;

   799 

   800     case 0x10:	/* SYS_DMA_CEN_CH0 */

   801         *value = ch->elements;

   802         break;

   803 

   804     case 0x12:	/* SYS_DMA_CFN_CH0 */

   805         *value = ch->frames;

   806         break;

   807 

   808     case 0x14:	/* SYS_DMA_CFI_CH0 */

   809         *value = ch->frame_index[0];

   810         break;

   811 

   812     case 0x16:	/* SYS_DMA_CEI_CH0 */

   813         *value = ch->element_index[0];

   814         break;

   815 

   816     case 0x18:	/* SYS_DMA_CPC_CH0 or DMA_CSAC */

   817         if (ch->omap_3_1_compatible_disable)

   818             *value = ch->active_set.src & 0xffff;	/* CSAC */

   819         else

   820             *value = ch->cpc;

   821         break;

   822 

   823     case 0x1a:	/* DMA_CDAC */

   824         *value = ch->active_set.dest & 0xffff;	/* CDAC */

   825         break;

   826 

   827     case 0x1c:	/* DMA_CDEI */

   828         *value = ch->element_index[1];

   829         break;

   830 

   831     case 0x1e:	/* DMA_CDFI */

   832         *value = ch->frame_index[1];

   833         break;

   834 

   835     case 0x20:	/* DMA_COLOR_L */

   836         *value = ch->color & 0xffff;

   837         break;

   838 

   839     case 0x22:	/* DMA_COLOR_U */

   840         *value = ch->color >> 16;

   841         break;

   842 

   843     case 0x24:	/* DMA_CCR2 */

   844         *value = (ch->bs << 2) |

   845                 (ch->transparent_copy << 1) |

   846                 ch->constant_fill;

   847         break;

   848 

   849     case 0x28:	/* DMA_CLNK_CTRL */

   850         *value = (ch->link_enabled << 15) |

   851                 (ch->link_next_ch & 0xf);

   852         break;

   853 

   854     case 0x2a:	/* DMA_LCH_CTRL */

   855         *value = (ch->interleave_disabled << 15) |

   856                 ch->type;

   857         break;

   858 

   859     default:

   860         return 1;

   861     }

   862     return 0;

   863 }

   864 

   865 static int omap_dma_ch_reg_write(struct omap_dma_s *s,

   866                 struct omap_dma_channel_s *ch, int reg, uint16_t value)

   867 {

   868     switch (reg) {

   869     case 0x00:	/* SYS_DMA_CSDP_CH0 */

   870         ch->burst[1] = (value & 0xc000) >> 14;

   871         ch->pack[1] = (value & 0x2000) >> 13;

   872         ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);

   873         ch->burst[0] = (value & 0x0180) >> 7;

   874         ch->pack[0] = (value & 0x0040) >> 6;

   875         ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);

   876         ch->data_type = 1 << (value & 3);

   877         if (ch->port[0] >= __omap_dma_port_last)

   878             printf("%s: invalid DMA port %i\n", __FUNCTION__,

   879                             ch->port[0]);

   880         if (ch->port[1] >= __omap_dma_port_last)

   881             printf("%s: invalid DMA port %i\n", __FUNCTION__,

   882                             ch->port[1]);

   883         if ((value & 3) == 3)

   884             printf("%s: bad data_type for DMA channel\n", __FUNCTION__);

   885         break;

   886 

   887     case 0x02:	/* SYS_DMA_CCR_CH0 */

   888         ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);

   889         ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);

   890         ch->end_prog = (value & 0x0800) >> 11;

   891         if (s->model >= omap_dma_3_2)

   892             ch->omap_3_1_compatible_disable  = (value >> 10) & 0x1;

   893         ch->repeat = (value & 0x0200) >> 9;

   894         ch->auto_init = (value & 0x0100) >> 8;

   895         ch->priority = (value & 0x0040) >> 6;

   896         ch->fs = (value & 0x0020) >> 5;

   897         ch->sync = value & 0x001f;

   898 

   899         if (value & 0x0080)

   900             omap_dma_enable_channel(s, ch);

   901         else

   902             omap_dma_disable_channel(s, ch);

   903 

   904         if (ch->end_prog)

   905             omap_dma_channel_end_prog(s, ch);

   906 

   907         break;

   908 

   909     case 0x04:	/* SYS_DMA_CICR_CH0 */

   910         ch->interrupts = value & 0x3f;

   911         break;

   912 

   913     case 0x06:	/* SYS_DMA_CSR_CH0 */

   914         OMAP_RO_REG((target_phys_addr_t) reg);

   915         break;

   916 

   917     case 0x08:	/* SYS_DMA_CSSA_L_CH0 */

   918         ch->addr[0] &= 0xffff0000;

   919         ch->addr[0] |= value;

   920         break;

   921 

   922     case 0x0a:	/* SYS_DMA_CSSA_U_CH0 */

   923         ch->addr[0] &= 0x0000ffff;

   924         ch->addr[0] |= (uint32_t) value << 16;

   925         break;

   926 

   927     case 0x0c:	/* SYS_DMA_CDSA_L_CH0 */

   928         ch->addr[1] &= 0xffff0000;

   929         ch->addr[1] |= value;

   930         break;

   931 

   932     case 0x0e:	/* SYS_DMA_CDSA_U_CH0 */

   933         ch->addr[1] &= 0x0000ffff;

   934         ch->addr[1] |= (uint32_t) value << 16;

   935         break;

   936 

   937     case 0x10:	/* SYS_DMA_CEN_CH0 */

   938         ch->elements = value;

   939         break;

   940 

   941     case 0x12:	/* SYS_DMA_CFN_CH0 */

   942         ch->frames = value;

   943         break;

   944 

   945     case 0x14:	/* SYS_DMA_CFI_CH0 */

   946         ch->frame_index[0] = (int16_t) value;

   947         break;

   948 

   949     case 0x16:	/* SYS_DMA_CEI_CH0 */

   950         ch->element_index[0] = (int16_t) value;

   951         break;

   952 

   953     case 0x18:	/* SYS_DMA_CPC_CH0 or DMA_CSAC */

   954         OMAP_RO_REG((target_phys_addr_t) reg);

   955         break;

   956 

   957     case 0x1c:	/* DMA_CDEI */

   958         ch->element_index[1] = (int16_t) value;

   959         break;

   960 

   961     case 0x1e:	/* DMA_CDFI */

   962         ch->frame_index[1] = (int16_t) value;

   963         break;

   964 

   965     case 0x20:	/* DMA_COLOR_L */

   966         ch->color &= 0xffff0000;

   967         ch->color |= value;

   968         break;

   969 

   970     case 0x22:	/* DMA_COLOR_U */

   971         ch->color &= 0xffff;

   972         ch->color |= value << 16;

   973         break;

   974 

   975     case 0x24:	/* DMA_CCR2 */

   976         ch->bs = (value >> 2) & 0x1;

   977         ch->transparent_copy = (value >> 1) & 0x1;

   978         ch->constant_fill = value & 0x1;

   979         break;

   980 

   981     case 0x28:	/* DMA_CLNK_CTRL */

   982         ch->link_enabled = (value >> 15) & 0x1;

   983         if (value & (1 << 14)) {			/* Stop_Lnk */

   984             ch->link_enabled = 0;

   985             omap_dma_disable_channel(s, ch);

   986         }

   987         ch->link_next_ch = value & 0x1f;

   988         break;

   989 

   990     case 0x2a:	/* DMA_LCH_CTRL */

   991         ch->interleave_disabled = (value >> 15) & 0x1;

   992         ch->type = value & 0xf;

   993         break;

   994 

   995     default:

   996         return 1;

   997     }

   998     return 0;

   999 }

  1000 

  1001 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,

  1002                 uint16_t value)

  1003 {

  1004     switch (offset) {

  1005     case 0xbc0:	/* DMA_LCD_CSDP */

  1006         s->brust_f2 = (value >> 14) & 0x3;

  1007         s->pack_f2 = (value >> 13) & 0x1;

  1008         s->data_type_f2 = (1 << ((value >> 11) & 0x3));

  1009         s->brust_f1 = (value >> 7) & 0x3;

  1010         s->pack_f1 = (value >> 6) & 0x1;

  1011         s->data_type_f1 = (1 << ((value >> 0) & 0x3));

  1012         break;

  1013 

  1014     case 0xbc2:	/* DMA_LCD_CCR */

  1015         s->mode_f2 = (value >> 14) & 0x3;

  1016         s->mode_f1 = (value >> 12) & 0x3;

  1017         s->end_prog = (value >> 11) & 0x1;

  1018         s->omap_3_1_compatible_disable = (value >> 10) & 0x1;

  1019         s->repeat = (value >> 9) & 0x1;

  1020         s->auto_init = (value >> 8) & 0x1;

  1021         s->running = (value >> 7) & 0x1;

  1022         s->priority = (value >> 6) & 0x1;

  1023         s->bs = (value >> 4) & 0x1;

  1024         break;

  1025 

  1026     case 0xbc4:	/* DMA_LCD_CTRL */

  1027         s->dst = (value >> 8) & 0x1;

  1028         s->src = ((value >> 6) & 0x3) << 1;

  1029         s->condition = 0;

  1030         /* Assume no bus errors and thus no BUS_ERROR irq bits.  */

  1031         s->interrupts = (value >> 1) & 1;

  1032         s->dual = value & 1;

  1033         break;

  1034 

  1035     case 0xbc8:	/* TOP_B1_L */

  1036         s->src_f1_top &= 0xffff0000;

  1037         s->src_f1_top |= 0x0000ffff & value;

  1038         break;

  1039 

  1040     case 0xbca:	/* TOP_B1_U */

  1041         s->src_f1_top &= 0x0000ffff;

  1042         s->src_f1_top |= value << 16;

  1043         break;

  1044 

  1045     case 0xbcc:	/* BOT_B1_L */

  1046         s->src_f1_bottom &= 0xffff0000;

  1047         s->src_f1_bottom |= 0x0000ffff & value;

  1048         break;

  1049 

  1050     case 0xbce:	/* BOT_B1_U */

  1051         s->src_f1_bottom &= 0x0000ffff;

  1052         s->src_f1_bottom |= (uint32_t) value << 16;

  1053         break;

  1054 

  1055     case 0xbd0:	/* TOP_B2_L */

  1056         s->src_f2_top &= 0xffff0000;

  1057         s->src_f2_top |= 0x0000ffff & value;

  1058         break;

  1059 

  1060     case 0xbd2:	/* TOP_B2_U */

  1061         s->src_f2_top &= 0x0000ffff;

  1062         s->src_f2_top |= (uint32_t) value << 16;

  1063         break;

  1064 

  1065     case 0xbd4:	/* BOT_B2_L */

  1066         s->src_f2_bottom &= 0xffff0000;

  1067         s->src_f2_bottom |= 0x0000ffff & value;

  1068         break;

  1069 

  1070     case 0xbd6:	/* BOT_B2_U */

  1071         s->src_f2_bottom &= 0x0000ffff;

  1072         s->src_f2_bottom |= (uint32_t) value << 16;

  1073         break;

  1074 

  1075     case 0xbd8:	/* DMA_LCD_SRC_EI_B1 */

  1076         s->element_index_f1 = value;

  1077         break;

  1078 

  1079     case 0xbda:	/* DMA_LCD_SRC_FI_B1_L */

  1080         s->frame_index_f1 &= 0xffff0000;

  1081         s->frame_index_f1 |= 0x0000ffff & value;

  1082         break;

  1083 

  1084     case 0xbf4:	/* DMA_LCD_SRC_FI_B1_U */

  1085         s->frame_index_f1 &= 0x0000ffff;

  1086         s->frame_index_f1 |= (uint32_t) value << 16;

  1087         break;

  1088 

  1089     case 0xbdc:	/* DMA_LCD_SRC_EI_B2 */

  1090         s->element_index_f2 = value;

  1091         break;

  1092 

  1093     case 0xbde:	/* DMA_LCD_SRC_FI_B2_L */

  1094         s->frame_index_f2 &= 0xffff0000;

  1095         s->frame_index_f2 |= 0x0000ffff & value;

  1096         break;

  1097 

  1098     case 0xbf6:	/* DMA_LCD_SRC_FI_B2_U */

  1099         s->frame_index_f2 &= 0x0000ffff;

  1100         s->frame_index_f2 |= (uint32_t) value << 16;

  1101         break;

  1102 

  1103     case 0xbe0:	/* DMA_LCD_SRC_EN_B1 */

  1104         s->elements_f1 = value;

  1105         break;

  1106 

  1107     case 0xbe4:	/* DMA_LCD_SRC_FN_B1 */

  1108         s->frames_f1 = value;

  1109         break;

  1110 

  1111     case 0xbe2:	/* DMA_LCD_SRC_EN_B2 */

  1112         s->elements_f2 = value;

  1113         break;

  1114 

  1115     case 0xbe6:	/* DMA_LCD_SRC_FN_B2 */

  1116         s->frames_f2 = value;

  1117         break;

  1118 

  1119     case 0xbea:	/* DMA_LCD_LCH_CTRL */

  1120         s->lch_type = value & 0xf;

  1121         break;

  1122 

  1123     default:

  1124         return 1;

  1125     }

  1126     return 0;

  1127 }

  1128 

  1129 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,

  1130                 uint16_t *ret)

  1131 {

  1132     switch (offset) {

  1133     case 0xbc0:	/* DMA_LCD_CSDP */

  1134         *ret = (s->brust_f2 << 14) |

  1135             (s->pack_f2 << 13) |