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1 /* |
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2 * OMAP LCD controller. |
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3 * |
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4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> |
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5 * |
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6 * This program is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU General Public License as |
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8 * published by the Free Software Foundation; either version 2 of |
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9 * the License, or (at your option) any later version. |
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10 * |
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11 * This program is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 * GNU General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU General Public License |
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17 * along with this program; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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19 * MA 02111-1307 USA |
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20 */ |
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21 #include "hw.h" |
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22 #include "gui.h" |
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23 #include "omap.h" |
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24 |
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25 struct omap_lcd_panel_s { |
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26 qemu_irq irq; |
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27 DisplayState *state; |
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28 ram_addr_t imif_base; |
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29 ram_addr_t emiff_base; |
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30 |
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31 int plm; |
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32 int tft; |
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33 int mono; |
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34 int enable; |
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35 int width; |
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36 int height; |
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37 int interrupts; |
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38 uint32_t timing[3]; |
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39 uint32_t subpanel; |
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40 uint32_t ctrl; |
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41 |
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42 struct omap_dma_lcd_channel_s *dma; |
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43 uint16_t palette[256]; |
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44 int palette_done; |
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45 int frame_done; |
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46 int invalidate; |
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47 int sync_error; |
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48 }; |
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49 |
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50 static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) |
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51 { |
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52 if (s->frame_done && (s->interrupts & 1)) { |
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53 qemu_irq_raise(s->irq); |
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54 return; |
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55 } |
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56 |
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57 if (s->palette_done && (s->interrupts & 2)) { |
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58 qemu_irq_raise(s->irq); |
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59 return; |
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60 } |
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61 |
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62 if (s->sync_error) { |
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63 qemu_irq_raise(s->irq); |
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64 return; |
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65 } |
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66 |
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67 qemu_irq_lower(s->irq); |
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68 } |
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69 |
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70 #include "pixel_ops.h" |
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71 |
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72 typedef void draw_line_func( |
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73 uint8_t *d, const uint8_t *s, int width, const uint16_t *pal); |
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74 |
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75 #define DEPTH 8 |
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76 #include "omap_lcd_template.h" |
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77 #define DEPTH 15 |
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78 #include "omap_lcd_template.h" |
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79 #define DEPTH 16 |
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80 #include "omap_lcd_template.h" |
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81 #define DEPTH 32 |
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82 #include "omap_lcd_template.h" |
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83 |
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84 static draw_line_func *draw_line_table2[33] = { |
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85 [0 ... 32] = 0, |
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86 [8] = draw_line2_8, |
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87 [15] = draw_line2_15, |
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88 [16] = draw_line2_16, |
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89 [32] = draw_line2_32, |
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90 }, *draw_line_table4[33] = { |
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91 [0 ... 32] = 0, |
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92 [8] = draw_line4_8, |
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93 [15] = draw_line4_15, |
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94 [16] = draw_line4_16, |
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95 [32] = draw_line4_32, |
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96 }, *draw_line_table8[33] = { |
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97 [0 ... 32] = 0, |
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98 [8] = draw_line8_8, |
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99 [15] = draw_line8_15, |
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100 [16] = draw_line8_16, |
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101 [32] = draw_line8_32, |
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102 }, *draw_line_table12[33] = { |
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103 [0 ... 32] = 0, |
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104 [8] = draw_line12_8, |
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105 [15] = draw_line12_15, |
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106 [16] = draw_line12_16, |
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107 [32] = draw_line12_32, |
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108 }, *draw_line_table16[33] = { |
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109 [0 ... 32] = 0, |
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110 [8] = draw_line16_8, |
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111 [15] = draw_line16_15, |
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112 [16] = draw_line16_16, |
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113 [32] = draw_line16_32, |
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114 }; |
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115 |
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116 static void omap_update_display(void *opaque) |
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117 { |
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118 struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; |
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119 draw_line_func *draw_line; |
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120 int size, dirty[2], minline, maxline, height; |
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121 int line, width, linesize, step, bpp, frame_offset; |
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122 ram_addr_t frame_base, scanline, newline, x; |
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123 uint8_t *s, *d; |
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124 |
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125 if (!omap_lcd || omap_lcd->plm == 1 || |
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126 !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state)) |
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127 return; |
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128 |
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129 frame_offset = 0; |
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130 if (omap_lcd->plm != 2) { |
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131 /* FIXME: This is broken if it spans multiple RAM regions. */ |
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132 memcpy(omap_lcd->palette, |
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133 host_ram_addr(omap_lcd->dma->phys_framebuffer[ |
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134 omap_lcd->dma->current_frame]), 0x200); |
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135 switch (omap_lcd->palette[0] >> 12 & 7) { |
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136 case 3 ... 7: |
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137 frame_offset += 0x200; |
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138 break; |
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139 default: |
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140 frame_offset += 0x20; |
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141 } |
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142 } |
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143 |
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144 /* Colour depth */ |
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145 switch ((omap_lcd->palette[0] >> 12) & 7) { |
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146 case 1: |
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147 draw_line = draw_line_table2[ds_get_bits_per_pixel(omap_lcd->state)]; |
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148 bpp = 2; |
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149 break; |
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150 |
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151 case 2: |
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152 draw_line = draw_line_table4[ds_get_bits_per_pixel(omap_lcd->state)]; |
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153 bpp = 4; |
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154 break; |
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155 |
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156 case 3: |
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157 draw_line = draw_line_table8[ds_get_bits_per_pixel(omap_lcd->state)]; |
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158 bpp = 8; |
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159 break; |
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160 |
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161 case 4 ... 7: |
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162 if (!omap_lcd->tft) |
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163 draw_line = draw_line_table12[ds_get_bits_per_pixel(omap_lcd->state)]; |
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164 else |
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165 draw_line = draw_line_table16[ds_get_bits_per_pixel(omap_lcd->state)]; |
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166 bpp = 16; |
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167 break; |
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168 |
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169 default: |
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170 /* Unsupported at the moment. */ |
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171 return; |
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172 } |
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173 |
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174 /* Resolution */ |
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175 width = omap_lcd->width; |
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176 if (width != ds_get_width(omap_lcd->state) || |
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177 omap_lcd->height != ds_get_height(omap_lcd->state)) { |
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178 gui_resize_vt(omap_lcd->state, |
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179 omap_lcd->width, omap_lcd->height); |
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180 omap_lcd->invalidate = 1; |
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181 } |
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182 |
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183 if (omap_lcd->dma->current_frame == 0) |
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184 size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top; |
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185 else |
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186 size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top; |
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187 |
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188 if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) { |
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189 omap_lcd->sync_error = 1; |
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190 omap_lcd_interrupts(omap_lcd); |
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191 omap_lcd->enable = 0; |
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192 return; |
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193 } |
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194 |
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195 /* Content */ |
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196 frame_base = omap_lcd->dma->phys_framebuffer[ |
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197 omap_lcd->dma->current_frame] + frame_offset; |
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198 omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame; |
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199 if (omap_lcd->dma->interrupts & 1) |
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200 qemu_irq_raise(omap_lcd->dma->irq); |
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201 if (omap_lcd->dma->dual) |
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202 omap_lcd->dma->current_frame ^= 1; |
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203 |
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204 if (!ds_get_bits_per_pixel(omap_lcd->state)) |
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205 return; |
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206 |
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207 line = 0; |
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208 height = omap_lcd->height; |
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209 if (omap_lcd->subpanel & (1 << 31)) { |
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210 if (omap_lcd->subpanel & (1 << 29)) |
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211 line = (omap_lcd->subpanel >> 16) & 0x3ff; |
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212 else |
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213 height = (omap_lcd->subpanel >> 16) & 0x3ff; |
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214 /* TODO: fill the rest of the panel with DPD */ |
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215 } |
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216 step = width * bpp >> 3; |
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217 scanline = frame_base + step * line; |
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218 /* FIXME: This is broken if it spans multiple RAM regions. */ |
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219 s = host_ram_addr(scanline); |
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220 d = ds_get_data(omap_lcd->state); |
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221 linesize = ds_get_linesize(omap_lcd->state); |
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222 |
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223 dirty[0] = dirty[1] = |
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224 cpu_physical_memory_get_dirty(scanline, VGA_DIRTY_FLAG); |
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225 minline = height; |
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226 maxline = line; |
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227 for (; line < height; line ++) { |
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228 newline = scanline + step; |
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229 for (x = scanline + TARGET_PAGE_SIZE; x < newline; |
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230 x += TARGET_PAGE_SIZE) { |
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231 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG); |
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232 dirty[0] |= dirty[1]; |
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233 } |
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234 if (dirty[0] || omap_lcd->invalidate) { |
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235 draw_line(d, s, width, omap_lcd->palette); |
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236 if (line < minline) |
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237 minline = line; |
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238 maxline = line + 1; |
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239 } |
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240 scanline = newline; |
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241 dirty[0] = dirty[1]; |
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242 s += step; |
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243 d += linesize; |
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244 } |
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245 |
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246 if (maxline >= minline) { |
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247 dpy_update(omap_lcd->state, 0, minline, width, maxline); |
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248 cpu_physical_memory_reset_dirty(frame_base + step * minline, |
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249 frame_base + step * maxline, VGA_DIRTY_FLAG); |
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250 } |
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251 } |
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252 |
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253 static int ppm_save(const char *filename, uint8_t *data, |
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254 int w, int h, int linesize) |
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255 { |
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256 FILE *f; |
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257 uint8_t *d, *d1; |
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258 unsigned int v; |
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259 int y, x, bpp; |
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260 |
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261 f = fopen(filename, "wb"); |
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262 if (!f) |
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263 return -1; |
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264 fprintf(f, "P6\n%d %d\n%d\n", w, h, 255); |
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265 d1 = data; |
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266 bpp = linesize / w; |
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267 for (y = 0; y < h; y ++) { |
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268 d = d1; |
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269 for (x = 0; x < w; x ++) { |
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270 v = *(uint32_t *) d; |
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271 switch (bpp) { |
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272 case 2: |
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273 fputc((v >> 8) & 0xf8, f); |
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274 fputc((v >> 3) & 0xfc, f); |
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275 fputc((v << 3) & 0xf8, f); |
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276 break; |
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277 case 3: |
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278 case 4: |
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279 default: |
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280 fputc((v >> 16) & 0xff, f); |
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281 fputc((v >> 8) & 0xff, f); |
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282 fputc((v) & 0xff, f); |
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283 break; |
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284 } |
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285 d += bpp; |
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286 } |
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287 d1 += linesize; |
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288 } |
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289 fclose(f); |
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290 return 0; |
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291 } |
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292 |
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293 static void omap_screen_dump(void *opaque, const char *filename) { |
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294 struct omap_lcd_panel_s *omap_lcd = opaque; |
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295 omap_update_display(opaque); |
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296 if (omap_lcd && ds_get_data(omap_lcd->state)) |
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297 ppm_save(filename, ds_get_data(omap_lcd->state), |
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298 omap_lcd->width, omap_lcd->height, |
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299 ds_get_linesize(omap_lcd->state)); |
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300 } |
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301 |
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302 static void omap_invalidate_display(void *opaque) { |
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303 struct omap_lcd_panel_s *omap_lcd = opaque; |
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304 omap_lcd->invalidate = 1; |
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305 } |
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306 |
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307 static void omap_lcd_update(struct omap_lcd_panel_s *s) { |
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308 if (!s->enable) { |
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309 s->dma->current_frame = -1; |
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310 s->sync_error = 0; |
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311 if (s->plm != 1) |
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312 s->frame_done = 1; |
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313 omap_lcd_interrupts(s); |
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314 return; |
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315 } |
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316 |
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317 if (s->dma->current_frame == -1) { |
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318 s->frame_done = 0; |
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319 s->palette_done = 0; |
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320 s->dma->current_frame = 0; |
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321 } |
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322 |
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323 if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu, |
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324 s->dma->src_f1_top) || |
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325 !s->dma->mpu->port[ |
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326 s->dma->src].addr_valid(s->dma->mpu, |
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327 s->dma->src_f1_bottom) || |
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328 (s->dma->dual && |
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329 (!s->dma->mpu->port[ |
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330 s->dma->src].addr_valid(s->dma->mpu, |
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331 s->dma->src_f2_top) || |
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332 !s->dma->mpu->port[ |
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333 s->dma->src].addr_valid(s->dma->mpu, |
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334 s->dma->src_f2_bottom)))) { |
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335 s->dma->condition |= 1 << 2; |
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336 if (s->dma->interrupts & (1 << 1)) |
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337 qemu_irq_raise(s->dma->irq); |
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338 s->enable = 0; |
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339 return; |
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340 } |
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341 |
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342 if (s->dma->src == imif) { |
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343 /* Framebuffers are in SRAM */ |
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344 s->dma->phys_framebuffer[0] = s->imif_base + |
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345 s->dma->src_f1_top - OMAP_IMIF_BASE; |
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346 |
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347 s->dma->phys_framebuffer[1] = s->imif_base + |
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348 s->dma->src_f2_top - OMAP_IMIF_BASE; |
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349 } else { |
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350 /* Framebuffers are in RAM */ |
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351 s->dma->phys_framebuffer[0] = s->emiff_base + |
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352 s->dma->src_f1_top - OMAP_EMIFF_BASE; |
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353 |
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354 s->dma->phys_framebuffer[1] = s->emiff_base + |
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355 s->dma->src_f2_top - OMAP_EMIFF_BASE; |
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356 } |
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357 |
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358 if (s->plm != 2 && !s->palette_done) { |
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359 /* FIXME: This is broken if it spans multiple RAM regions. */ |
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360 memcpy(s->palette, host_ram_addr( |
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361 s->dma->phys_framebuffer[s->dma->current_frame]), 0x200); |
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362 s->palette_done = 1; |
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363 omap_lcd_interrupts(s); |
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364 } |
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365 } |
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366 |
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367 static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr) |
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368 { |
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369 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; |
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370 |
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371 switch (addr) { |
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372 case 0x00: /* LCD_CONTROL */ |
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373 return (s->tft << 23) | (s->plm << 20) | |
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374 (s->tft << 7) | (s->interrupts << 3) | |
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375 (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34; |
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376 |
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377 case 0x04: /* LCD_TIMING0 */ |
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378 return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f; |
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379 |
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380 case 0x08: /* LCD_TIMING1 */ |
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381 return (s->timing[1] << 10) | (s->height - 1); |
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382 |
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383 case 0x0c: /* LCD_TIMING2 */ |
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384 return s->timing[2] | 0xfc000000; |
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385 |
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386 case 0x10: /* LCD_STATUS */ |
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387 return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done; |
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388 |
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389 case 0x14: /* LCD_SUBPANEL */ |
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390 return s->subpanel; |
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391 |
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392 default: |
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393 break; |
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394 } |
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395 OMAP_BAD_REG(addr); |
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396 return 0; |
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397 } |
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398 |
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399 static void omap_lcdc_write(void *opaque, target_phys_addr_t addr, |
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400 uint32_t value) |
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401 { |
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402 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; |
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403 |
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404 switch (addr) { |
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405 case 0x00: /* LCD_CONTROL */ |
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406 s->plm = (value >> 20) & 3; |
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407 s->tft = (value >> 7) & 1; |
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408 s->interrupts = (value >> 3) & 3; |
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409 s->mono = (value >> 1) & 1; |
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410 s->ctrl = value & 0x01cff300; |
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411 if (s->enable != (value & 1)) { |
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412 s->enable = value & 1; |
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413 omap_lcd_update(s); |
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414 } |
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415 break; |
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416 |
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417 case 0x04: /* LCD_TIMING0 */ |
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418 s->timing[0] = value >> 10; |
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419 s->width = (value & 0x3ff) + 1; |
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420 break; |
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421 |
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422 case 0x08: /* LCD_TIMING1 */ |
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423 s->timing[1] = value >> 10; |
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424 s->height = (value & 0x3ff) + 1; |
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425 break; |
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426 |
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427 case 0x0c: /* LCD_TIMING2 */ |
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428 s->timing[2] = value; |
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429 break; |
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430 |
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431 case 0x10: /* LCD_STATUS */ |
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432 break; |
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433 |
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434 case 0x14: /* LCD_SUBPANEL */ |
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435 s->subpanel = value & 0xa1ffffff; |
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436 break; |
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437 |
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438 default: |
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439 OMAP_BAD_REG(addr); |
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440 } |
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441 } |
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442 |
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443 static CPUReadMemoryFunc *omap_lcdc_readfn[] = { |
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444 omap_lcdc_read, |
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445 omap_lcdc_read, |
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446 omap_lcdc_read, |
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447 }; |
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448 |
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449 static CPUWriteMemoryFunc *omap_lcdc_writefn[] = { |
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450 omap_lcdc_write, |
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451 omap_lcdc_write, |
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452 omap_lcdc_write, |
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453 }; |
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454 |
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455 void omap_lcdc_reset(struct omap_lcd_panel_s *s) |
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456 { |
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457 s->dma->current_frame = -1; |
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458 s->plm = 0; |
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459 s->tft = 0; |
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460 s->mono = 0; |
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461 s->enable = 0; |
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462 s->width = 0; |
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463 s->height = 0; |
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464 s->interrupts = 0; |
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465 s->timing[0] = 0; |
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466 s->timing[1] = 0; |
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467 s->timing[2] = 0; |
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468 s->subpanel = 0; |
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469 s->palette_done = 0; |
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470 s->frame_done = 0; |
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471 s->sync_error = 0; |
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472 s->invalidate = 1; |
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473 s->subpanel = 0; |
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474 s->ctrl = 0; |
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475 } |
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476 |
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477 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq, |
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478 struct omap_dma_lcd_channel_s *dma, DisplayState *ds, |
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479 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk) |
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480 { |
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481 int iomemtype; |
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482 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) |
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483 qemu_mallocz(sizeof(struct omap_lcd_panel_s)); |
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484 |
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485 s->irq = irq; |
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486 s->dma = dma; |
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487 s->imif_base = imif_base; |
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488 s->emiff_base = emiff_base; |
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489 omap_lcdc_reset(s); |
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490 |
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491 iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn, |
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492 omap_lcdc_writefn, s); |
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493 cpu_register_physical_memory(base, 0x100, iomemtype); |
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494 |
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495 s->state = gui_get_graphic_console(NULL, |
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496 omap_update_display, |
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497 omap_invalidate_display, |
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498 omap_screen_dump, s); |
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499 |
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500 return s; |
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501 } |