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1 #ifndef QEMU_PCI_H |
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2 #define QEMU_PCI_H |
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3 |
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4 /* PCI includes legacy ISA access. */ |
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5 #include "isa.h" |
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6 |
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7 /* PCI bus */ |
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8 |
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9 extern target_phys_addr_t pci_mem_base; |
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10 |
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11 /* see pci-ids.txt */ |
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12 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
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13 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
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14 #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
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15 |
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16 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
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17 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
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18 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
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19 |
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20 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
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21 uint32_t address, uint32_t data, int len); |
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22 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, |
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23 uint32_t address, int len); |
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24 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
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25 uint32_t addr, uint32_t size, int type); |
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26 |
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27 #define PCI_ADDRESS_SPACE_MEM 0x00 |
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28 #define PCI_ADDRESS_SPACE_IO 0x01 |
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29 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 |
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30 |
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31 typedef struct PCIIORegion { |
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32 uint32_t addr; /* current PCI mapping address. -1 means not mapped */ |
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33 uint32_t size; |
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34 uint8_t type; |
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35 PCIMapIORegionFunc *map_func; |
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36 } PCIIORegion; |
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37 |
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38 #define PCI_ROM_SLOT 6 |
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39 #define PCI_NUM_REGIONS 7 |
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40 |
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41 #define PCI_DEVICES_MAX 64 |
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42 |
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43 #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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44 #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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45 #define PCI_COMMAND 0x04 /* 16 bits */ |
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46 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
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47 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
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48 #define PCI_REVISION 0x08 |
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49 #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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50 #define PCI_SUBVENDOR_ID 0x2c /* 16 bits */ |
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51 #define PCI_SUBDEVICE_ID 0x2e /* 16 bits */ |
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52 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
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53 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
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54 #define PCI_MIN_GNT 0x3e /* 8 bits */ |
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55 #define PCI_MAX_LAT 0x3f /* 8 bits */ |
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56 |
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57 /* Bits in the PCI Status Register (PCI 2.3 spec) */ |
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58 #define PCI_STATUS_RESERVED1 0x007 |
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59 #define PCI_STATUS_INT_STATUS 0x008 |
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60 #define PCI_STATUS_CAPABILITIES 0x010 |
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61 #define PCI_STATUS_66MHZ 0x020 |
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62 #define PCI_STATUS_RESERVED2 0x040 |
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63 #define PCI_STATUS_FAST_BACK 0x080 |
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64 #define PCI_STATUS_DEVSEL 0x600 |
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65 |
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66 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ |
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67 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ |
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68 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) |
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69 |
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70 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) |
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71 |
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72 /* Bits in the PCI Command Register (PCI 2.3 spec) */ |
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73 #define PCI_COMMAND_RESERVED 0xf800 |
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74 |
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75 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) |
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76 |
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77 struct PCIDevice { |
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78 /* PCI config space */ |
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79 uint8_t config[256]; |
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80 |
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81 /* the following fields are read only */ |
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82 PCIBus *bus; |
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83 int devfn; |
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84 char name[64]; |
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85 PCIIORegion io_regions[PCI_NUM_REGIONS]; |
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86 |
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87 /* do not access the following fields */ |
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88 PCIConfigReadFunc *config_read; |
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89 PCIConfigWriteFunc *config_write; |
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90 /* ??? This is a PC-specific hack, and should be removed. */ |
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91 int irq_index; |
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92 |
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93 /* IRQ objects for the INTA-INTD pins. */ |
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94 qemu_irq *irq; |
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95 |
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96 /* Current IRQ levels. Used internally by the generic PCI code. */ |
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97 int irq_state[4]; |
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98 }; |
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99 |
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100 PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
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101 int instance_size, int devfn, |
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102 PCIConfigReadFunc *config_read, |
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103 PCIConfigWriteFunc *config_write); |
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104 |
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105 void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
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106 uint32_t size, int type, |
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107 PCIMapIORegionFunc *map_func); |
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108 |
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109 uint32_t pci_default_read_config(PCIDevice *d, |
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110 uint32_t address, int len); |
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111 void pci_default_write_config(PCIDevice *d, |
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112 uint32_t address, uint32_t val, int len); |
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113 void pci_device_save(PCIDevice *s, QEMUFile *f); |
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114 int pci_device_load(PCIDevice *s, QEMUFile *f); |
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115 |
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116 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); |
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117 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
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118 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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119 qemu_irq *pic, int devfn_min, int nirq); |
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120 |
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121 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn); |
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122 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
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123 uint32_t pci_data_read(void *opaque, uint32_t addr, int len); |
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124 int pci_bus_num(PCIBus *s); |
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125 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
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126 |
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127 void pci_info(void); |
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128 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id, |
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129 pci_map_irq_fn map_irq, const char *name); |
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130 |
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131 /* lsi53c895a.c */ |
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132 #define LSI_MAX_DEVS 7 |
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133 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
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134 void *lsi_scsi_init(PCIBus *bus, int devfn); |
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135 |
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136 /* vmware_vga.c */ |
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137 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, |
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138 unsigned long vga_ram_offset, int vga_ram_size); |
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139 |
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140 /* usb-uhci.c */ |
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141 void usb_uhci_piix3_init(PCIBus *bus, int devfn); |
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142 void usb_uhci_piix4_init(PCIBus *bus, int devfn); |
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143 |
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144 /* usb-ohci.c */ |
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145 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn); |
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146 |
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147 /* eepro100.c */ |
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148 |
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149 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); |
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150 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); |
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151 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); |
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152 |
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153 /* ne2000.c */ |
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154 |
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155 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
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156 |
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157 /* rtl8139.c */ |
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158 |
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159 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
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160 |
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161 /* e1000.c */ |
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162 void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn); |
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163 |
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164 /* pcnet.c */ |
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165 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
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166 |
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167 /* prep_pci.c */ |
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168 PCIBus *pci_prep_init(qemu_irq *pic); |
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169 |
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170 /* apb_pci.c */ |
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171 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, |
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172 qemu_irq *pic); |
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173 |
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174 /* sh_pci.c */ |
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175 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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176 qemu_irq *pic, int devfn_min, int nirq); |
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177 |
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178 #endif |