1 /*

     2  * QEMU Common PCI Host bridge configuration data space access routines.

     3  *

     4  * Copyright (c) 2006 Fabrice Bellard

     5  *

     6  * Permission is hereby granted, free of charge, to any person obtaining a copy

     7  * of this software and associated documentation files (the "Software"), to deal

     8  * in the Software without restriction, including without limitation the rights

     9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    10  * copies of the Software, and to permit persons to whom the Software is

    11  * furnished to do so, subject to the following conditions:

    12  *

    13  * The above copyright notice and this permission notice shall be included in

    14  * all copies or substantial portions of the Software.

    15  *

    16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    22  * THE SOFTWARE.

    23  */

    24 

    25 /* Worker routines for a PCI host controller that uses an {address,data}

    26    register pair to access PCI configuration space.  */

    27 

    28 typedef struct {

    29     uint32_t config_reg;

    30     PCIBus *bus;

    31 } PCIHostState;

    32 

    33 static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val)

    34 {

    35     PCIHostState *s = opaque;

    36     if (s->config_reg & (1u << 31))

    37         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);

    38 }

    39 

    40 static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val)

    41 {

    42     PCIHostState *s = opaque;

    43 #ifdef TARGET_WORDS_BIGENDIAN

    44     val = bswap16(val);

    45 #endif

    46     if (s->config_reg & (1u << 31))

    47         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);

    48 }

    49 

    50 static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val)

    51 {

    52     PCIHostState *s = opaque;

    53 #ifdef TARGET_WORDS_BIGENDIAN

    54     val = bswap32(val);

    55 #endif

    56     if (s->config_reg & (1u << 31))

    57         pci_data_write(s->bus, s->config_reg, val, 4);

    58 }

    59 

    60 static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr)

    61 {

    62     PCIHostState *s = opaque;

    63     if (!(s->config_reg & (1 << 31)))

    64         return 0xff;

    65     return pci_data_read(s->bus, s->config_reg | (addr & 3), 1);

    66 }

    67 

    68 static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr)

    69 {

    70     PCIHostState *s = opaque;

    71     uint32_t val;

    72     if (!(s->config_reg & (1 << 31)))

    73         return 0xffff;

    74     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);

    75 #ifdef TARGET_WORDS_BIGENDIAN

    76     val = bswap16(val);

    77 #endif

    78     return val;

    79 }

    80 

    81 static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr)

    82 {

    83     PCIHostState *s = opaque;

    84     uint32_t val;

    85     if (!(s->config_reg & (1 << 31)))

    86         return 0xffffffff;

    87     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);

    88 #ifdef TARGET_WORDS_BIGENDIAN

    89     val = bswap32(val);

    90 #endif

    91     return val;

    92 }