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1 /* |
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2 * QEMU PPC PREP hardware System Emulator |
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3 * |
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4 * Copyright (c) 2003-2007 Jocelyn Mayer |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "nvram.h" |
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26 #include "pc.h" |
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27 #include "fdc.h" |
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28 #include "net.h" |
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29 #include "sysemu.h" |
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30 #include "isa.h" |
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31 #include "pci.h" |
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32 #include "ppc.h" |
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33 #include "boards.h" |
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34 #include "qemu-log.h" |
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35 |
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36 //#define HARD_DEBUG_PPC_IO |
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37 //#define DEBUG_PPC_IO |
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38 |
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39 /* SMP is not enabled, for now */ |
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40 #define MAX_CPUS 1 |
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41 |
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42 #define MAX_IDE_BUS 2 |
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43 |
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44 #define BIOS_FILENAME "ppc_rom.bin" |
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45 #define KERNEL_LOAD_ADDR 0x01000000 |
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46 #define INITRD_LOAD_ADDR 0x01800000 |
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47 |
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48 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) |
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49 #define DEBUG_PPC_IO |
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50 #endif |
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51 |
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52 #if defined (HARD_DEBUG_PPC_IO) |
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53 #define PPC_IO_DPRINTF(fmt, args...) \ |
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54 do { \ |
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55 if (loglevel & CPU_LOG_IOPORT) { \ |
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56 fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
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57 } else { \ |
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58 printf("%s : " fmt, __func__ , ##args); \ |
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59 } \ |
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60 } while (0) |
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61 #elif defined (DEBUG_PPC_IO) |
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62 #define PPC_IO_DPRINTF(fmt, args...) \ |
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63 do { \ |
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64 if (loglevel & CPU_LOG_IOPORT) { \ |
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65 fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
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66 } \ |
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67 } while (0) |
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68 #else |
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69 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0) |
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70 #endif |
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71 |
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72 /* Constants for devices init */ |
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73 static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
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74 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
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75 static const int ide_irq[2] = { 13, 13 }; |
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76 |
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77 #define NE2000_NB_MAX 6 |
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78 |
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79 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
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80 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
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81 |
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82 //static PITState *pit; |
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83 |
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84 /* ISA IO ports bridge */ |
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85 #define PPC_IO_BASE 0x80000000 |
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86 |
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87 #if 0 |
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88 /* Speaker port 0x61 */ |
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89 static int speaker_data_on; |
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90 static int dummy_refresh_clock; |
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91 #endif |
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92 |
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93 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
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94 { |
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95 #if 0 |
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96 speaker_data_on = (val >> 1) & 1; |
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97 pit_set_gate(pit, 2, val & 1); |
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98 #endif |
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99 } |
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100 |
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101 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
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102 { |
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103 #if 0 |
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104 int out; |
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105 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); |
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106 dummy_refresh_clock ^= 1; |
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107 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | |
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108 (dummy_refresh_clock << 4); |
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109 #endif |
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110 return 0; |
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111 } |
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112 |
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113 /* PCI intack register */ |
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114 /* Read-only register (?) */ |
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115 static void _PPC_intack_write (void *opaque, |
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116 target_phys_addr_t addr, uint32_t value) |
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117 { |
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118 // printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
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119 } |
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120 |
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121 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr) |
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122 { |
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123 uint32_t retval = 0; |
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124 |
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125 if ((addr & 0xf) == 0) |
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126 retval = pic_intack_read(isa_pic); |
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127 // printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
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128 |
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129 return retval; |
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130 } |
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131 |
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132 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
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133 { |
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134 return _PPC_intack_read(addr); |
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135 } |
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136 |
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137 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
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138 { |
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139 #ifdef TARGET_WORDS_BIGENDIAN |
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140 return bswap16(_PPC_intack_read(addr)); |
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141 #else |
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142 return _PPC_intack_read(addr); |
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143 #endif |
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144 } |
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145 |
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146 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
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147 { |
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148 #ifdef TARGET_WORDS_BIGENDIAN |
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149 return bswap32(_PPC_intack_read(addr)); |
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150 #else |
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151 return _PPC_intack_read(addr); |
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152 #endif |
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153 } |
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154 |
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155 static CPUWriteMemoryFunc *PPC_intack_write[] = { |
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156 &_PPC_intack_write, |
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157 &_PPC_intack_write, |
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158 &_PPC_intack_write, |
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159 }; |
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160 |
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161 static CPUReadMemoryFunc *PPC_intack_read[] = { |
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162 &PPC_intack_readb, |
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163 &PPC_intack_readw, |
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164 &PPC_intack_readl, |
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165 }; |
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166 |
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167 /* PowerPC control and status registers */ |
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168 #if 0 // Not used |
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169 static struct { |
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170 /* IDs */ |
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171 uint32_t veni_devi; |
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172 uint32_t revi; |
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173 /* Control and status */ |
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174 uint32_t gcsr; |
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175 uint32_t xcfr; |
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176 uint32_t ct32; |
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177 uint32_t mcsr; |
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178 /* General purpose registers */ |
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179 uint32_t gprg[6]; |
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180 /* Exceptions */ |
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181 uint32_t feen; |
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182 uint32_t fest; |
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183 uint32_t fema; |
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184 uint32_t fecl; |
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185 uint32_t eeen; |
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186 uint32_t eest; |
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187 uint32_t eecl; |
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188 uint32_t eeint; |
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189 uint32_t eemck0; |
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190 uint32_t eemck1; |
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191 /* Error diagnostic */ |
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192 } XCSR; |
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193 |
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194 static void PPC_XCSR_writeb (void *opaque, |
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195 target_phys_addr_t addr, uint32_t value) |
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196 { |
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197 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
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198 } |
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199 |
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200 static void PPC_XCSR_writew (void *opaque, |
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201 target_phys_addr_t addr, uint32_t value) |
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202 { |
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203 #ifdef TARGET_WORDS_BIGENDIAN |
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204 value = bswap16(value); |
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205 #endif |
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206 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
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207 } |
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208 |
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209 static void PPC_XCSR_writel (void *opaque, |
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210 target_phys_addr_t addr, uint32_t value) |
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211 { |
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212 #ifdef TARGET_WORDS_BIGENDIAN |
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213 value = bswap32(value); |
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214 #endif |
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215 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
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216 } |
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217 |
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218 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
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219 { |
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220 uint32_t retval = 0; |
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221 |
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222 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
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223 |
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224 return retval; |
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225 } |
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226 |
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227 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
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228 { |
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229 uint32_t retval = 0; |
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230 |
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231 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
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232 #ifdef TARGET_WORDS_BIGENDIAN |
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233 retval = bswap16(retval); |
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234 #endif |
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235 |
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236 return retval; |
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237 } |
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238 |
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239 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
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240 { |
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241 uint32_t retval = 0; |
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242 |
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243 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
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244 #ifdef TARGET_WORDS_BIGENDIAN |
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245 retval = bswap32(retval); |
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246 #endif |
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247 |
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248 return retval; |
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249 } |
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250 |
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251 static CPUWriteMemoryFunc *PPC_XCSR_write[] = { |
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252 &PPC_XCSR_writeb, |
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253 &PPC_XCSR_writew, |
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254 &PPC_XCSR_writel, |
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255 }; |
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256 |
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257 static CPUReadMemoryFunc *PPC_XCSR_read[] = { |
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258 &PPC_XCSR_readb, |
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259 &PPC_XCSR_readw, |
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260 &PPC_XCSR_readl, |
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261 }; |
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262 #endif |
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263 |
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264 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
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265 typedef struct sysctrl_t { |
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266 qemu_irq reset_irq; |
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267 m48t59_t *nvram; |
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268 uint8_t state; |
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269 uint8_t syscontrol; |
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270 uint8_t fake_io[2]; |
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271 int contiguous_map; |
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272 int endian; |
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273 } sysctrl_t; |
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274 |
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275 enum { |
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276 STATE_HARDFILE = 0x01, |
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277 }; |
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278 |
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279 static sysctrl_t *sysctrl; |
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280 |
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281 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
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282 { |
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283 sysctrl_t *sysctrl = opaque; |
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284 |
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285 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
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286 val); |
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287 sysctrl->fake_io[addr - 0x0398] = val; |
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288 } |
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289 |
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290 static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
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291 { |
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292 sysctrl_t *sysctrl = opaque; |
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293 |
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294 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
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295 sysctrl->fake_io[addr - 0x0398]); |
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296 return sysctrl->fake_io[addr - 0x0398]; |
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297 } |
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298 |
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299 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
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300 { |
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301 sysctrl_t *sysctrl = opaque; |
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302 |
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303 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
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304 addr - PPC_IO_BASE, val); |
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305 switch (addr) { |
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306 case 0x0092: |
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307 /* Special port 92 */ |
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308 /* Check soft reset asked */ |
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309 if (val & 0x01) { |
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310 qemu_irq_raise(sysctrl->reset_irq); |
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311 } else { |
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312 qemu_irq_lower(sysctrl->reset_irq); |
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313 } |
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314 /* Check LE mode */ |
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315 if (val & 0x02) { |
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316 sysctrl->endian = 1; |
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317 } else { |
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318 sysctrl->endian = 0; |
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319 } |
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320 break; |
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321 case 0x0800: |
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322 /* Motorola CPU configuration register : read-only */ |
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323 break; |
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324 case 0x0802: |
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325 /* Motorola base module feature register : read-only */ |
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326 break; |
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327 case 0x0803: |
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328 /* Motorola base module status register : read-only */ |
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329 break; |
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330 case 0x0808: |
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331 /* Hardfile light register */ |
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332 if (val & 1) |
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333 sysctrl->state |= STATE_HARDFILE; |
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334 else |
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335 sysctrl->state &= ~STATE_HARDFILE; |
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336 break; |
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337 case 0x0810: |
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338 /* Password protect 1 register */ |
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339 if (sysctrl->nvram != NULL) |
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340 m48t59_toggle_lock(sysctrl->nvram, 1); |
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341 break; |
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342 case 0x0812: |
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343 /* Password protect 2 register */ |
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344 if (sysctrl->nvram != NULL) |
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345 m48t59_toggle_lock(sysctrl->nvram, 2); |
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346 break; |
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347 case 0x0814: |
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348 /* L2 invalidate register */ |
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349 // tlb_flush(first_cpu, 1); |
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350 break; |
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351 case 0x081C: |
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352 /* system control register */ |
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353 sysctrl->syscontrol = val & 0x0F; |
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354 break; |
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355 case 0x0850: |
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356 /* I/O map type register */ |
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357 sysctrl->contiguous_map = val & 0x01; |
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358 break; |
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359 default: |
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360 printf("ERROR: unaffected IO port write: %04" PRIx32 |
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361 " => %02" PRIx32"\n", addr, val); |
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362 break; |
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363 } |
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364 } |
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365 |
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366 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
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367 { |
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368 sysctrl_t *sysctrl = opaque; |
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369 uint32_t retval = 0xFF; |
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370 |
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371 switch (addr) { |
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372 case 0x0092: |
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373 /* Special port 92 */ |
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374 retval = 0x00; |
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375 break; |
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376 case 0x0800: |
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377 /* Motorola CPU configuration register */ |
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378 retval = 0xEF; /* MPC750 */ |
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379 break; |
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380 case 0x0802: |
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381 /* Motorola Base module feature register */ |
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382 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
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383 break; |
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384 case 0x0803: |
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385 /* Motorola base module status register */ |
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386 retval = 0xE0; /* Standard MPC750 */ |
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387 break; |
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388 case 0x080C: |
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389 /* Equipment present register: |
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390 * no L2 cache |
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391 * no upgrade processor |
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392 * no cards in PCI slots |
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393 * SCSI fuse is bad |
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394 */ |
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395 retval = 0x3C; |
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396 break; |
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397 case 0x0810: |
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398 /* Motorola base module extended feature register */ |
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399 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
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400 break; |
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401 case 0x0814: |
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402 /* L2 invalidate: don't care */ |
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403 break; |
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404 case 0x0818: |
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405 /* Keylock */ |
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406 retval = 0x00; |
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407 break; |
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408 case 0x081C: |
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409 /* system control register |
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410 * 7 - 6 / 1 - 0: L2 cache enable |
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411 */ |
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412 retval = sysctrl->syscontrol; |
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413 break; |
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414 case 0x0823: |
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415 /* */ |
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416 retval = 0x03; /* no L2 cache */ |
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417 break; |
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418 case 0x0850: |
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419 /* I/O map type register */ |
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420 retval = sysctrl->contiguous_map; |
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421 break; |
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422 default: |
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423 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
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424 break; |
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425 } |
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426 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
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427 addr - PPC_IO_BASE, retval); |
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428 |
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429 return retval; |
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430 } |
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431 |
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432 static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl, |
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433 target_phys_addr_t |
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434 addr) |
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435 { |
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436 if (sysctrl->contiguous_map == 0) { |
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437 /* 64 KB contiguous space for IOs */ |
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438 addr &= 0xFFFF; |
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439 } else { |
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440 /* 8 MB non-contiguous space for IOs */ |
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441 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
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442 } |
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443 |
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444 return addr; |
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445 } |
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446 |
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447 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
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448 uint32_t value) |
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449 { |
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450 sysctrl_t *sysctrl = opaque; |
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451 |
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452 addr = prep_IO_address(sysctrl, addr); |
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453 cpu_outb(NULL, addr, value); |
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454 } |
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455 |
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456 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
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457 { |
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458 sysctrl_t *sysctrl = opaque; |
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459 uint32_t ret; |
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460 |
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461 addr = prep_IO_address(sysctrl, addr); |
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462 ret = cpu_inb(NULL, addr); |
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463 |
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464 return ret; |
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465 } |
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466 |
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467 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
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468 uint32_t value) |
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469 { |
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470 sysctrl_t *sysctrl = opaque; |
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471 |
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472 addr = prep_IO_address(sysctrl, addr); |
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473 #ifdef TARGET_WORDS_BIGENDIAN |
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474 value = bswap16(value); |
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475 #endif |
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476 PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value); |
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477 cpu_outw(NULL, addr, value); |
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478 } |
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479 |
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480 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
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481 { |
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482 sysctrl_t *sysctrl = opaque; |
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483 uint32_t ret; |
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484 |
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485 addr = prep_IO_address(sysctrl, addr); |
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486 ret = cpu_inw(NULL, addr); |
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487 #ifdef TARGET_WORDS_BIGENDIAN |
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488 ret = bswap16(ret); |
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489 #endif |
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490 PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret); |
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491 |
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492 return ret; |
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493 } |
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494 |
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495 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
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496 uint32_t value) |
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497 { |
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498 sysctrl_t *sysctrl = opaque; |
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499 |
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500 addr = prep_IO_address(sysctrl, addr); |
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501 #ifdef TARGET_WORDS_BIGENDIAN |
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502 value = bswap32(value); |
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503 #endif |
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504 PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value); |
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505 cpu_outl(NULL, addr, value); |
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506 } |
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507 |
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508 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
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509 { |
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510 sysctrl_t *sysctrl = opaque; |
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511 uint32_t ret; |
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512 |
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513 addr = prep_IO_address(sysctrl, addr); |
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514 ret = cpu_inl(NULL, addr); |
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515 #ifdef TARGET_WORDS_BIGENDIAN |
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516 ret = bswap32(ret); |
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517 #endif |
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518 PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret); |
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519 |
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520 return ret; |
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521 } |
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522 |
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523 static CPUWriteMemoryFunc *PPC_prep_io_write[] = { |
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524 &PPC_prep_io_writeb, |
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525 &PPC_prep_io_writew, |
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526 &PPC_prep_io_writel, |
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527 }; |
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528 |
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529 static CPUReadMemoryFunc *PPC_prep_io_read[] = { |
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530 &PPC_prep_io_readb, |
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531 &PPC_prep_io_readw, |
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532 &PPC_prep_io_readl, |
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533 }; |
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534 |
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535 #define NVRAM_SIZE 0x2000 |
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536 |
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537 /* PowerPC PREP hardware initialisation */ |
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538 static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size, |
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539 const char *boot_device, DisplayState *ds, |
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540 const char *kernel_filename, |
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541 const char *kernel_cmdline, |
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542 const char *initrd_filename, |
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543 const char *cpu_model) |
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544 { |
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545 CPUState *env = NULL, *envs[MAX_CPUS]; |
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546 char buf[1024]; |
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547 nvram_t nvram; |
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548 m48t59_t *m48t59; |
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549 int PPC_io_memory; |
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550 int linux_boot, i, nb_nics1, bios_size; |
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551 unsigned long bios_offset; |
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552 uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
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553 PCIBus *pci_bus; |
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554 qemu_irq *i8259; |
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555 int ppc_boot_device; |
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556 int index; |
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557 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
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558 BlockDriverState *fd[MAX_FD]; |
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559 |
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560 sysctrl = qemu_mallocz(sizeof(sysctrl_t)); |
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561 if (sysctrl == NULL) |
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562 return; |
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563 |
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564 linux_boot = (kernel_filename != NULL); |
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565 |
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566 /* init CPUs */ |
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567 if (cpu_model == NULL) |
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568 cpu_model = "default"; |
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569 for (i = 0; i < smp_cpus; i++) { |
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570 env = cpu_init(cpu_model); |
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571 if (!env) { |
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572 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
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573 exit(1); |
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574 } |
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575 if (env->flags & POWERPC_FLAG_RTC_CLK) { |
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576 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ |
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577 cpu_ppc_tb_init(env, 7812500UL); |
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578 } else { |
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579 /* Set time-base frequency to 100 Mhz */ |
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580 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
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581 } |
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582 qemu_register_reset(&cpu_ppc_reset, env); |
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583 envs[i] = env; |
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584 } |
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585 |
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586 /* allocate RAM */ |
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587 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
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588 |
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589 /* allocate and load BIOS */ |
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590 bios_offset = ram_size + vga_ram_size; |
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591 if (bios_name == NULL) |
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592 bios_name = BIOS_FILENAME; |
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593 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
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594 bios_size = load_image(buf, phys_ram_base + bios_offset); |
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595 if (bios_size < 0 || bios_size > BIOS_SIZE) { |
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596 cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf); |
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597 exit(1); |
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598 } |
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599 if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
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600 cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n"); |
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601 } |
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602 bios_size = (bios_size + 0xfff) & ~0xfff; |
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603 cpu_register_physical_memory((uint32_t)(-bios_size), |
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604 bios_size, bios_offset | IO_MEM_ROM); |
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605 |
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606 if (linux_boot) { |
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607 kernel_base = KERNEL_LOAD_ADDR; |
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608 /* now we can load the kernel */ |
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609 kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
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610 if (kernel_size < 0) { |
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611 cpu_abort(env, "qemu: could not load kernel '%s'\n", |
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612 kernel_filename); |
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613 exit(1); |
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614 } |
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615 /* load initrd */ |
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616 if (initrd_filename) { |
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617 initrd_base = INITRD_LOAD_ADDR; |
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618 initrd_size = load_image(initrd_filename, |
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619 phys_ram_base + initrd_base); |
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620 if (initrd_size < 0) { |
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621 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n", |
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622 initrd_filename); |
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623 exit(1); |
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624 } |
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625 } else { |
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626 initrd_base = 0; |
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627 initrd_size = 0; |
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628 } |
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629 ppc_boot_device = 'm'; |
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630 } else { |
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631 kernel_base = 0; |
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632 kernel_size = 0; |
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633 initrd_base = 0; |
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634 initrd_size = 0; |
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635 ppc_boot_device = '\0'; |
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636 /* For now, OHW cannot boot from the network. */ |
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637 for (i = 0; boot_device[i] != '\0'; i++) { |
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638 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
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639 ppc_boot_device = boot_device[i]; |
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640 break; |
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641 } |
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642 } |
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643 if (ppc_boot_device == '\0') { |
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644 fprintf(stderr, "No valid boot device for Mac99 machine\n"); |
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645 exit(1); |
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646 } |
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647 } |
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648 |
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649 isa_mem_base = 0xc0000000; |
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650 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
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651 cpu_abort(env, "Only 6xx bus is supported on PREP machine\n"); |
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652 exit(1); |
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653 } |
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654 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
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655 pci_bus = pci_prep_init(i8259); |
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656 // pci_bus = i440fx_init(); |
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657 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ |
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658 PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read, |
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659 PPC_prep_io_write, sysctrl); |
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660 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
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661 |
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662 /* init basic PC hardware */ |
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663 pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
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664 vga_ram_size, 0, 0); |
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665 // openpic = openpic_init(0x00000000, 0xF0000000, 1); |
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666 // pit = pit_init(0x40, i8259[0]); |
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667 rtc_init(0x70, i8259[8]); |
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668 |
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669 serial_init(0x3f8, i8259[4], 115200, serial_hds[0]); |
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670 nb_nics1 = nb_nics; |
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671 if (nb_nics1 > NE2000_NB_MAX) |
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672 nb_nics1 = NE2000_NB_MAX; |
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673 for(i = 0; i < nb_nics1; i++) { |
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674 if (nd_table[i].model == NULL |
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675 || strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
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676 isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); |
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677 } else { |
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678 pci_nic_init(pci_bus, &nd_table[i], -1); |
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679 } |
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680 } |
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681 |
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682 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
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683 fprintf(stderr, "qemu: too many IDE bus\n"); |
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684 exit(1); |
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685 } |
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686 |
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687 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
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688 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
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689 if (index != -1) |
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690 hd[i] = drives_table[index].bdrv; |
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691 else |
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692 hd[i] = NULL; |
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693 } |
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694 |
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695 for(i = 0; i < MAX_IDE_BUS; i++) { |
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696 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
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697 hd[2 * i], |
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698 hd[2 * i + 1]); |
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699 } |
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700 i8042_init(i8259[1], i8259[12], 0x60); |
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701 DMA_init(1); |
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702 // AUD_init(); |
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703 // SB16_init(); |
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704 |
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705 for(i = 0; i < MAX_FD; i++) { |
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706 index = drive_get_index(IF_FLOPPY, 0, i); |
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707 if (index != -1) |
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708 fd[i] = drives_table[index].bdrv; |
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709 else |
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710 fd[i] = NULL; |
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711 } |
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712 fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); |
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713 |
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714 /* Register speaker port */ |
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715 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
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716 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
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717 /* Register fake IO ports for PREP */ |
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718 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
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719 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
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720 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
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721 /* System control ports */ |
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722 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
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723 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
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724 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
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725 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
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726 /* PCI intack location */ |
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727 PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read, |
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728 PPC_intack_write, NULL); |
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729 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
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730 /* PowerPC control and status register group */ |
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731 #if 0 |
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732 PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, |
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733 NULL); |
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734 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
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735 #endif |
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736 |
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737 if (usb_enabled) { |
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738 usb_ohci_init_pci(pci_bus, 3, -1); |
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739 } |
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740 |
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741 m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
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742 if (m48t59 == NULL) |
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743 return; |
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744 sysctrl->nvram = m48t59; |
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745 |
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746 /* Initialise NVRAM */ |
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747 nvram.opaque = m48t59; |
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748 nvram.read_fn = &m48t59_read; |
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749 nvram.write_fn = &m48t59_write; |
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750 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, |
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751 kernel_base, kernel_size, |
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752 kernel_cmdline, |
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753 initrd_base, initrd_size, |
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754 /* XXX: need an option to load a NVRAM image */ |
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755 0, |
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756 graphic_width, graphic_height, graphic_depth); |
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757 |
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758 /* Special port to get debug messages from Open-Firmware */ |
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759 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
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760 } |
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761 |
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762 QEMUMachine prep_machine = { |
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763 .name = "prep", |
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764 .desc = "PowerPC PREP platform", |
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765 .init = ppc_prep_init, |
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766 .ram_require = BIOS_SIZE + VGA_RAM_SIZE, |
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767 .max_cpus = MAX_CPUS, |
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768 }; |