1 /*

     2  * Intel XScale PXA255/270 processor support.

     3  *

     4  * Copyright (c) 2006 Openedhand Ltd.

     5  * Written by Andrzej Zaborowski <balrog@zabor.org>

     6  *

     7  * This code is licenced under the GPL.

     8  */

     9 

    10 #include "hw.h"

    11 #include "pxa.h"

    12 #include "sysemu.h"

    13 #include "pc.h"

    14 #include "i2c.h"

    15 #include "qemu-timer.h"

    16 #include "qemu-char.h"

    17 

    18 static struct {

    19     target_phys_addr_t io_base;

    20     int irqn;

    21 } pxa255_serial[] = {

    22     { 0x40100000, PXA2XX_PIC_FFUART },

    23     { 0x40200000, PXA2XX_PIC_BTUART },

    24     { 0x40700000, PXA2XX_PIC_STUART },

    25     { 0x41600000, PXA25X_PIC_HWUART },

    26     { 0, 0 }

    27 }, pxa270_serial[] = {

    28     { 0x40100000, PXA2XX_PIC_FFUART },

    29     { 0x40200000, PXA2XX_PIC_BTUART },

    30     { 0x40700000, PXA2XX_PIC_STUART },

    31     { 0, 0 }

    32 };

    33 

    34 typedef struct PXASSPDef {

    35     target_phys_addr_t io_base;

    36     int irqn;

    37 } PXASSPDef;

    38 

    39 #if 0

    40 static PXASSPDef pxa250_ssp[] = {

    41     { 0x41000000, PXA2XX_PIC_SSP },

    42     { 0, 0 }

    43 };

    44 #endif

    45 

    46 static PXASSPDef pxa255_ssp[] = {

    47     { 0x41000000, PXA2XX_PIC_SSP },

    48     { 0x41400000, PXA25X_PIC_NSSP },

    49     { 0, 0 }

    50 };

    51 

    52 #if 0

    53 static PXASSPDef pxa26x_ssp[] = {

    54     { 0x41000000, PXA2XX_PIC_SSP },

    55     { 0x41400000, PXA25X_PIC_NSSP },

    56     { 0x41500000, PXA26X_PIC_ASSP },

    57     { 0, 0 }

    58 };

    59 #endif

    60 

    61 static PXASSPDef pxa27x_ssp[] = {

    62     { 0x41000000, PXA2XX_PIC_SSP },

    63     { 0x41700000, PXA27X_PIC_SSP2 },

    64     { 0x41900000, PXA2XX_PIC_SSP3 },

    65     { 0, 0 }

    66 };

    67 

    68 #define PMCR	0x00	/* Power Manager Control register */

    69 #define PSSR	0x04	/* Power Manager Sleep Status register */

    70 #define PSPR	0x08	/* Power Manager Scratch-Pad register */

    71 #define PWER	0x0c	/* Power Manager Wake-Up Enable register */

    72 #define PRER	0x10	/* Power Manager Rising-Edge Detect Enable register */

    73 #define PFER	0x14	/* Power Manager Falling-Edge Detect Enable register */

    74 #define PEDR	0x18	/* Power Manager Edge-Detect Status register */

    75 #define PCFR	0x1c	/* Power Manager General Configuration register */

    76 #define PGSR0	0x20	/* Power Manager GPIO Sleep-State register 0 */

    77 #define PGSR1	0x24	/* Power Manager GPIO Sleep-State register 1 */

    78 #define PGSR2	0x28	/* Power Manager GPIO Sleep-State register 2 */

    79 #define PGSR3	0x2c	/* Power Manager GPIO Sleep-State register 3 */

    80 #define RCSR	0x30	/* Reset Controller Status register */

    81 #define PSLR	0x34	/* Power Manager Sleep Configuration register */

    82 #define PTSR	0x38	/* Power Manager Standby Configuration register */

    83 #define PVCR	0x40	/* Power Manager Voltage Change Control register */

    84 #define PUCR	0x4c	/* Power Manager USIM Card Control/Status register */

    85 #define PKWR	0x50	/* Power Manager Keyboard Wake-Up Enable register */

    86 #define PKSR	0x54	/* Power Manager Keyboard Level-Detect Status */

    87 #define PCMD0	0x80	/* Power Manager I2C Command register File 0 */

    88 #define PCMD31	0xfc	/* Power Manager I2C Command register File 31 */

    89 

    90 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)

    91 {

    92     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

    93 

    94     switch (addr) {

    95     case PMCR ... PCMD31:

    96         if (addr & 3)

    97             goto fail;

    98 

    99         return s->pm_regs[addr >> 2];

   100     default:

   101     fail:

   102         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   103         break;

   104     }

   105     return 0;

   106 }

   107 

   108 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,

   109                 uint32_t value)

   110 {

   111     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   112 

   113     switch (addr) {

   114     case PMCR:

   115         s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);

   116         s->pm_regs[addr >> 2] |= value & 0x15;

   117         break;

   118 

   119     case PSSR:	/* Read-clean registers */

   120     case RCSR:

   121     case PKSR:

   122         s->pm_regs[addr >> 2] &= ~value;

   123         break;

   124 

   125     default:	/* Read-write registers */

   126         if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {

   127             s->pm_regs[addr >> 2] = value;

   128             break;

   129         }

   130 

   131         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   132         break;

   133     }

   134 }

   135 

   136 static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {

   137     pxa2xx_pm_read,

   138     pxa2xx_pm_read,

   139     pxa2xx_pm_read,

   140 };

   141 

   142 static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {

   143     pxa2xx_pm_write,

   144     pxa2xx_pm_write,

   145     pxa2xx_pm_write,

   146 };

   147 

   148 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)

   149 {

   150     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   151     int i;

   152 

   153     for (i = 0; i < 0x40; i ++)

   154         qemu_put_be32s(f, &s->pm_regs[i]);

   155 }

   156 

   157 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)

   158 {

   159     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   160     int i;

   161 

   162     for (i = 0; i < 0x40; i ++)

   163         qemu_get_be32s(f, &s->pm_regs[i]);

   164 

   165     return 0;

   166 }

   167 

   168 #define CCCR	0x00	/* Core Clock Configuration register */

   169 #define CKEN	0x04	/* Clock Enable register */

   170 #define OSCC	0x08	/* Oscillator Configuration register */

   171 #define CCSR	0x0c	/* Core Clock Status register */

   172 

   173 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)

   174 {

   175     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   176 

   177     switch (addr) {

   178     case CCCR:

   179     case CKEN:

   180     case OSCC:

   181         return s->cm_regs[addr >> 2];

   182 

   183     case CCSR:

   184         return s->cm_regs[CCCR >> 2] | (3 << 28);

   185 

   186     default:

   187         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   188         break;

   189     }

   190     return 0;

   191 }

   192 

   193 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,

   194                 uint32_t value)

   195 {

   196     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   197 

   198     switch (addr) {

   199     case CCCR:

   200     case CKEN:

   201         s->cm_regs[addr >> 2] = value;

   202         break;

   203 

   204     case OSCC:

   205         s->cm_regs[addr >> 2] &= ~0x6c;

   206         s->cm_regs[addr >> 2] |= value & 0x6e;

   207         if ((value >> 1) & 1)			/* OON */

   208             s->cm_regs[addr >> 2] |= 1 << 0;	/* Oscillator is now stable */

   209         break;

   210 

   211     default:

   212         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   213         break;

   214     }

   215 }

   216 

   217 static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {

   218     pxa2xx_cm_read,

   219     pxa2xx_cm_read,

   220     pxa2xx_cm_read,

   221 };

   222 

   223 static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {

   224     pxa2xx_cm_write,

   225     pxa2xx_cm_write,

   226     pxa2xx_cm_write,

   227 };

   228 

   229 static void pxa2xx_cm_save(QEMUFile *f, void *opaque)

   230 {

   231     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   232     int i;

   233 

   234     for (i = 0; i < 4; i ++)

   235         qemu_put_be32s(f, &s->cm_regs[i]);

   236     qemu_put_be32s(f, &s->clkcfg);

   237     qemu_put_be32s(f, &s->pmnc);

   238 }

   239 

   240 static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)

   241 {

   242     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   243     int i;

   244 

   245     for (i = 0; i < 4; i ++)

   246         qemu_get_be32s(f, &s->cm_regs[i]);

   247     qemu_get_be32s(f, &s->clkcfg);

   248     qemu_get_be32s(f, &s->pmnc);

   249 

   250     return 0;

   251 }

   252 

   253 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)

   254 {

   255     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   256 

   257     switch (reg) {

   258     case 6:	/* Clock Configuration register */

   259         return s->clkcfg;

   260 

   261     case 7:	/* Power Mode register */

   262         return 0;

   263 

   264     default:

   265         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

   266         break;

   267     }

   268     return 0;

   269 }

   270 

   271 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,

   272                 uint32_t value)

   273 {

   274     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   275     static const char *pwrmode[8] = {

   276         "Normal", "Idle", "Deep-idle", "Standby",

   277         "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",

   278     };

   279 

   280     switch (reg) {

   281     case 6:	/* Clock Configuration register */

   282         s->clkcfg = value & 0xf;

   283         if (value & 2)

   284             printf("%s: CPU frequency change attempt\n", __FUNCTION__);

   285         break;

   286 

   287     case 7:	/* Power Mode register */

   288         if (value & 8)

   289             printf("%s: CPU voltage change attempt\n", __FUNCTION__);

   290         switch (value & 7) {

   291         case 0:

   292             /* Do nothing */

   293             break;

   294 

   295         case 1:

   296             /* Idle */

   297             if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) {	/* CPDIS */

   298                 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);

   299                 break;

   300             }

   301             /* Fall through.  */

   302 

   303         case 2:

   304             /* Deep-Idle */

   305             cpu_interrupt(s->env, CPU_INTERRUPT_HALT);

   306             s->pm_regs[RCSR >> 2] |= 0x8;	/* Set GPR */

   307             goto message;

   308 

   309         case 3:

   310             s->env->uncached_cpsr =

   311                     ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;

   312             s->env->cp15.c1_sys = 0;

   313             s->env->cp15.c1_coproc = 0;

   314             s->env->cp15.c2_base0 = 0;

   315             s->env->cp15.c3 = 0;

   316             s->pm_regs[PSSR >> 2] |= 0x8;	/* Set STS */

   317             s->pm_regs[RCSR >> 2] |= 0x8;	/* Set GPR */

   318 

   319             /*

   320              * The scratch-pad register is almost universally used

   321              * for storing the return address on suspend.  For the

   322              * lack of a resuming bootloader, perform a jump

   323              * directly to that address.

   324              */

   325             memset(s->env->regs, 0, 4 * 15);

   326             s->env->regs[15] = s->pm_regs[PSPR >> 2];

   327 

   328 #if 0

   329             buffer = 0xe59ff000;	/* ldr     pc, [pc, #0] */

   330             cpu_physical_memory_write(0, &buffer, 4);

   331             buffer = s->pm_regs[PSPR >> 2];

   332             cpu_physical_memory_write(8, &buffer, 4);

   333 #endif

   334 

   335             /* Suspend */

   336             cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);

   337 

   338             goto message;

   339 

   340         default:

   341         message:

   342             printf("%s: machine entered %s mode\n", __FUNCTION__,

   343                             pwrmode[value & 7]);

   344         }

   345         break;

   346 

   347     default:

   348         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

   349         break;

   350     }

   351 }

   352 

   353 /* Performace Monitoring Registers */

   354 #define CPPMNC		0	/* Performance Monitor Control register */

   355 #define CPCCNT		1	/* Clock Counter register */

   356 #define CPINTEN		4	/* Interrupt Enable register */

   357 #define CPFLAG		5	/* Overflow Flag register */

   358 #define CPEVTSEL	8	/* Event Selection register */

   359 

   360 #define CPPMN0		0	/* Performance Count register 0 */

   361 #define CPPMN1		1	/* Performance Count register 1 */

   362 #define CPPMN2		2	/* Performance Count register 2 */

   363 #define CPPMN3		3	/* Performance Count register 3 */

   364 

   365 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)

   366 {

   367     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   368 

   369     switch (reg) {

   370     case CPPMNC:

   371         return s->pmnc;

   372     case CPCCNT:

   373         if (s->pmnc & 1)

   374             return qemu_get_clock(vm_clock);

   375         else

   376             return 0;

   377     case CPINTEN:

   378     case CPFLAG:

   379     case CPEVTSEL:

   380         return 0;

   381 

   382     default:

   383         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

   384         break;

   385     }

   386     return 0;

   387 }

   388 

   389 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,

   390                 uint32_t value)

   391 {

   392     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   393 

   394     switch (reg) {

   395     case CPPMNC:

   396         s->pmnc = value;

   397         break;

   398 

   399     case CPCCNT:

   400     case CPINTEN:

   401     case CPFLAG:

   402     case CPEVTSEL:

   403         break;

   404 

   405     default:

   406         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

   407         break;

   408     }

   409 }

   410 

   411 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)

   412 {

   413     switch (crm) {

   414     case 0:

   415         return pxa2xx_clkpwr_read(opaque, op2, reg, crm);

   416     case 1:

   417         return pxa2xx_perf_read(opaque, op2, reg, crm);

   418     case 2:

   419         switch (reg) {

   420         case CPPMN0:

   421         case CPPMN1:

   422         case CPPMN2:

   423         case CPPMN3:

   424             return 0;

   425         }

   426         /* Fall through */

   427     default:

   428         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

   429         break;

   430     }

   431     return 0;

   432 }

   433 

   434 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,

   435                 uint32_t value)

   436 {

   437     switch (crm) {

   438     case 0:

   439         pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);

   440         break;

   441     case 1:

   442         pxa2xx_perf_write(opaque, op2, reg, crm, value);

   443         break;

   444     case 2:

   445         switch (reg) {

   446         case CPPMN0:

   447         case CPPMN1:

   448         case CPPMN2:

   449         case CPPMN3:

   450             return;

   451         }

   452         /* Fall through */

   453     default:

   454         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

   455         break;

   456     }

   457 }

   458 

   459 #define MDCNFG		0x00	/* SDRAM Configuration register */

   460 #define MDREFR		0x04	/* SDRAM Refresh Control register */

   461 #define MSC0		0x08	/* Static Memory Control register 0 */

   462 #define MSC1		0x0c	/* Static Memory Control register 1 */

   463 #define MSC2		0x10	/* Static Memory Control register 2 */

   464 #define MECR		0x14	/* Expansion Memory Bus Config register */

   465 #define SXCNFG		0x1c	/* Synchronous Static Memory Config register */

   466 #define MCMEM0		0x28	/* PC Card Memory Socket 0 Timing register */

   467 #define MCMEM1		0x2c	/* PC Card Memory Socket 1 Timing register */

   468 #define MCATT0		0x30	/* PC Card Attribute Socket 0 register */

   469 #define MCATT1		0x34	/* PC Card Attribute Socket 1 register */

   470 #define MCIO0		0x38	/* PC Card I/O Socket 0 Timing register */

   471 #define MCIO1		0x3c	/* PC Card I/O Socket 1 Timing register */

   472 #define MDMRS		0x40	/* SDRAM Mode Register Set Config register */

   473 #define BOOT_DEF	0x44	/* Boot-time Default Configuration register */

   474 #define ARB_CNTL	0x48	/* Arbiter Control register */

   475 #define BSCNTR0		0x4c	/* Memory Buffer Strength Control register 0 */

   476 #define BSCNTR1		0x50	/* Memory Buffer Strength Control register 1 */

   477 #define LCDBSCNTR	0x54	/* LCD Buffer Strength Control register */

   478 #define MDMRSLP		0x58	/* Low Power SDRAM Mode Set Config register */

   479 #define BSCNTR2		0x5c	/* Memory Buffer Strength Control register 2 */

   480 #define BSCNTR3		0x60	/* Memory Buffer Strength Control register 3 */

   481 #define SA1110		0x64	/* SA-1110 Memory Compatibility register */

   482 

   483 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)

   484 {

   485     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   486 

   487     switch (addr) {

   488     case MDCNFG ... SA1110:

   489         if ((addr & 3) == 0)

   490             return s->mm_regs[addr >> 2];

   491 

   492     default:

   493         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   494         break;

   495     }

   496     return 0;

   497 }

   498 

   499 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,

   500                 uint32_t value)

   501 {

   502     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   503 

   504     switch (addr) {

   505     case MDCNFG ... SA1110:

   506         if ((addr & 3) == 0) {

   507             s->mm_regs[addr >> 2] = value;

   508             break;

   509         }

   510 

   511     default:

   512         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   513         break;

   514     }

   515 }

   516 

   517 static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {

   518     pxa2xx_mm_read,

   519     pxa2xx_mm_read,

   520     pxa2xx_mm_read,

   521 };

   522 

   523 static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {

   524     pxa2xx_mm_write,

   525     pxa2xx_mm_write,

   526     pxa2xx_mm_write,

   527 };

   528 

   529 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)

   530 {

   531     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   532     int i;

   533 

   534     for (i = 0; i < 0x1a; i ++)

   535         qemu_put_be32s(f, &s->mm_regs[i]);

   536 }

   537 

   538 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)

   539 {

   540     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   541     int i;

   542 

   543     for (i = 0; i < 0x1a; i ++)

   544         qemu_get_be32s(f, &s->mm_regs[i]);

   545 

   546     return 0;

   547 }

   548 

   549 /* Synchronous Serial Ports */

   550 struct pxa2xx_ssp_s {

   551     qemu_irq irq;

   552     int enable;

   553 

   554     uint32_t sscr[2];

   555     uint32_t sspsp;

   556     uint32_t ssto;

   557     uint32_t ssitr;

   558     uint32_t sssr;

   559     uint8_t sstsa;

   560     uint8_t ssrsa;

   561     uint8_t ssacd;

   562 

   563     uint32_t rx_fifo[16];

   564     int rx_level;

   565     int rx_start;

   566 

   567     uint32_t (*readfn)(void *opaque);

   568     void (*writefn)(void *opaque, uint32_t value);

   569     void *opaque;

   570 };

   571 

   572 #define SSCR0	0x00	/* SSP Control register 0 */

   573 #define SSCR1	0x04	/* SSP Control register 1 */

   574 #define SSSR	0x08	/* SSP Status register */

   575 #define SSITR	0x0c	/* SSP Interrupt Test register */

   576 #define SSDR	0x10	/* SSP Data register */

   577 #define SSTO	0x28	/* SSP Time-Out register */

   578 #define SSPSP	0x2c	/* SSP Programmable Serial Protocol register */

   579 #define SSTSA	0x30	/* SSP TX Time Slot Active register */

   580 #define SSRSA	0x34	/* SSP RX Time Slot Active register */

   581 #define SSTSS	0x38	/* SSP Time Slot Status register */

   582 #define SSACD	0x3c	/* SSP Audio Clock Divider register */

   583 

   584 /* Bitfields for above registers */

   585 #define SSCR0_SPI(x)	(((x) & 0x30) == 0x00)

   586 #define SSCR0_SSP(x)	(((x) & 0x30) == 0x10)

   587 #define SSCR0_UWIRE(x)	(((x) & 0x30) == 0x20)

   588 #define SSCR0_PSP(x)	(((x) & 0x30) == 0x30)

   589 #define SSCR0_SSE	(1 << 7)

   590 #define SSCR0_RIM	(1 << 22)

   591 #define SSCR0_TIM	(1 << 23)

   592 #define SSCR0_MOD	(1 << 31)

   593 #define SSCR0_DSS(x)	(((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)

   594 #define SSCR1_RIE	(1 << 0)

   595 #define SSCR1_TIE	(1 << 1)

   596 #define SSCR1_LBM	(1 << 2)

   597 #define SSCR1_MWDS	(1 << 5)

   598 #define SSCR1_TFT(x)	((((x) >> 6) & 0xf) + 1)

   599 #define SSCR1_RFT(x)	((((x) >> 10) & 0xf) + 1)

   600 #define SSCR1_EFWR	(1 << 14)

   601 #define SSCR1_PINTE	(1 << 18)

   602 #define SSCR1_TINTE	(1 << 19)

   603 #define SSCR1_RSRE	(1 << 20)

   604 #define SSCR1_TSRE	(1 << 21)

   605 #define SSCR1_EBCEI	(1 << 29)

   606 #define SSITR_INT	(7 << 5)

   607 #define SSSR_TNF	(1 << 2)

   608 #define SSSR_RNE	(1 << 3)

   609 #define SSSR_TFS	(1 << 5)

   610 #define SSSR_RFS	(1 << 6)

   611 #define SSSR_ROR	(1 << 7)

   612 #define SSSR_PINT	(1 << 18)

   613 #define SSSR_TINT	(1 << 19)

   614 #define SSSR_EOC	(1 << 20)

   615 #define SSSR_TUR	(1 << 21)

   616 #define SSSR_BCE	(1 << 23)

   617 #define SSSR_RW		0x00bc0080

   618 

   619 static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)

   620 {

   621     int level = 0;

   622 

   623     level |= s->ssitr & SSITR_INT;

   624     level |= (s->sssr & SSSR_BCE)  &&  (s->sscr[1] & SSCR1_EBCEI);

   625     level |= (s->sssr & SSSR_TUR)  && !(s->sscr[0] & SSCR0_TIM);

   626     level |= (s->sssr & SSSR_EOC)  &&  (s->sssr & (SSSR_TINT | SSSR_PINT));

   627     level |= (s->sssr & SSSR_TINT) &&  (s->sscr[1] & SSCR1_TINTE);

   628     level |= (s->sssr & SSSR_PINT) &&  (s->sscr[1] & SSCR1_PINTE);

   629     level |= (s->sssr & SSSR_ROR)  && !(s->sscr[0] & SSCR0_RIM);

   630     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);

   631     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);

   632     qemu_set_irq(s->irq, !!level);

   633 }

   634 

   635 static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)

   636 {

   637     s->sssr &= ~(0xf << 12);	/* Clear RFL */

   638     s->sssr &= ~(0xf << 8);	/* Clear TFL */

   639     s->sssr &= ~SSSR_TNF;

   640     if (s->enable) {

   641         s->sssr |= ((s->rx_level - 1) & 0xf) << 12;

   642         if (s->rx_level >= SSCR1_RFT(s->sscr[1]))

   643             s->sssr |= SSSR_RFS;

   644         else

   645             s->sssr &= ~SSSR_RFS;

   646         if (0 <= SSCR1_TFT(s->sscr[1]))

   647             s->sssr |= SSSR_TFS;

   648         else

   649             s->sssr &= ~SSSR_TFS;

   650         if (s->rx_level)

   651             s->sssr |= SSSR_RNE;

   652         else

   653             s->sssr &= ~SSSR_RNE;

   654         s->sssr |= SSSR_TNF;

   655     }

   656 

   657     pxa2xx_ssp_int_update(s);

   658 }

   659 

   660 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)

   661 {

   662     struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;

   663     uint32_t retval;

   664 

   665     switch (addr) {

   666     case SSCR0:

   667         return s->sscr[0];

   668     case SSCR1:

   669         return s->sscr[1];

   670     case SSPSP:

   671         return s->sspsp;

   672     case SSTO:

   673         return s->ssto;

   674     case SSITR:

   675         return s->ssitr;

   676     case SSSR:

   677         return s->sssr | s->ssitr;

   678     case SSDR:

   679         if (!s->enable)

   680             return 0xffffffff;

   681         if (s->rx_level < 1) {

   682             printf("%s: SSP Rx Underrun\n", __FUNCTION__);

   683             return 0xffffffff;

   684         }

   685         s->rx_level --;

   686         retval = s->rx_fifo[s->rx_start ++];

   687         s->rx_start &= 0xf;

   688         pxa2xx_ssp_fifo_update(s);

   689         return retval;

   690     case SSTSA:

   691         return s->sstsa;

   692     case SSRSA:

   693         return s->ssrsa;

   694     case SSTSS:

   695         return 0;

   696     case SSACD:

   697         return s->ssacd;

   698     default:

   699         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   700         break;

   701     }

   702     return 0;

   703 }

   704 

   705 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,

   706                 uint32_t value)

   707 {

   708     struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;

   709 

   710     switch (addr) {

   711     case SSCR0:

   712         s->sscr[0] = value & 0xc7ffffff;

   713         s->enable = value & SSCR0_SSE;

   714         if (value & SSCR0_MOD)

   715             printf("%s: Attempt to use network mode\n", __FUNCTION__);

   716         if (s->enable && SSCR0_DSS(value) < 4)

   717             printf("%s: Wrong data size: %i bits\n", __FUNCTION__,

   718                             SSCR0_DSS(value));

   719         if (!(value & SSCR0_SSE)) {

   720             s->sssr = 0;

   721             s->ssitr = 0;

   722             s->rx_level = 0;

   723         }

   724         pxa2xx_ssp_fifo_update(s);

   725         break;

   726 

   727     case SSCR1:

   728         s->sscr[1] = value;

   729         if (value & (SSCR1_LBM | SSCR1_EFWR))

   730             printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);

   731         pxa2xx_ssp_fifo_update(s);

   732         break;

   733 

   734     case SSPSP:

   735         s->sspsp = value;

   736         break;

   737 

   738     case SSTO:

   739         s->ssto = value;

   740         break;

   741 

   742     case SSITR:

   743         s->ssitr = value & SSITR_INT;

   744         pxa2xx_ssp_int_update(s);

   745         break;

   746 

   747     case SSSR:

   748         s->sssr &= ~(value & SSSR_RW);

   749         pxa2xx_ssp_int_update(s);

   750         break;

   751 

   752     case SSDR:

   753         if (SSCR0_UWIRE(s->sscr[0])) {

   754             if (s->sscr[1] & SSCR1_MWDS)

   755                 value &= 0xffff;

   756             else

   757                 value &= 0xff;

   758         } else

   759             /* Note how 32bits overflow does no harm here */

   760             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;

   761 

   762         /* Data goes from here to the Tx FIFO and is shifted out from

   763          * there directly to the slave, no need to buffer it.

   764          */

   765         if (s->enable) {

   766             if (s->writefn)

   767                 s->writefn(s->opaque, value);

   768 

   769             if (s->rx_level < 0x10) {

   770                 if (s->readfn)

   771                     s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =

   772                             s->readfn(s->opaque);

   773                 else

   774                     s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;

   775             } else

   776                 s->sssr |= SSSR_ROR;

   777         }

   778         pxa2xx_ssp_fifo_update(s);

   779         break;

   780 

   781     case SSTSA:

   782         s->sstsa = value;

   783         break;

   784 

   785     case SSRSA:

   786         s->ssrsa = value;

   787         break;

   788 

   789     case SSACD:

   790         s->ssacd = value;

   791         break;

   792 

   793     default:

   794         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

   795         break;

   796     }

   797 }

   798 

   799 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,

   800                 uint32_t (*readfn)(void *opaque),

   801                 void (*writefn)(void *opaque, uint32_t value), void *opaque)

   802 {

   803     if (!port) {

   804         printf("%s: no such SSP\n", __FUNCTION__);

   805         exit(-1);

   806     }

   807 

   808     port->opaque = opaque;

   809     port->readfn = readfn;

   810     port->writefn = writefn;

   811 }

   812 

   813 static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {

   814     pxa2xx_ssp_read,

   815     pxa2xx_ssp_read,

   816     pxa2xx_ssp_read,

   817 };

   818 

   819 static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {

   820     pxa2xx_ssp_write,

   821     pxa2xx_ssp_write,

   822     pxa2xx_ssp_write,

   823 };

   824 

   825 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)

   826 {

   827     struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;

   828     int i;

   829 

   830     qemu_put_be32(f, s->enable);

   831 

   832     qemu_put_be32s(f, &s->sscr[0]);

   833     qemu_put_be32s(f, &s->sscr[1]);

   834     qemu_put_be32s(f, &s->sspsp);

   835     qemu_put_be32s(f, &s->ssto);

   836     qemu_put_be32s(f, &s->ssitr);

   837     qemu_put_be32s(f, &s->sssr);

   838     qemu_put_8s(f, &s->sstsa);

   839     qemu_put_8s(f, &s->ssrsa);

   840     qemu_put_8s(f, &s->ssacd);

   841 

   842     qemu_put_byte(f, s->rx_level);

   843     for (i = 0; i < s->rx_level; i ++)

   844         qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);

   845 }

   846 

   847 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)

   848 {

   849     struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;

   850     int i;

   851 

   852     s->enable = qemu_get_be32(f);

   853 

   854     qemu_get_be32s(f, &s->sscr[0]);

   855     qemu_get_be32s(f, &s->sscr[1]);

   856     qemu_get_be32s(f, &s->sspsp);

   857     qemu_get_be32s(f, &s->ssto);

   858     qemu_get_be32s(f, &s->ssitr);

   859     qemu_get_be32s(f, &s->sssr);

   860     qemu_get_8s(f, &s->sstsa);

   861     qemu_get_8s(f, &s->ssrsa);

   862     qemu_get_8s(f, &s->ssacd);

   863 

   864     s->rx_level = qemu_get_byte(f);

   865     s->rx_start = 0;

   866     for (i = 0; i < s->rx_level; i ++)

   867         s->rx_fifo[i] = qemu_get_byte(f);

   868 

   869     return 0;

   870 }

   871 

   872 /* Real-Time Clock */

   873 #define RCNR		0x00	/* RTC Counter register */

   874 #define RTAR		0x04	/* RTC Alarm register */

   875 #define RTSR		0x08	/* RTC Status register */

   876 #define RTTR		0x0c	/* RTC Timer Trim register */

   877 #define RDCR		0x10	/* RTC Day Counter register */

   878 #define RYCR		0x14	/* RTC Year Counter register */

   879 #define RDAR1		0x18	/* RTC Wristwatch Day Alarm register 1 */

   880 #define RYAR1		0x1c	/* RTC Wristwatch Year Alarm register 1 */

   881 #define RDAR2		0x20	/* RTC Wristwatch Day Alarm register 2 */

   882 #define RYAR2		0x24	/* RTC Wristwatch Year Alarm register 2 */

   883 #define SWCR		0x28	/* RTC Stopwatch Counter register */

   884 #define SWAR1		0x2c	/* RTC Stopwatch Alarm register 1 */

   885 #define SWAR2		0x30	/* RTC Stopwatch Alarm register 2 */

   886 #define RTCPICR		0x34	/* RTC Periodic Interrupt Counter register */

   887 #define PIAR		0x38	/* RTC Periodic Interrupt Alarm register */

   888 

   889 static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)

   890 {

   891     qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));

   892 }

   893 

   894 static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)

   895 {

   896     int64_t rt = qemu_get_clock(rt_clock);

   897     s->last_rcnr += ((rt - s->last_hz) << 15) /

   898             (1000 * ((s->rttr & 0xffff) + 1));

   899     s->last_rdcr += ((rt - s->last_hz) << 15) /

   900             (1000 * ((s->rttr & 0xffff) + 1));

   901     s->last_hz = rt;

   902 }

   903 

   904 static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)

   905 {

   906     int64_t rt = qemu_get_clock(rt_clock);

   907     if (s->rtsr & (1 << 12))

   908         s->last_swcr += (rt - s->last_sw) / 10;

   909     s->last_sw = rt;

   910 }

   911 

   912 static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)

   913 {

   914     int64_t rt = qemu_get_clock(rt_clock);

   915     if (s->rtsr & (1 << 15))

   916         s->last_swcr += rt - s->last_pi;

   917     s->last_pi = rt;

   918 }

   919 

   920 static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,

   921                 uint32_t rtsr)

   922 {

   923     if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))

   924         qemu_mod_timer(s->rtc_hz, s->last_hz +

   925                 (((s->rtar - s->last_rcnr) * 1000 *

   926                   ((s->rttr & 0xffff) + 1)) >> 15));

   927     else

   928         qemu_del_timer(s->rtc_hz);

   929 

   930     if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))

   931         qemu_mod_timer(s->rtc_rdal1, s->last_hz +

   932                 (((s->rdar1 - s->last_rdcr) * 1000 *

   933                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */

   934     else

   935         qemu_del_timer(s->rtc_rdal1);

   936 

   937     if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))

   938         qemu_mod_timer(s->rtc_rdal2, s->last_hz +

   939                 (((s->rdar2 - s->last_rdcr) * 1000 *

   940                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */

   941     else

   942         qemu_del_timer(s->rtc_rdal2);

   943 

   944     if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))

   945         qemu_mod_timer(s->rtc_swal1, s->last_sw +

   946                         (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */

   947     else

   948         qemu_del_timer(s->rtc_swal1);

   949 

   950     if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))

   951         qemu_mod_timer(s->rtc_swal2, s->last_sw +

   952                         (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */

   953     else

   954         qemu_del_timer(s->rtc_swal2);

   955 

   956     if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))

   957         qemu_mod_timer(s->rtc_pi, s->last_pi +

   958                         (s->piar & 0xffff) - s->last_rtcpicr);

   959     else

   960         qemu_del_timer(s->rtc_pi);

   961 }

   962 

   963 static inline void pxa2xx_rtc_hz_tick(void *opaque)

   964 {

   965     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   966     s->rtsr |= (1 << 0);

   967     pxa2xx_rtc_alarm_update(s, s->rtsr);

   968     pxa2xx_rtc_int_update(s);

   969 }

   970 

   971 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)

   972 {

   973     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   974     s->rtsr |= (1 << 4);

   975     pxa2xx_rtc_alarm_update(s, s->rtsr);

   976     pxa2xx_rtc_int_update(s);

   977 }

   978 

   979 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)

   980 {

   981     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   982     s->rtsr |= (1 << 6);

   983     pxa2xx_rtc_alarm_update(s, s->rtsr);

   984     pxa2xx_rtc_int_update(s);

   985 }

   986 

   987 static inline void pxa2xx_rtc_swal1_tick(void *opaque)

   988 {

   989     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   990     s->rtsr |= (1 << 8);

   991     pxa2xx_rtc_alarm_update(s, s->rtsr);

   992     pxa2xx_rtc_int_update(s);

   993 }

   994 

   995 static inline void pxa2xx_rtc_swal2_tick(void *opaque)

   996 {

   997     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

   998     s->rtsr |= (1 << 10);

   999     pxa2xx_rtc_alarm_update(s, s->rtsr);

  1000     pxa2xx_rtc_int_update(s);

  1001 }

  1002 

  1003 static inline void pxa2xx_rtc_pi_tick(void *opaque)

  1004 {

  1005     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

  1006     s->rtsr |= (1 << 13);

  1007     pxa2xx_rtc_piupdate(s);

  1008     s->last_rtcpicr = 0;

  1009     pxa2xx_rtc_alarm_update(s, s->rtsr);

  1010     pxa2xx_rtc_int_update(s);

  1011 }

  1012 

  1013 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)

  1014 {

  1015     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

  1016 

  1017     switch (addr) {

  1018     case RTTR:

  1019         return s->rttr;

  1020     case RTSR:

  1021         return s->rtsr;

  1022     case RTAR:

  1023         return s->rtar;

  1024     case RDAR1:

  1025         return s->rdar1;

  1026     case RDAR2:

  1027         return s->rdar2;

  1028     case RYAR1:

  1029         return s->ryar1;

  1030     case RYAR2:

  1031         return s->ryar2;

  1032     case SWAR1:

  1033         return s->swar1;

  1034     case SWAR2:

  1035         return s->swar2;

  1036     case PIAR:

  1037         return s->piar;

  1038     case RCNR:

  1039         return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /

  1040                 (1000 * ((s->rttr & 0xffff) + 1));

  1041     case RDCR:

  1042         return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /

  1043                 (1000 * ((s->rttr & 0xffff) + 1));

  1044     case RYCR:

  1045         return s->last_rycr;

  1046     case SWCR:

  1047         if (s->rtsr & (1 << 12))

  1048             return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;

  1049         else

  1050             return s->last_swcr;

  1051     default:

  1052         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

  1053         break;

  1054     }

  1055     return 0;

  1056 }

  1057 

  1058 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,

  1059                 uint32_t value)

  1060 {

  1061     struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;

  1062 

  1063     switch (addr) {

  1064     case RTTR:

  1065         if (!(s->rttr & (1 << 31))) {

  1066             pxa2xx_rtc_hzupdate(s);

  1067             s->rttr = value;

  1068             pxa2xx_rtc_alarm_update(s, s->rtsr);

  1069         }

  1070         break;

  1071 

  1072     case RTSR:

  1073         if ((s->rtsr ^ value) & (1 << 15))

  1074             pxa2xx_rtc_piupdate(s);

  1075 

  1076         if ((s->rtsr ^ value) & (1 << 12))

  1077             pxa2xx_rtc_swupdate(s);

  1078 

  1079         if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))

  1080             pxa2xx_rtc_alarm_update(s, value);

  1081 

  1082         s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));

  1083         pxa2xx_rtc_int_update(s);

  1084         break;

  1085 

  1086     case RTAR:

  1087         s->rtar = value;

  1088         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1089         break;

  1090 

  1091     case RDAR1:

  1092         s->rdar1 = value;

  1093         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1094         break;

  1095 

  1096     case RDAR2:

  1097         s->rdar2 = value;

  1098         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1099         break;

  1100 

  1101     case RYAR1:

  1102         s->ryar1 = value;

  1103         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1104         break;

  1105 

  1106     case RYAR2:

  1107         s->ryar2 = value;

  1108         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1109         break;

  1110 

  1111     case SWAR1:

  1112         pxa2xx_rtc_swupdate(s);

  1113         s->swar1 = value;

  1114         s->last_swcr = 0;

  1115         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1116         break;

  1117 

  1118     case SWAR2:

  1119         s->swar2 = value;

  1120         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1121         break;

  1122 

  1123     case PIAR:

  1124         s->piar = value;

  1125         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1126         break;

  1127 

  1128     case RCNR:

  1129         pxa2xx_rtc_hzupdate(s);

  1130         s->last_rcnr = value;

  1131         pxa2xx_rtc_alarm_update(s, s->rtsr);

  1132         break;

  1133 

  1134     case RDCR:

  1135         pxa2xx_rtc_hzupdate(s);