1 /*

     2  * QEMU Sparc SBI interrupt controller emulation

     3  *

     4  * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard

     5  *

     6  * Permission is hereby granted, free of charge, to any person obtaining a copy

     7  * of this software and associated documentation files (the "Software"), to deal

     8  * in the Software without restriction, including without limitation the rights

     9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    10  * copies of the Software, and to permit persons to whom the Software is

    11  * furnished to do so, subject to the following conditions:

    12  *

    13  * The above copyright notice and this permission notice shall be included in

    14  * all copies or substantial portions of the Software.

    15  *

    16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    22  * THE SOFTWARE.

    23  */

    24 #include "hw.h"

    25 #include "sun4m.h"

    26 #include "console.h"

    27 

    28 //#define DEBUG_IRQ

    29 

    30 #ifdef DEBUG_IRQ

    31 #define DPRINTF(fmt, args...) \

    32 do { printf("IRQ: " fmt , ##args); } while (0)

    33 #else

    34 #define DPRINTF(fmt, args...)

    35 #endif

    36 

    37 #define MAX_CPUS 16

    38 

    39 #define SBI_NREGS 16

    40 

    41 typedef struct SBIState {

    42     uint32_t regs[SBI_NREGS];

    43     uint32_t intreg_pending[MAX_CPUS];

    44     qemu_irq *cpu_irqs[MAX_CPUS];

    45     uint32_t pil_out[MAX_CPUS];

    46 } SBIState;

    47 

    48 #define SBI_SIZE (SBI_NREGS * 4)

    49 

    50 static void sbi_check_interrupts(void *opaque)

    51 {

    52 }

    53 

    54 static void sbi_set_irq(void *opaque, int irq, int level)

    55 {

    56 }

    57 

    58 static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level)

    59 {

    60 }

    61 

    62 static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)

    63 {

    64     SBIState *s = opaque;

    65     uint32_t saddr, ret;

    66 

    67     saddr = addr >> 2;

    68     switch (saddr) {

    69     default:

    70         ret = s->regs[saddr];

    71         break;

    72     }

    73     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);

    74 

    75     return ret;

    76 }

    77 

    78 static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)

    79 {

    80     SBIState *s = opaque;

    81     uint32_t saddr;

    82 

    83     saddr = addr >> 2;

    84     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);

    85     switch (saddr) {

    86     default:

    87         s->regs[saddr] = val;

    88         break;

    89     }

    90 }

    91 

    92 static CPUReadMemoryFunc *sbi_mem_read[3] = {

    93     NULL,

    94     NULL,

    95     sbi_mem_readl,

    96 };

    97 

    98 static CPUWriteMemoryFunc *sbi_mem_write[3] = {

    99     NULL,

   100     NULL,

   101     sbi_mem_writel,

   102 };

   103 

   104 static void sbi_save(QEMUFile *f, void *opaque)

   105 {

   106     SBIState *s = opaque;

   107     unsigned int i;

   108 

   109     for (i = 0; i < MAX_CPUS; i++) {

   110         qemu_put_be32s(f, &s->intreg_pending[i]);

   111     }

   112 }

   113 

   114 static int sbi_load(QEMUFile *f, void *opaque, int version_id)

   115 {

   116     SBIState *s = opaque;

   117     unsigned int i;

   118 

   119     if (version_id != 1)

   120         return -EINVAL;

   121 

   122     for (i = 0; i < MAX_CPUS; i++) {

   123         qemu_get_be32s(f, &s->intreg_pending[i]);

   124     }

   125     sbi_check_interrupts(s);

   126 

   127     return 0;

   128 }

   129 

   130 static void sbi_reset(void *opaque)

   131 {

   132     SBIState *s = opaque;

   133     unsigned int i;

   134 

   135     for (i = 0; i < MAX_CPUS; i++) {

   136         s->intreg_pending[i] = 0;

   137     }

   138     sbi_check_interrupts(s);

   139 }

   140 

   141 void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,

   142                qemu_irq **parent_irq)

   143 {

   144     unsigned int i;

   145     int sbi_io_memory;

   146     SBIState *s;

   147 

   148     s = qemu_mallocz(sizeof(SBIState));

   149     if (!s)

   150         return NULL;

   151 

   152     for (i = 0; i < MAX_CPUS; i++) {

   153         s->cpu_irqs[i] = parent_irq[i];

   154     }

   155 

   156     sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);

   157     cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);

   158 

   159     register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);

   160     qemu_register_reset(sbi_reset, s);

   161     *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);

   162     *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);

   163     sbi_reset(s);

   164 

   165     return s;

   166 }