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1 /* |
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2 * QEMU Sparc SBI interrupt controller emulation |
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3 * |
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4 * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "sun4m.h" |
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26 #include "console.h" |
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27 |
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28 //#define DEBUG_IRQ |
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29 |
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30 #ifdef DEBUG_IRQ |
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31 #define DPRINTF(fmt, args...) \ |
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32 do { printf("IRQ: " fmt , ##args); } while (0) |
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33 #else |
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34 #define DPRINTF(fmt, args...) |
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35 #endif |
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36 |
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37 #define MAX_CPUS 16 |
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38 |
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39 #define SBI_NREGS 16 |
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40 |
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41 typedef struct SBIState { |
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42 uint32_t regs[SBI_NREGS]; |
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43 uint32_t intreg_pending[MAX_CPUS]; |
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44 qemu_irq *cpu_irqs[MAX_CPUS]; |
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45 uint32_t pil_out[MAX_CPUS]; |
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46 } SBIState; |
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47 |
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48 #define SBI_SIZE (SBI_NREGS * 4) |
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49 |
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50 static void sbi_check_interrupts(void *opaque) |
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51 { |
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52 } |
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53 |
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54 static void sbi_set_irq(void *opaque, int irq, int level) |
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55 { |
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56 } |
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57 |
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58 static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level) |
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59 { |
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60 } |
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61 |
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62 static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) |
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63 { |
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64 SBIState *s = opaque; |
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65 uint32_t saddr, ret; |
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66 |
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67 saddr = addr >> 2; |
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68 switch (saddr) { |
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69 default: |
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70 ret = s->regs[saddr]; |
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71 break; |
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72 } |
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73 DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
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74 |
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75 return ret; |
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76 } |
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77 |
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78 static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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79 { |
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80 SBIState *s = opaque; |
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81 uint32_t saddr; |
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82 |
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83 saddr = addr >> 2; |
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84 DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
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85 switch (saddr) { |
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86 default: |
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87 s->regs[saddr] = val; |
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88 break; |
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89 } |
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90 } |
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91 |
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92 static CPUReadMemoryFunc *sbi_mem_read[3] = { |
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93 NULL, |
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94 NULL, |
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95 sbi_mem_readl, |
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96 }; |
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97 |
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98 static CPUWriteMemoryFunc *sbi_mem_write[3] = { |
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99 NULL, |
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100 NULL, |
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101 sbi_mem_writel, |
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102 }; |
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103 |
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104 static void sbi_save(QEMUFile *f, void *opaque) |
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105 { |
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106 SBIState *s = opaque; |
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107 unsigned int i; |
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108 |
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109 for (i = 0; i < MAX_CPUS; i++) { |
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110 qemu_put_be32s(f, &s->intreg_pending[i]); |
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111 } |
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112 } |
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113 |
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114 static int sbi_load(QEMUFile *f, void *opaque, int version_id) |
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115 { |
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116 SBIState *s = opaque; |
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117 unsigned int i; |
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118 |
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119 if (version_id != 1) |
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120 return -EINVAL; |
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121 |
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122 for (i = 0; i < MAX_CPUS; i++) { |
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123 qemu_get_be32s(f, &s->intreg_pending[i]); |
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124 } |
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125 sbi_check_interrupts(s); |
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126 |
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127 return 0; |
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128 } |
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129 |
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130 static void sbi_reset(void *opaque) |
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131 { |
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132 SBIState *s = opaque; |
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133 unsigned int i; |
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134 |
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135 for (i = 0; i < MAX_CPUS; i++) { |
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136 s->intreg_pending[i] = 0; |
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137 } |
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138 sbi_check_interrupts(s); |
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139 } |
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140 |
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141 void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, |
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142 qemu_irq **parent_irq) |
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143 { |
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144 unsigned int i; |
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145 int sbi_io_memory; |
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146 SBIState *s; |
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147 |
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148 s = qemu_mallocz(sizeof(SBIState)); |
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149 if (!s) |
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150 return NULL; |
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151 |
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152 for (i = 0; i < MAX_CPUS; i++) { |
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153 s->cpu_irqs[i] = parent_irq[i]; |
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154 } |
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155 |
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156 sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s); |
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157 cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory); |
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158 |
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159 register_savevm("sbi", addr, 1, sbi_save, sbi_load, s); |
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160 qemu_register_reset(sbi_reset, s); |
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161 *irq = qemu_allocate_irqs(sbi_set_irq, s, 32); |
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162 *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS); |
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163 sbi_reset(s); |
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164 |
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165 return s; |
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166 } |