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1 /* |
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2 * SH7750 device |
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3 * |
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4 * Copyright (c) 2007 Magnus Damm |
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5 * Copyright (c) 2005 Samuel Tardieu |
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6 * |
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7 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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8 * of this software and associated documentation files (the "Software"), to deal |
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9 * in the Software without restriction, including without limitation the rights |
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10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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11 * copies of the Software, and to permit persons to whom the Software is |
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12 * furnished to do so, subject to the following conditions: |
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13 * |
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14 * The above copyright notice and this permission notice shall be included in |
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15 * all copies or substantial portions of the Software. |
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16 * |
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17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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23 * THE SOFTWARE. |
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24 */ |
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25 #include <stdio.h> |
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26 #include <assert.h> |
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27 #include "hw.h" |
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28 #include "sh.h" |
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29 #include "sysemu.h" |
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30 #include "sh7750_regs.h" |
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31 #include "sh7750_regnames.h" |
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32 #include "sh_intc.h" |
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33 #include "exec-all.h" |
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34 #include "cpu.h" |
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35 |
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36 #define NB_DEVICES 4 |
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37 |
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38 typedef struct SH7750State { |
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39 /* CPU */ |
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40 CPUSH4State *cpu; |
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41 /* Peripheral frequency in Hz */ |
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42 uint32_t periph_freq; |
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43 /* SDRAM controller */ |
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44 uint32_t bcr1; |
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45 uint32_t bcr2; |
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46 uint16_t rfcr; |
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47 /* IO ports */ |
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48 uint16_t gpioic; |
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49 uint32_t pctra; |
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50 uint32_t pctrb; |
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51 uint16_t portdira; /* Cached */ |
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52 uint16_t portpullupa; /* Cached */ |
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53 uint16_t portdirb; /* Cached */ |
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54 uint16_t portpullupb; /* Cached */ |
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55 uint16_t pdtra; |
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56 uint16_t pdtrb; |
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57 uint16_t periph_pdtra; /* Imposed by the peripherals */ |
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58 uint16_t periph_portdira; /* Direction seen from the peripherals */ |
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59 uint16_t periph_pdtrb; /* Imposed by the peripherals */ |
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60 uint16_t periph_portdirb; /* Direction seen from the peripherals */ |
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61 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ |
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62 |
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63 /* Cache */ |
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64 uint32_t ccr; |
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65 |
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66 struct intc_desc intc; |
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67 } SH7750State; |
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68 |
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69 |
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70 /********************************************************************** |
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71 I/O ports |
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72 **********************************************************************/ |
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73 |
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74 int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) |
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75 { |
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76 int i; |
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77 |
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78 for (i = 0; i < NB_DEVICES; i++) { |
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79 if (s->devices[i] == NULL) { |
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80 s->devices[i] = device; |
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81 return 0; |
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82 } |
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83 } |
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84 return -1; |
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85 } |
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86 |
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87 static uint16_t portdir(uint32_t v) |
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88 { |
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89 #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) |
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90 return |
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91 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | |
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92 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | |
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93 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | |
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94 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | |
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95 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | |
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96 EVENPORTMASK(0); |
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97 } |
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98 |
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99 static uint16_t portpullup(uint32_t v) |
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100 { |
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101 #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) |
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102 return |
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103 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | |
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104 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | |
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105 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | |
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106 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | |
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107 ODDPORTMASK(1) | ODDPORTMASK(0); |
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108 } |
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109 |
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110 static uint16_t porta_lines(SH7750State * s) |
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111 { |
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112 return (s->portdira & s->pdtra) | /* CPU */ |
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113 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ |
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114 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ |
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115 } |
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116 |
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117 static uint16_t portb_lines(SH7750State * s) |
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118 { |
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119 return (s->portdirb & s->pdtrb) | /* CPU */ |
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120 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ |
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121 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ |
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122 } |
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123 |
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124 static void gen_port_interrupts(SH7750State * s) |
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125 { |
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126 /* XXXXX interrupts not generated */ |
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127 } |
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128 |
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129 static void porta_changed(SH7750State * s, uint16_t prev) |
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130 { |
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131 uint16_t currenta, changes; |
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132 int i, r = 0; |
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133 |
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134 #if 0 |
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135 fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n", |
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136 prev, porta_lines(s)); |
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137 fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); |
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138 #endif |
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139 currenta = porta_lines(s); |
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140 if (currenta == prev) |
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141 return; |
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142 changes = currenta ^ prev; |
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143 |
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144 for (i = 0; i < NB_DEVICES; i++) { |
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145 if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) { |
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146 r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), |
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147 &s->periph_pdtra, |
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148 &s->periph_portdira, |
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149 &s->periph_pdtrb, |
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150 &s->periph_portdirb); |
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151 } |
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152 } |
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153 |
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154 if (r) |
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155 gen_port_interrupts(s); |
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156 } |
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157 |
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158 static void portb_changed(SH7750State * s, uint16_t prev) |
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159 { |
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160 uint16_t currentb, changes; |
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161 int i, r = 0; |
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162 |
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163 currentb = portb_lines(s); |
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164 if (currentb == prev) |
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165 return; |
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166 changes = currentb ^ prev; |
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167 |
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168 for (i = 0; i < NB_DEVICES; i++) { |
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169 if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) { |
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170 r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, |
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171 &s->periph_pdtra, |
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172 &s->periph_portdira, |
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173 &s->periph_pdtrb, |
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174 &s->periph_portdirb); |
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175 } |
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176 } |
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177 |
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178 if (r) |
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179 gen_port_interrupts(s); |
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180 } |
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181 |
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182 /********************************************************************** |
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183 Memory |
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184 **********************************************************************/ |
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185 |
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186 static void error_access(const char *kind, target_phys_addr_t addr) |
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187 { |
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188 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", |
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189 kind, regname(addr), addr); |
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190 } |
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191 |
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192 static void ignore_access(const char *kind, target_phys_addr_t addr) |
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193 { |
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194 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", |
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195 kind, regname(addr), addr); |
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196 } |
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197 |
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198 static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) |
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199 { |
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200 switch (addr) { |
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201 default: |
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202 error_access("byte read", addr); |
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203 assert(0); |
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204 } |
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205 } |
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206 |
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207 static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) |
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208 { |
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209 SH7750State *s = opaque; |
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210 |
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211 switch (addr) { |
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212 case SH7750_BCR2_A7: |
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213 return s->bcr2; |
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214 case SH7750_FRQCR_A7: |
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215 return 0; |
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216 case SH7750_RFCR_A7: |
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217 fprintf(stderr, |
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218 "Read access to refresh count register, incrementing\n"); |
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219 return s->rfcr++; |
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220 case SH7750_PDTRA_A7: |
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221 return porta_lines(s); |
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222 case SH7750_PDTRB_A7: |
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223 return portb_lines(s); |
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224 default: |
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225 error_access("word read", addr); |
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226 assert(0); |
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227 } |
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228 } |
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229 |
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230 static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) |
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231 { |
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232 SH7750State *s = opaque; |
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233 |
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234 switch (addr) { |
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235 case SH7750_BCR1_A7: |
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236 return s->bcr1; |
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237 case SH7750_BCR4_A7: |
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238 case SH7750_WCR1_A7: |
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239 case SH7750_WCR2_A7: |
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240 case SH7750_WCR3_A7: |
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241 case SH7750_MCR_A7: |
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242 ignore_access("long read", addr); |
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243 return 0; |
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244 case SH7750_MMUCR_A7: |
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245 return s->cpu->mmucr; |
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246 case SH7750_PTEH_A7: |
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247 return s->cpu->pteh; |
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248 case SH7750_PTEL_A7: |
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249 return s->cpu->ptel; |
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250 case SH7750_TTB_A7: |
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251 return s->cpu->ttb; |
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252 case SH7750_TEA_A7: |
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253 return s->cpu->tea; |
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254 case SH7750_TRA_A7: |
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255 return s->cpu->tra; |
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256 case SH7750_EXPEVT_A7: |
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257 return s->cpu->expevt; |
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258 case SH7750_INTEVT_A7: |
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259 return s->cpu->intevt; |
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260 case SH7750_CCR_A7: |
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261 return s->ccr; |
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262 case 0x1f000030: /* Processor version */ |
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263 return s->cpu->pvr; |
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264 case 0x1f000040: /* Cache version */ |
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265 return s->cpu->cvr; |
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266 case 0x1f000044: /* Processor revision */ |
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267 return s->cpu->prr; |
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268 default: |
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269 error_access("long read", addr); |
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270 assert(0); |
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271 } |
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272 } |
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273 |
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274 static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
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275 uint32_t mem_value) |
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276 { |
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277 switch (addr) { |
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278 /* PRECHARGE ? XXXXX */ |
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279 case SH7750_PRECHARGE0_A7: |
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280 case SH7750_PRECHARGE1_A7: |
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281 ignore_access("byte write", addr); |
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282 return; |
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283 default: |
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284 error_access("byte write", addr); |
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285 assert(0); |
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286 } |
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287 } |
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288 |
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289 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
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290 uint32_t mem_value) |
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291 { |
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292 SH7750State *s = opaque; |
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293 uint16_t temp; |
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294 |
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295 switch (addr) { |
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296 /* SDRAM controller */ |
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297 case SH7750_BCR2_A7: |
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298 s->bcr2 = mem_value; |
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299 return; |
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300 case SH7750_BCR3_A7: |
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301 case SH7750_RTCOR_A7: |
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302 case SH7750_RTCNT_A7: |
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303 case SH7750_RTCSR_A7: |
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304 ignore_access("word write", addr); |
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305 return; |
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306 /* IO ports */ |
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307 case SH7750_PDTRA_A7: |
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308 temp = porta_lines(s); |
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309 s->pdtra = mem_value; |
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310 porta_changed(s, temp); |
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311 return; |
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312 case SH7750_PDTRB_A7: |
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313 temp = portb_lines(s); |
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314 s->pdtrb = mem_value; |
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315 portb_changed(s, temp); |
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316 return; |
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317 case SH7750_RFCR_A7: |
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318 fprintf(stderr, "Write access to refresh count register\n"); |
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319 s->rfcr = mem_value; |
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320 return; |
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321 case SH7750_GPIOIC_A7: |
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322 s->gpioic = mem_value; |
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323 if (mem_value != 0) { |
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324 fprintf(stderr, "I/O interrupts not implemented\n"); |
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325 assert(0); |
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326 } |
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327 return; |
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328 default: |
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329 error_access("word write", addr); |
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330 assert(0); |
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331 } |
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332 } |
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333 |
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334 static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, |
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335 uint32_t mem_value) |
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336 { |
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337 SH7750State *s = opaque; |
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338 uint16_t temp; |
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339 |
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340 switch (addr) { |
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341 /* SDRAM controller */ |
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342 case SH7750_BCR1_A7: |
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343 s->bcr1 = mem_value; |
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344 return; |
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345 case SH7750_BCR4_A7: |
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346 case SH7750_WCR1_A7: |
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347 case SH7750_WCR2_A7: |
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348 case SH7750_WCR3_A7: |
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349 case SH7750_MCR_A7: |
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350 ignore_access("long write", addr); |
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351 return; |
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352 /* IO ports */ |
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353 case SH7750_PCTRA_A7: |
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354 temp = porta_lines(s); |
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355 s->pctra = mem_value; |
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356 s->portdira = portdir(mem_value); |
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357 s->portpullupa = portpullup(mem_value); |
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358 porta_changed(s, temp); |
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359 return; |
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360 case SH7750_PCTRB_A7: |
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361 temp = portb_lines(s); |
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362 s->pctrb = mem_value; |
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363 s->portdirb = portdir(mem_value); |
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364 s->portpullupb = portpullup(mem_value); |
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365 portb_changed(s, temp); |
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366 return; |
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367 case SH7750_MMUCR_A7: |
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368 s->cpu->mmucr = mem_value; |
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369 return; |
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370 case SH7750_PTEH_A7: |
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371 /* If asid changes, clear all registered tlb entries. */ |
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372 if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) |
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373 tlb_flush(s->cpu, 1); |
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374 s->cpu->pteh = mem_value; |
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375 return; |
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376 case SH7750_PTEL_A7: |
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377 s->cpu->ptel = mem_value; |
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378 return; |
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379 case SH7750_PTEA_A7: |
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380 s->cpu->ptea = mem_value & 0x0000000f; |
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381 return; |
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382 case SH7750_TTB_A7: |
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383 s->cpu->ttb = mem_value; |
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384 return; |
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385 case SH7750_TEA_A7: |
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386 s->cpu->tea = mem_value; |
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387 return; |
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388 case SH7750_TRA_A7: |
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389 s->cpu->tra = mem_value & 0x000007ff; |
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390 return; |
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391 case SH7750_EXPEVT_A7: |
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392 s->cpu->expevt = mem_value & 0x000007ff; |
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393 return; |
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394 case SH7750_INTEVT_A7: |
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395 s->cpu->intevt = mem_value & 0x000007ff; |
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396 return; |
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397 case SH7750_CCR_A7: |
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398 s->ccr = mem_value; |
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399 return; |
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400 default: |
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401 error_access("long write", addr); |
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402 assert(0); |
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403 } |
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404 } |
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405 |
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406 static CPUReadMemoryFunc *sh7750_mem_read[] = { |
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407 sh7750_mem_readb, |
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408 sh7750_mem_readw, |
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409 sh7750_mem_readl |
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410 }; |
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411 |
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412 static CPUWriteMemoryFunc *sh7750_mem_write[] = { |
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413 sh7750_mem_writeb, |
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414 sh7750_mem_writew, |
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415 sh7750_mem_writel |
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416 }; |
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417 |
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418 /* sh775x interrupt controller tables for sh_intc.c |
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419 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c |
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420 */ |
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421 |
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422 enum { |
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423 UNUSED = 0, |
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424 |
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425 /* interrupt sources */ |
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426 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, |
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427 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, |
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428 IRL0, IRL1, IRL2, IRL3, |
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429 HUDI, GPIOI, |
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430 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, |
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431 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, |
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432 DMAC_DMAE, |
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433 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
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434 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, |
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435 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, |
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436 RTC_ATI, RTC_PRI, RTC_CUI, |
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437 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, |
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438 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, |
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439 WDT, |
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440 REF_RCMI, REF_ROVI, |
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441 |
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442 /* interrupt groups */ |
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443 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, |
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444 /* irl bundle */ |
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445 IRL, |
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446 |
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447 NR_SOURCES, |
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448 }; |
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449 |
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450 static struct intc_vect vectors[] = { |
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451 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
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452 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
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453 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
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454 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), |
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455 INTC_VECT(RTC_CUI, 0x4c0), |
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456 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), |
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457 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), |
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458 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), |
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459 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), |
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460 INTC_VECT(WDT, 0x560), |
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461 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
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462 }; |
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463 |
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464 static struct intc_group groups[] = { |
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465 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
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466 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
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467 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), |
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468 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), |
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469 INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
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470 }; |
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471 |
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472 static struct intc_prio_reg prio_registers[] = { |
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473 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
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474 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, |
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475 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, |
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476 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, |
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477 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, |
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478 TMU4, TMU3, |
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479 PCIC1, PCIC0_PCISERR } }, |
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480 }; |
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481 |
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482 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ |
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483 |
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484 static struct intc_vect vectors_dma4[] = { |
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485 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
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486 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
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487 INTC_VECT(DMAC_DMAE, 0x6c0), |
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488 }; |
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489 |
|
490 static struct intc_group groups_dma4[] = { |
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491 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
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492 DMAC_DMTE3, DMAC_DMAE), |
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493 }; |
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494 |
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495 /* SH7750R and SH7751R both have 8-channel DMA controllers */ |
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496 |
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497 static struct intc_vect vectors_dma8[] = { |
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498 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
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499 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
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500 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), |
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501 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), |
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502 INTC_VECT(DMAC_DMAE, 0x6c0), |
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503 }; |
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504 |
|
505 static struct intc_group groups_dma8[] = { |
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506 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
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507 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
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508 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
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509 }; |
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510 |
|
511 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ |
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512 |
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513 static struct intc_vect vectors_tmu34[] = { |
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514 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), |
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515 }; |
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516 |
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517 static struct intc_mask_reg mask_registers[] = { |
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518 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
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519 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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520 0, 0, 0, 0, 0, 0, TMU4, TMU3, |
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521 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
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522 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, |
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523 PCIC1_PCIDMA3, PCIC0_PCISERR } }, |
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524 }; |
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525 |
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526 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ |
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527 |
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528 static struct intc_vect vectors_irlm[] = { |
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529 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
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530 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
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531 }; |
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532 |
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533 /* SH7751 and SH7751R both have PCI */ |
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534 |
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535 static struct intc_vect vectors_pci[] = { |
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536 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), |
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537 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), |
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538 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), |
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539 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), |
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540 }; |
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541 |
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542 static struct intc_group groups_pci[] = { |
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543 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
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544 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), |
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545 }; |
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546 |
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547 static struct intc_vect vectors_irl[] = { |
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548 INTC_VECT(IRL_0, 0x200), |
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549 INTC_VECT(IRL_1, 0x220), |
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550 INTC_VECT(IRL_2, 0x240), |
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551 INTC_VECT(IRL_3, 0x260), |
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552 INTC_VECT(IRL_4, 0x280), |
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553 INTC_VECT(IRL_5, 0x2a0), |
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554 INTC_VECT(IRL_6, 0x2c0), |
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555 INTC_VECT(IRL_7, 0x2e0), |
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556 INTC_VECT(IRL_8, 0x300), |
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557 INTC_VECT(IRL_9, 0x320), |
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558 INTC_VECT(IRL_A, 0x340), |
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559 INTC_VECT(IRL_B, 0x360), |
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560 INTC_VECT(IRL_C, 0x380), |
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561 INTC_VECT(IRL_D, 0x3a0), |
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562 INTC_VECT(IRL_E, 0x3c0), |
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563 }; |
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564 |
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565 static struct intc_group groups_irl[] = { |
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566 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, |
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567 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), |
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568 }; |
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569 |
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570 /********************************************************************** |
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571 Memory mapped cache and TLB |
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572 **********************************************************************/ |
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573 |
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574 #define MM_REGION_MASK 0x07000000 |
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575 #define MM_ICACHE_ADDR (0) |
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576 #define MM_ICACHE_DATA (1) |
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577 #define MM_ITLB_ADDR (2) |
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578 #define MM_ITLB_DATA (3) |
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579 #define MM_OCACHE_ADDR (4) |
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580 #define MM_OCACHE_DATA (5) |
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581 #define MM_UTLB_ADDR (6) |
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582 #define MM_UTLB_DATA (7) |
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583 #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) |
|
584 |
|
585 static uint32_t invalid_read(void *opaque, target_phys_addr_t addr) |
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586 { |
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587 assert(0); |
|
588 |
|
589 return 0; |
|
590 } |
|
591 |
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592 static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) |
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593 { |
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594 uint32_t ret = 0; |
|
595 |
|
596 switch (MM_REGION_TYPE(addr)) { |
|
597 case MM_ICACHE_ADDR: |
|
598 case MM_ICACHE_DATA: |
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599 /* do nothing */ |
|
600 break; |
|
601 case MM_ITLB_ADDR: |
|
602 case MM_ITLB_DATA: |
|
603 /* XXXXX */ |
|
604 assert(0); |
|
605 break; |
|
606 case MM_OCACHE_ADDR: |
|
607 case MM_OCACHE_DATA: |
|
608 /* do nothing */ |
|
609 break; |
|
610 case MM_UTLB_ADDR: |
|
611 case MM_UTLB_DATA: |
|
612 /* XXXXX */ |
|
613 assert(0); |
|
614 break; |
|
615 default: |
|
616 assert(0); |
|
617 } |
|
618 |
|
619 return ret; |
|
620 } |
|
621 |
|
622 static void invalid_write(void *opaque, target_phys_addr_t addr, |
|
623 uint32_t mem_value) |
|
624 { |
|
625 assert(0); |
|
626 } |
|
627 |
|
628 static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, |
|
629 uint32_t mem_value) |
|
630 { |
|
631 SH7750State *s = opaque; |
|
632 |
|
633 switch (MM_REGION_TYPE(addr)) { |
|
634 case MM_ICACHE_ADDR: |
|
635 case MM_ICACHE_DATA: |
|
636 /* do nothing */ |
|
637 break; |
|
638 case MM_ITLB_ADDR: |
|
639 case MM_ITLB_DATA: |
|
640 /* XXXXX */ |
|
641 assert(0); |
|
642 break; |
|
643 case MM_OCACHE_ADDR: |
|
644 case MM_OCACHE_DATA: |
|
645 /* do nothing */ |
|
646 break; |
|
647 case MM_UTLB_ADDR: |
|
648 cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); |
|
649 break; |
|
650 case MM_UTLB_DATA: |
|
651 /* XXXXX */ |
|
652 assert(0); |
|
653 break; |
|
654 default: |
|
655 assert(0); |
|
656 break; |
|
657 } |
|
658 } |
|
659 |
|
660 static CPUReadMemoryFunc *sh7750_mmct_read[] = { |
|
661 invalid_read, |
|
662 invalid_read, |
|
663 sh7750_mmct_readl |
|
664 }; |
|
665 |
|
666 static CPUWriteMemoryFunc *sh7750_mmct_write[] = { |
|
667 invalid_write, |
|
668 invalid_write, |
|
669 sh7750_mmct_writel |
|
670 }; |
|
671 |
|
672 SH7750State *sh7750_init(CPUSH4State * cpu) |
|
673 { |
|
674 SH7750State *s; |
|
675 int sh7750_io_memory; |
|
676 int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */ |
|
677 |
|
678 s = qemu_mallocz(sizeof(SH7750State)); |
|
679 s->cpu = cpu; |
|
680 s->periph_freq = 60000000; /* 60MHz */ |
|
681 sh7750_io_memory = cpu_register_io_memory(0, |
|
682 sh7750_mem_read, |
|
683 sh7750_mem_write, s); |
|
684 cpu_register_physical_memory_offset(0x1f000000, 0x1000, |
|
685 sh7750_io_memory, 0x1f000000); |
|
686 cpu_register_physical_memory_offset(0xff000000, 0x1000, |
|
687 sh7750_io_memory, 0x1f000000); |
|
688 cpu_register_physical_memory_offset(0x1f800000, 0x1000, |
|
689 sh7750_io_memory, 0x1f800000); |
|
690 cpu_register_physical_memory_offset(0xff800000, 0x1000, |
|
691 sh7750_io_memory, 0x1f800000); |
|
692 cpu_register_physical_memory_offset(0x1fc00000, 0x1000, |
|
693 sh7750_io_memory, 0x1fc00000); |
|
694 cpu_register_physical_memory_offset(0xffc00000, 0x1000, |
|
695 sh7750_io_memory, 0x1fc00000); |
|
696 |
|
697 sh7750_mm_cache_and_tlb = cpu_register_io_memory(0, |
|
698 sh7750_mmct_read, |
|
699 sh7750_mmct_write, s); |
|
700 cpu_register_physical_memory(0xf0000000, 0x08000000, |
|
701 sh7750_mm_cache_and_tlb); |
|
702 |
|
703 sh_intc_init(&s->intc, NR_SOURCES, |
|
704 _INTC_ARRAY(mask_registers), |
|
705 _INTC_ARRAY(prio_registers)); |
|
706 |
|
707 sh_intc_register_sources(&s->intc, |
|
708 _INTC_ARRAY(vectors), |
|
709 _INTC_ARRAY(groups)); |
|
710 |
|
711 cpu->intc_handle = &s->intc; |
|
712 |
|
713 sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0], |
|
714 s->intc.irqs[SCI1_ERI], |
|
715 s->intc.irqs[SCI1_RXI], |
|
716 s->intc.irqs[SCI1_TXI], |
|
717 s->intc.irqs[SCI1_TEI], |
|
718 NULL); |
|
719 sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF, |
|
720 s->periph_freq, serial_hds[1], |
|
721 s->intc.irqs[SCIF_ERI], |
|
722 s->intc.irqs[SCIF_RXI], |
|
723 s->intc.irqs[SCIF_TXI], |
|
724 NULL, |
|
725 s->intc.irqs[SCIF_BRI]); |
|
726 |
|
727 tmu012_init(0x1fd80000, |
|
728 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
|
729 s->periph_freq, |
|
730 s->intc.irqs[TMU0], |
|
731 s->intc.irqs[TMU1], |
|
732 s->intc.irqs[TMU2_TUNI], |
|
733 s->intc.irqs[TMU2_TICPI]); |
|
734 |
|
735 if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { |
|
736 sh_intc_register_sources(&s->intc, |
|
737 _INTC_ARRAY(vectors_dma4), |
|
738 _INTC_ARRAY(groups_dma4)); |
|
739 } |
|
740 |
|
741 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { |
|
742 sh_intc_register_sources(&s->intc, |
|
743 _INTC_ARRAY(vectors_dma8), |
|
744 _INTC_ARRAY(groups_dma8)); |
|
745 } |
|
746 |
|
747 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { |
|
748 sh_intc_register_sources(&s->intc, |
|
749 _INTC_ARRAY(vectors_tmu34), |
|
750 NULL, 0); |
|
751 tmu012_init(0x1e100000, 0, s->periph_freq, |
|
752 s->intc.irqs[TMU3], |
|
753 s->intc.irqs[TMU4], |
|
754 NULL, NULL); |
|
755 } |
|
756 |
|
757 if (cpu->id & (SH_CPU_SH7751_ALL)) { |
|
758 sh_intc_register_sources(&s->intc, |
|
759 _INTC_ARRAY(vectors_pci), |
|
760 _INTC_ARRAY(groups_pci)); |
|
761 } |
|
762 |
|
763 if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { |
|
764 sh_intc_register_sources(&s->intc, |
|
765 _INTC_ARRAY(vectors_irlm), |
|
766 NULL, 0); |
|
767 } |
|
768 |
|
769 sh_intc_register_sources(&s->intc, |
|
770 _INTC_ARRAY(vectors_irl), |
|
771 _INTC_ARRAY(groups_irl)); |
|
772 return s; |
|
773 } |
|
774 |
|
775 qemu_irq sh7750_irl(SH7750State *s) |
|
776 { |
|
777 sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ |
|
778 return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), |
|
779 1)[0]; |
|
780 } |