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1 /* |
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2 * SuperH interrupt controller module |
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3 * |
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4 * Copyright (c) 2007 Magnus Damm |
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5 * Based on sh_timer.c and arm_timer.c by Paul Brook |
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6 * Copyright (c) 2005-2006 CodeSourcery. |
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7 * |
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8 * This code is licenced under the GPL. |
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9 */ |
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10 |
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11 #include <assert.h> |
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12 #include "sh_intc.h" |
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13 #include "hw.h" |
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14 #include "sh.h" |
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15 |
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16 //#define DEBUG_INTC |
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17 //#define DEBUG_INTC_SOURCES |
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18 |
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19 #define INTC_A7(x) ((x) & 0x1fffffff) |
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20 |
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21 void sh_intc_toggle_source(struct intc_source *source, |
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22 int enable_adj, int assert_adj) |
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23 { |
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24 int enable_changed = 0; |
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25 int pending_changed = 0; |
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26 int old_pending; |
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27 |
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28 if ((source->enable_count == source->enable_max) && (enable_adj == -1)) |
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29 enable_changed = -1; |
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30 |
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31 source->enable_count += enable_adj; |
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32 |
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33 if (source->enable_count == source->enable_max) |
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34 enable_changed = 1; |
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35 |
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36 source->asserted += assert_adj; |
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37 |
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38 old_pending = source->pending; |
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39 source->pending = source->asserted && |
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40 (source->enable_count == source->enable_max); |
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41 |
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42 if (old_pending != source->pending) |
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43 pending_changed = 1; |
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44 |
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45 if (pending_changed) { |
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46 if (source->pending) { |
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47 source->parent->pending++; |
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48 if (source->parent->pending == 1) |
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49 cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
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50 } |
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51 else { |
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52 source->parent->pending--; |
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53 if (source->parent->pending == 0) |
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54 cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
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55 } |
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56 } |
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57 |
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58 if (enable_changed || assert_adj || pending_changed) { |
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59 #ifdef DEBUG_INTC_SOURCES |
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60 printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n", |
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61 source->parent->pending, |
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62 source->asserted, |
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63 source->enable_count, |
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64 source->enable_max, |
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65 source->vect, |
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66 source->asserted ? "asserted " : |
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67 assert_adj ? "deasserted" : "", |
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68 enable_changed == 1 ? "enabled " : |
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69 enable_changed == -1 ? "disabled " : "", |
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70 source->pending ? "pending" : ""); |
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71 #endif |
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72 } |
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73 } |
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74 |
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75 static void sh_intc_set_irq (void *opaque, int n, int level) |
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76 { |
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77 struct intc_desc *desc = opaque; |
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78 struct intc_source *source = &(desc->sources[n]); |
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79 |
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80 if (level && !source->asserted) |
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81 sh_intc_toggle_source(source, 0, 1); |
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82 else if (!level && source->asserted) |
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83 sh_intc_toggle_source(source, 0, -1); |
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84 } |
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85 |
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86 int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) |
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87 { |
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88 unsigned int i; |
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89 |
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90 /* slow: use a linked lists of pending sources instead */ |
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91 /* wrong: take interrupt priority into account (one list per priority) */ |
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92 |
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93 if (imask == 0x0f) { |
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94 return -1; /* FIXME, update code to include priority per source */ |
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95 } |
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96 |
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97 for (i = 0; i < desc->nr_sources; i++) { |
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98 struct intc_source *source = desc->sources + i; |
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99 |
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100 if (source->pending) { |
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101 #ifdef DEBUG_INTC_SOURCES |
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102 printf("sh_intc: (%d) returning interrupt source 0x%x\n", |
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103 desc->pending, source->vect); |
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104 #endif |
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105 return source->vect; |
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106 } |
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107 } |
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108 |
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109 assert(0); |
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110 } |
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111 |
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112 #define INTC_MODE_NONE 0 |
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113 #define INTC_MODE_DUAL_SET 1 |
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114 #define INTC_MODE_DUAL_CLR 2 |
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115 #define INTC_MODE_ENABLE_REG 3 |
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116 #define INTC_MODE_MASK_REG 4 |
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117 #define INTC_MODE_IS_PRIO 8 |
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118 |
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119 static unsigned int sh_intc_mode(unsigned long address, |
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120 unsigned long set_reg, unsigned long clr_reg) |
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121 { |
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122 if ((address != INTC_A7(set_reg)) && |
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123 (address != INTC_A7(clr_reg))) |
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124 return INTC_MODE_NONE; |
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125 |
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126 if (set_reg && clr_reg) { |
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127 if (address == INTC_A7(set_reg)) |
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128 return INTC_MODE_DUAL_SET; |
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129 else |
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130 return INTC_MODE_DUAL_CLR; |
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131 } |
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132 |
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133 if (set_reg) |
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134 return INTC_MODE_ENABLE_REG; |
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135 else |
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136 return INTC_MODE_MASK_REG; |
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137 } |
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138 |
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139 static void sh_intc_locate(struct intc_desc *desc, |
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140 unsigned long address, |
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141 unsigned long **datap, |
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142 intc_enum **enums, |
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143 unsigned int *first, |
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144 unsigned int *width, |
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145 unsigned int *modep) |
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146 { |
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147 unsigned int i, mode; |
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148 |
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149 /* this is slow but works for now */ |
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150 |
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151 if (desc->mask_regs) { |
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152 for (i = 0; i < desc->nr_mask_regs; i++) { |
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153 struct intc_mask_reg *mr = desc->mask_regs + i; |
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154 |
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155 mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg); |
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156 if (mode == INTC_MODE_NONE) |
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157 continue; |
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158 |
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159 *modep = mode; |
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160 *datap = &mr->value; |
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161 *enums = mr->enum_ids; |
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162 *first = mr->reg_width - 1; |
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163 *width = 1; |
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164 return; |
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165 } |
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166 } |
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167 |
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168 if (desc->prio_regs) { |
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169 for (i = 0; i < desc->nr_prio_regs; i++) { |
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170 struct intc_prio_reg *pr = desc->prio_regs + i; |
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171 |
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172 mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg); |
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173 if (mode == INTC_MODE_NONE) |
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174 continue; |
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175 |
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176 *modep = mode | INTC_MODE_IS_PRIO; |
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177 *datap = &pr->value; |
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178 *enums = pr->enum_ids; |
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179 *first = (pr->reg_width / pr->field_width) - 1; |
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180 *width = pr->field_width; |
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181 return; |
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182 } |
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183 } |
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184 |
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185 assert(0); |
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186 } |
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187 |
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188 static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, |
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189 int enable, int is_group) |
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190 { |
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191 struct intc_source *source = desc->sources + id; |
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192 |
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193 if (!id) |
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194 return; |
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195 |
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196 if (!source->next_enum_id && (!source->enable_max || !source->vect)) { |
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197 #ifdef DEBUG_INTC_SOURCES |
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198 printf("sh_intc: reserved interrupt source %d modified\n", id); |
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199 #endif |
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200 return; |
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201 } |
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202 |
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203 if (source->vect) |
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204 sh_intc_toggle_source(source, enable ? 1 : -1, 0); |
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205 |
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206 #ifdef DEBUG_INTC |
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207 else { |
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208 printf("setting interrupt group %d to %d\n", id, !!enable); |
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209 } |
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210 #endif |
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211 |
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212 if ((is_group || !source->vect) && source->next_enum_id) { |
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213 sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1); |
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214 } |
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215 |
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216 #ifdef DEBUG_INTC |
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217 if (!source->vect) { |
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218 printf("setting interrupt group %d to %d - done\n", id, !!enable); |
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219 } |
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220 #endif |
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221 } |
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222 |
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223 static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset) |
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224 { |
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225 struct intc_desc *desc = opaque; |
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226 intc_enum *enum_ids = NULL; |
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227 unsigned int first = 0; |
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228 unsigned int width = 0; |
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229 unsigned int mode = 0; |
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230 unsigned long *valuep; |
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231 |
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232 #ifdef DEBUG_INTC |
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233 printf("sh_intc_read 0x%lx\n", (unsigned long) offset); |
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234 #endif |
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235 |
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236 sh_intc_locate(desc, (unsigned long)offset, &valuep, |
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237 &enum_ids, &first, &width, &mode); |
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238 return *valuep; |
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239 } |
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240 |
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241 static void sh_intc_write(void *opaque, target_phys_addr_t offset, |
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242 uint32_t value) |
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243 { |
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244 struct intc_desc *desc = opaque; |
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245 intc_enum *enum_ids = NULL; |
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246 unsigned int first = 0; |
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247 unsigned int width = 0; |
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248 unsigned int mode = 0; |
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249 unsigned int k; |
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250 unsigned long *valuep; |
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251 unsigned long mask; |
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252 |
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253 #ifdef DEBUG_INTC |
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254 printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value); |
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255 #endif |
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256 |
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257 sh_intc_locate(desc, (unsigned long)offset, &valuep, |
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258 &enum_ids, &first, &width, &mode); |
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259 |
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260 switch (mode) { |
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261 case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; |
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262 case INTC_MODE_DUAL_SET: value |= *valuep; break; |
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263 case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break; |
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264 default: assert(0); |
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265 } |
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266 |
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267 for (k = 0; k <= first; k++) { |
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268 mask = ((1 << width) - 1) << ((first - k) * width); |
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269 |
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270 if ((*valuep & mask) == (value & mask)) |
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271 continue; |
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272 #if 0 |
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273 printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", |
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274 k, first, enum_ids[k], (unsigned int)mask); |
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275 #endif |
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276 sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0); |
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277 } |
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278 |
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279 *valuep = value; |
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280 |
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281 #ifdef DEBUG_INTC |
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282 printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value); |
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283 #endif |
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284 } |
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285 |
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286 static CPUReadMemoryFunc *sh_intc_readfn[] = { |
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287 sh_intc_read, |
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288 sh_intc_read, |
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289 sh_intc_read |
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290 }; |
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291 |
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292 static CPUWriteMemoryFunc *sh_intc_writefn[] = { |
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293 sh_intc_write, |
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294 sh_intc_write, |
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295 sh_intc_write |
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296 }; |
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297 |
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298 struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id) |
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299 { |
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300 if (id) |
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301 return desc->sources + id; |
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302 |
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303 return NULL; |
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304 } |
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305 |
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306 static void sh_intc_register(struct intc_desc *desc, |
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307 unsigned long address) |
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308 { |
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309 if (address) { |
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310 cpu_register_physical_memory_offset(P4ADDR(address), 4, |
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311 desc->iomemtype, INTC_A7(address)); |
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312 cpu_register_physical_memory_offset(A7ADDR(address), 4, |
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313 desc->iomemtype, INTC_A7(address)); |
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314 } |
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315 } |
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316 |
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317 static void sh_intc_register_source(struct intc_desc *desc, |
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318 intc_enum source, |
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319 struct intc_group *groups, |
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320 int nr_groups) |
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321 { |
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322 unsigned int i, k; |
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323 struct intc_source *s; |
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324 |
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325 if (desc->mask_regs) { |
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326 for (i = 0; i < desc->nr_mask_regs; i++) { |
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327 struct intc_mask_reg *mr = desc->mask_regs + i; |
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328 |
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329 for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) { |
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330 if (mr->enum_ids[k] != source) |
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331 continue; |
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332 |
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333 s = sh_intc_source(desc, mr->enum_ids[k]); |
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334 if (s) |
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335 s->enable_max++; |
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336 } |
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337 } |
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338 } |
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339 |
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340 if (desc->prio_regs) { |
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341 for (i = 0; i < desc->nr_prio_regs; i++) { |
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342 struct intc_prio_reg *pr = desc->prio_regs + i; |
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343 |
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344 for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) { |
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345 if (pr->enum_ids[k] != source) |
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346 continue; |
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347 |
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348 s = sh_intc_source(desc, pr->enum_ids[k]); |
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349 if (s) |
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350 s->enable_max++; |
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351 } |
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352 } |
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353 } |
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354 |
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355 if (groups) { |
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356 for (i = 0; i < nr_groups; i++) { |
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357 struct intc_group *gr = groups + i; |
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358 |
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359 for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) { |
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360 if (gr->enum_ids[k] != source) |
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361 continue; |
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362 |
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363 s = sh_intc_source(desc, gr->enum_ids[k]); |
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364 if (s) |
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365 s->enable_max++; |
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366 } |
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367 } |
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368 } |
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369 |
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370 } |
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371 |
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372 void sh_intc_register_sources(struct intc_desc *desc, |
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373 struct intc_vect *vectors, |
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374 int nr_vectors, |
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375 struct intc_group *groups, |
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376 int nr_groups) |
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377 { |
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378 unsigned int i, k; |
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379 struct intc_source *s; |
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380 |
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381 for (i = 0; i < nr_vectors; i++) { |
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382 struct intc_vect *vect = vectors + i; |
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383 |
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384 sh_intc_register_source(desc, vect->enum_id, groups, nr_groups); |
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385 s = sh_intc_source(desc, vect->enum_id); |
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386 if (s) |
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387 s->vect = vect->vect; |
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388 |
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389 #ifdef DEBUG_INTC_SOURCES |
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390 printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n", |
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391 vect->enum_id, s->vect, s->enable_count, s->enable_max); |
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392 #endif |
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393 } |
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394 |
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395 if (groups) { |
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396 for (i = 0; i < nr_groups; i++) { |
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397 struct intc_group *gr = groups + i; |
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398 |
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399 s = sh_intc_source(desc, gr->enum_id); |
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400 s->next_enum_id = gr->enum_ids[0]; |
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401 |
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402 for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) { |
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403 if (!gr->enum_ids[k]) |
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404 continue; |
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405 |
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406 s = sh_intc_source(desc, gr->enum_ids[k - 1]); |
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407 s->next_enum_id = gr->enum_ids[k]; |
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408 } |
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409 |
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410 #ifdef DEBUG_INTC_SOURCES |
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411 printf("sh_intc: registered group %d (%d/%d)\n", |
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412 gr->enum_id, s->enable_count, s->enable_max); |
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413 #endif |
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414 } |
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415 } |
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416 } |
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417 |
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418 int sh_intc_init(struct intc_desc *desc, |
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419 int nr_sources, |
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420 struct intc_mask_reg *mask_regs, |
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421 int nr_mask_regs, |
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422 struct intc_prio_reg *prio_regs, |
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423 int nr_prio_regs) |
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424 { |
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425 unsigned int i; |
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426 |
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427 desc->pending = 0; |
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428 desc->nr_sources = nr_sources; |
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429 desc->mask_regs = mask_regs; |
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430 desc->nr_mask_regs = nr_mask_regs; |
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431 desc->prio_regs = prio_regs; |
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432 desc->nr_prio_regs = nr_prio_regs; |
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433 |
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434 i = sizeof(struct intc_source) * nr_sources; |
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435 desc->sources = malloc(i); |
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436 if (!desc->sources) |
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437 return -1; |
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438 |
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439 memset(desc->sources, 0, i); |
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440 for (i = 0; i < desc->nr_sources; i++) { |
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441 struct intc_source *source = desc->sources + i; |
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442 |
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443 source->parent = desc; |
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444 } |
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445 |
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446 desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources); |
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447 |
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448 desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn, |
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449 sh_intc_writefn, desc); |
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450 if (desc->mask_regs) { |
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451 for (i = 0; i < desc->nr_mask_regs; i++) { |
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452 struct intc_mask_reg *mr = desc->mask_regs + i; |
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453 |
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454 sh_intc_register(desc, mr->set_reg); |
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455 sh_intc_register(desc, mr->clr_reg); |
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456 } |
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457 } |
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458 |
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459 if (desc->prio_regs) { |
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460 for (i = 0; i < desc->nr_prio_regs; i++) { |
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461 struct intc_prio_reg *pr = desc->prio_regs + i; |
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462 |
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463 sh_intc_register(desc, pr->set_reg); |
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464 sh_intc_register(desc, pr->clr_reg); |
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465 } |
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466 } |
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467 |
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468 return 0; |
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469 } |
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470 |
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471 /* Assert level <n> IRL interrupt. |
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472 0:deassert. 1:lowest priority,... 15:highest priority. */ |
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473 void sh_intc_set_irl(void *opaque, int n, int level) |
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474 { |
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475 struct intc_source *s = opaque; |
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476 int i, irl = level ^ 15; |
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477 for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { |
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478 if (i == irl) |
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479 sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1); |
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480 else |
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481 if (s->asserted) |
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482 sh_intc_toggle_source(s, 0, -1); |
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483 } |
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484 } |