1 /*

     2  * SuperH on-chip PCIC emulation.

     3  *

     4  * Copyright (c) 2008 Takashi YOSHII

     5  *

     6  * Permission is hereby granted, free of charge, to any person obtaining a copy

     7  * of this software and associated documentation files (the "Software"), to deal

     8  * in the Software without restriction, including without limitation the rights

     9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    10  * copies of the Software, and to permit persons to whom the Software is

    11  * furnished to do so, subject to the following conditions:

    12  *

    13  * The above copyright notice and this permission notice shall be included in

    14  * all copies or substantial portions of the Software.

    15  *

    16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    22  * THE SOFTWARE.

    23  */

    24 #include "hw.h"

    25 #include "sh.h"

    26 #include "pci.h"

    27 #include "bswap.h"

    28 

    29 typedef struct {

    30     PCIBus *bus;

    31     PCIDevice *dev;

    32     uint32_t regbase;

    33     uint32_t iopbase;

    34     uint32_t membase;

    35     uint32_t par;

    36     uint32_t mbr;

    37     uint32_t iobr;

    38 } SHPCIC;

    39 

    40 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)

    41 {

    42     SHPCIC *pcic = p;

    43     switch(addr) {

    44     case 0 ... 0xfc:

    45         cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);

    46         break;

    47     case 0x1c0:

    48         pcic->par = val;

    49         break;

    50     case 0x1c4:

    51         pcic->mbr = val;

    52         break;

    53     case 0x1c8:

    54         pcic->iobr = val;

    55         break;

    56     case 0x220:

    57         pci_data_write(pcic->bus, pcic->par, val, 4);

    58         break;

    59     }

    60 }

    61 

    62 static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)

    63 {

    64     SHPCIC *pcic = p;

    65     switch(addr) {

    66     case 0 ... 0xfc:

    67         return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));

    68     case 0x1c0:

    69         return pcic->par;

    70     case 0x220:

    71         return pci_data_read(pcic->bus, pcic->par, 4);

    72     }

    73     return 0;

    74 }

    75 

    76 static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr,

    77                                uint32_t val, int size)

    78 {

    79     pci_data_write(pcic->bus, addr + pcic->mbr, val, size);

    80 }

    81 

    82 static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,

    83                                  int size)

    84 {

    85     return pci_data_read(pcic->bus, addr + pcic->mbr, size);

    86 }

    87 

    88 static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val)

    89 {

    90     sh_pci_data_write(p, addr, val, 1);

    91 }

    92 

    93 static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val)

    94 {

    95     sh_pci_data_write(p, addr, val, 2);

    96 }

    97 

    98 static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val)

    99 {

   100     sh_pci_data_write(p, addr, val, 4);

   101 }

   102 

   103 static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr)

   104 {

   105     return sh_pci_mem_read(p, addr, 1);

   106 }

   107 

   108 static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr)

   109 {

   110     return sh_pci_mem_read(p, addr, 2);

   111 }

   112 

   113 static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr)

   114 {

   115     return sh_pci_mem_read(p, addr, 4);

   116 }

   117 

   118 static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr)

   119 {

   120     return addr + pcic->iobr;

   121 }

   122 

   123 static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val)

   124 {

   125     cpu_outb(NULL, sh_pci_addr2port(p, addr), val);

   126 }

   127 

   128 static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val)

   129 {

   130     cpu_outw(NULL, sh_pci_addr2port(p, addr), val);

   131 }

   132 

   133 static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val)

   134 {

   135     cpu_outl(NULL, sh_pci_addr2port(p, addr), val);

   136 }

   137 

   138 static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr)

   139 {

   140     return cpu_inb(NULL, sh_pci_addr2port(p, addr));

   141 }

   142 

   143 static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr)

   144 {

   145     return cpu_inw(NULL, sh_pci_addr2port(p, addr));

   146 }

   147 

   148 static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr)

   149 {

   150     return cpu_inl(NULL, sh_pci_addr2port(p, addr));

   151 }

   152 

   153 typedef struct {

   154     CPUReadMemoryFunc *r[3];

   155     CPUWriteMemoryFunc *w[3];

   156 } MemOp;

   157 

   158 static MemOp sh_pci_reg = {

   159     { NULL, NULL, sh_pci_reg_read },

   160     { NULL, NULL, sh_pci_reg_write },

   161 };

   162 

   163 static MemOp sh_pci_mem = {

   164     { sh_pci_readb, sh_pci_readw, sh_pci_readl },

   165     { sh_pci_writeb, sh_pci_writew, sh_pci_writel },

   166 };

   167 

   168 static MemOp sh_pci_iop = {

   169     { sh_pci_inb, sh_pci_inw, sh_pci_inl },

   170     { sh_pci_outb, sh_pci_outw, sh_pci_outl },

   171 };

   172 

   173 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,

   174                             qemu_irq *pic, int devfn_min, int nirq)

   175 {

   176     SHPCIC *p;

   177     int mem, reg, iop;

   178 

   179     p = qemu_mallocz(sizeof(SHPCIC));

   180     p->bus = pci_register_bus(set_irq, map_irq, pic, devfn_min, nirq);

   181 

   182     p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),

   183                                  -1, NULL, NULL);

   184     p->regbase = 0x1e200000;

   185     p->iopbase = 0x1e240000;

   186     p->membase = 0xfd000000;

   187     reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);

   188     mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);

   189     iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);

   190     cpu_register_physical_memory(p->regbase, 0x224, reg);

   191     cpu_register_physical_memory(p->iopbase, 0x40000, iop);

   192     cpu_register_physical_memory(p->membase, 0x1000000, mem);

   193 

   194     p->dev->config[0x00] = 0x54; // HITACHI

   195     p->dev->config[0x01] = 0x10; //

   196     p->dev->config[0x02] = 0x0e; // SH7751R

   197     p->dev->config[0x03] = 0x35; //

   198     p->dev->config[0x04] = 0x80;

   199     p->dev->config[0x05] = 0x00;

   200     p->dev->config[0x06] = 0x90;

   201     p->dev->config[0x07] = 0x02;

   202 

   203     return p->bus;

   204 }