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1 /* |
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2 * QEMU Sparc SLAVIO serial port emulation |
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3 * |
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4 * Copyright (c) 2003-2005 Fabrice Bellard |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "sun4m.h" |
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26 #include "qemu-char.h" |
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27 #include "console.h" |
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28 |
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29 /* debug serial */ |
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30 //#define DEBUG_SERIAL |
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31 |
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32 /* debug keyboard */ |
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33 //#define DEBUG_KBD |
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34 |
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35 /* debug mouse */ |
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36 //#define DEBUG_MOUSE |
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37 |
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38 /* |
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39 * This is the serial port, mouse and keyboard part of chip STP2001 |
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40 * (Slave I/O), also produced as NCR89C105. See |
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41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt |
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42 * |
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43 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips, |
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44 * mouse and keyboard ports don't implement all functions and they are |
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45 * only asynchronous. There is no DMA. |
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46 * |
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47 */ |
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48 |
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49 /* |
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50 * Modifications: |
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51 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented |
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52 * serial mouse queue. |
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53 * Implemented serial mouse protocol. |
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54 */ |
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55 |
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56 #ifdef DEBUG_SERIAL |
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57 #define SER_DPRINTF(fmt, args...) \ |
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58 do { printf("SER: " fmt , ##args); } while (0) |
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59 #else |
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60 #define SER_DPRINTF(fmt, args...) |
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61 #endif |
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62 #ifdef DEBUG_KBD |
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63 #define KBD_DPRINTF(fmt, args...) \ |
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64 do { printf("KBD: " fmt , ##args); } while (0) |
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65 #else |
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66 #define KBD_DPRINTF(fmt, args...) |
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67 #endif |
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68 #ifdef DEBUG_MOUSE |
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69 #define MS_DPRINTF(fmt, args...) \ |
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70 do { printf("MSC: " fmt , ##args); } while (0) |
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71 #else |
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72 #define MS_DPRINTF(fmt, args...) |
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73 #endif |
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74 |
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75 typedef enum { |
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76 chn_a, chn_b, |
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77 } chn_id_t; |
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78 |
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79 #define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a') |
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80 |
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81 typedef enum { |
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82 ser, kbd, mouse, |
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83 } chn_type_t; |
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84 |
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85 #define SERIO_QUEUE_SIZE 256 |
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86 |
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87 typedef struct { |
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88 uint8_t data[SERIO_QUEUE_SIZE]; |
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89 int rptr, wptr, count; |
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90 } SERIOQueue; |
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91 |
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92 #define SERIAL_REGS 16 |
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93 typedef struct ChannelState { |
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94 qemu_irq irq; |
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95 uint32_t reg; |
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96 uint32_t rxint, txint, rxint_under_svc, txint_under_svc; |
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97 chn_id_t chn; // this channel, A (base+4) or B (base+0) |
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98 chn_type_t type; |
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99 struct ChannelState *otherchn; |
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100 uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS]; |
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101 SERIOQueue queue; |
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102 CharDriverState *chr; |
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103 int e0_mode, led_mode, caps_lock_mode, num_lock_mode; |
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104 int disabled; |
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105 } ChannelState; |
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106 |
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107 struct SerialState { |
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108 struct ChannelState chn[2]; |
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109 }; |
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110 |
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111 #define SERIAL_SIZE 8 |
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112 #define SERIAL_CTRL 0 |
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113 #define SERIAL_DATA 1 |
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114 |
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115 #define W_CMD 0 |
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116 #define CMD_PTR_MASK 0x07 |
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117 #define CMD_CMD_MASK 0x38 |
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118 #define CMD_HI 0x08 |
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119 #define CMD_CLR_TXINT 0x28 |
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120 #define CMD_CLR_IUS 0x38 |
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121 #define W_INTR 1 |
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122 #define INTR_INTALL 0x01 |
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123 #define INTR_TXINT 0x02 |
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124 #define INTR_RXMODEMSK 0x18 |
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125 #define INTR_RXINT1ST 0x08 |
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126 #define INTR_RXINTALL 0x10 |
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127 #define W_IVEC 2 |
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128 #define W_RXCTRL 3 |
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129 #define RXCTRL_RXEN 0x01 |
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130 #define W_TXCTRL1 4 |
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131 #define TXCTRL1_PAREN 0x01 |
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132 #define TXCTRL1_PAREV 0x02 |
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133 #define TXCTRL1_1STOP 0x04 |
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134 #define TXCTRL1_1HSTOP 0x08 |
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135 #define TXCTRL1_2STOP 0x0c |
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136 #define TXCTRL1_STPMSK 0x0c |
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137 #define TXCTRL1_CLK1X 0x00 |
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138 #define TXCTRL1_CLK16X 0x40 |
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139 #define TXCTRL1_CLK32X 0x80 |
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140 #define TXCTRL1_CLK64X 0xc0 |
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141 #define TXCTRL1_CLKMSK 0xc0 |
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142 #define W_TXCTRL2 5 |
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143 #define TXCTRL2_TXEN 0x08 |
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144 #define TXCTRL2_BITMSK 0x60 |
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145 #define TXCTRL2_5BITS 0x00 |
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146 #define TXCTRL2_7BITS 0x20 |
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147 #define TXCTRL2_6BITS 0x40 |
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148 #define TXCTRL2_8BITS 0x60 |
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149 #define W_SYNC1 6 |
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150 #define W_SYNC2 7 |
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151 #define W_TXBUF 8 |
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152 #define W_MINTR 9 |
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153 #define MINTR_STATUSHI 0x10 |
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154 #define MINTR_RST_MASK 0xc0 |
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155 #define MINTR_RST_B 0x40 |
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156 #define MINTR_RST_A 0x80 |
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157 #define MINTR_RST_ALL 0xc0 |
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158 #define W_MISC1 10 |
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159 #define W_CLOCK 11 |
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160 #define CLOCK_TRXC 0x08 |
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161 #define W_BRGLO 12 |
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162 #define W_BRGHI 13 |
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163 #define W_MISC2 14 |
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164 #define MISC2_PLLDIS 0x30 |
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165 #define W_EXTINT 15 |
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166 #define EXTINT_DCD 0x08 |
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167 #define EXTINT_SYNCINT 0x10 |
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168 #define EXTINT_CTSINT 0x20 |
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169 #define EXTINT_TXUNDRN 0x40 |
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170 #define EXTINT_BRKINT 0x80 |
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171 |
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172 #define R_STATUS 0 |
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173 #define STATUS_RXAV 0x01 |
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174 #define STATUS_ZERO 0x02 |
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175 #define STATUS_TXEMPTY 0x04 |
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176 #define STATUS_DCD 0x08 |
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177 #define STATUS_SYNC 0x10 |
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178 #define STATUS_CTS 0x20 |
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179 #define STATUS_TXUNDRN 0x40 |
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180 #define STATUS_BRK 0x80 |
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181 #define R_SPEC 1 |
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182 #define SPEC_ALLSENT 0x01 |
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183 #define SPEC_BITS8 0x06 |
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184 #define R_IVEC 2 |
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185 #define IVEC_TXINTB 0x00 |
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186 #define IVEC_LONOINT 0x06 |
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187 #define IVEC_LORXINTA 0x0c |
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188 #define IVEC_LORXINTB 0x04 |
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189 #define IVEC_LOTXINTA 0x08 |
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190 #define IVEC_HINOINT 0x60 |
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191 #define IVEC_HIRXINTA 0x30 |
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192 #define IVEC_HIRXINTB 0x20 |
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193 #define IVEC_HITXINTA 0x10 |
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194 #define R_INTR 3 |
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195 #define INTR_EXTINTB 0x01 |
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196 #define INTR_TXINTB 0x02 |
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197 #define INTR_RXINTB 0x04 |
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198 #define INTR_EXTINTA 0x08 |
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199 #define INTR_TXINTA 0x10 |
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200 #define INTR_RXINTA 0x20 |
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201 #define R_IPEN 4 |
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202 #define R_TXCTRL1 5 |
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203 #define R_TXCTRL2 6 |
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204 #define R_BC 7 |
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205 #define R_RXBUF 8 |
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206 #define R_RXCTRL 9 |
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207 #define R_MISC 10 |
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208 #define R_MISC1 11 |
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209 #define R_BRGLO 12 |
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210 #define R_BRGHI 13 |
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211 #define R_MISC1I 14 |
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212 #define R_EXTINT 15 |
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213 |
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214 static void handle_kbd_command(ChannelState *s, int val); |
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215 static int serial_can_receive(void *opaque); |
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216 static void serial_receive_byte(ChannelState *s, int ch); |
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217 |
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218 static void clear_queue(void *opaque) |
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219 { |
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220 ChannelState *s = opaque; |
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221 SERIOQueue *q = &s->queue; |
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222 q->rptr = q->wptr = q->count = 0; |
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223 } |
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224 |
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225 static void put_queue(void *opaque, int b) |
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226 { |
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227 ChannelState *s = opaque; |
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228 SERIOQueue *q = &s->queue; |
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229 |
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230 SER_DPRINTF("channel %c put: 0x%02x\n", CHN_C(s), b); |
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231 if (q->count >= SERIO_QUEUE_SIZE) |
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232 return; |
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233 q->data[q->wptr] = b; |
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234 if (++q->wptr == SERIO_QUEUE_SIZE) |
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235 q->wptr = 0; |
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236 q->count++; |
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237 serial_receive_byte(s, 0); |
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238 } |
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239 |
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240 static uint32_t get_queue(void *opaque) |
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241 { |
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242 ChannelState *s = opaque; |
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243 SERIOQueue *q = &s->queue; |
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244 int val; |
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245 |
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246 if (q->count == 0) { |
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247 return 0; |
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248 } else { |
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249 val = q->data[q->rptr]; |
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250 if (++q->rptr == SERIO_QUEUE_SIZE) |
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251 q->rptr = 0; |
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252 q->count--; |
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253 } |
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254 SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val); |
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255 if (q->count > 0) |
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256 serial_receive_byte(s, 0); |
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257 return val; |
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258 } |
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259 |
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260 static int slavio_serial_update_irq_chn(ChannelState *s) |
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261 { |
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262 if ((((s->wregs[W_INTR] & INTR_TXINT) && s->txint == 1) || |
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263 // tx ints enabled, pending |
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264 ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) || |
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265 ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) && |
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266 s->rxint == 1) || // rx ints enabled, pending |
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267 ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && |
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268 (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p |
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269 return 1; |
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270 } |
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271 return 0; |
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272 } |
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273 |
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274 static void slavio_serial_update_irq(ChannelState *s) |
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275 { |
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276 int irq; |
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277 |
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278 irq = slavio_serial_update_irq_chn(s); |
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279 irq |= slavio_serial_update_irq_chn(s->otherchn); |
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280 |
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281 SER_DPRINTF("IRQ = %d\n", irq); |
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282 qemu_set_irq(s->irq, irq); |
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283 } |
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284 |
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285 static void slavio_serial_reset_chn(ChannelState *s) |
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286 { |
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287 int i; |
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288 |
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289 s->reg = 0; |
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290 for (i = 0; i < SERIAL_SIZE; i++) { |
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291 s->rregs[i] = 0; |
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292 s->wregs[i] = 0; |
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293 } |
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294 s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity |
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295 s->wregs[W_MINTR] = MINTR_RST_ALL; |
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296 s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC |
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297 s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled |
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298 s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | |
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299 EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts |
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300 if (s->disabled) |
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301 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | |
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302 STATUS_CTS | STATUS_TXUNDRN; |
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303 else |
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304 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; |
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305 s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; |
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306 |
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307 s->rx = s->tx = 0; |
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308 s->rxint = s->txint = 0; |
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309 s->rxint_under_svc = s->txint_under_svc = 0; |
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310 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; |
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311 clear_queue(s); |
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312 } |
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313 |
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314 static void slavio_serial_reset(void *opaque) |
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315 { |
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316 SerialState *s = opaque; |
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317 slavio_serial_reset_chn(&s->chn[0]); |
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318 slavio_serial_reset_chn(&s->chn[1]); |
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319 } |
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320 |
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321 static inline void set_rxint(ChannelState *s) |
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322 { |
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323 s->rxint = 1; |
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324 if (!s->txint_under_svc) { |
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325 s->rxint_under_svc = 1; |
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326 if (s->chn == chn_a) { |
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327 if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
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328 s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA; |
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329 else |
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330 s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA; |
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331 } else { |
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332 if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
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333 s->rregs[R_IVEC] = IVEC_HIRXINTB; |
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334 else |
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335 s->rregs[R_IVEC] = IVEC_LORXINTB; |
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336 } |
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337 } |
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338 if (s->chn == chn_a) |
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339 s->rregs[R_INTR] |= INTR_RXINTA; |
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340 else |
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341 s->otherchn->rregs[R_INTR] |= INTR_RXINTB; |
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342 slavio_serial_update_irq(s); |
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343 } |
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344 |
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345 static inline void set_txint(ChannelState *s) |
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346 { |
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347 s->txint = 1; |
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348 if (!s->rxint_under_svc) { |
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349 s->txint_under_svc = 1; |
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350 if (s->chn == chn_a) { |
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351 if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
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352 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; |
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353 else |
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354 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; |
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355 } else { |
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356 s->rregs[R_IVEC] = IVEC_TXINTB; |
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357 } |
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358 } |
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359 if (s->chn == chn_a) |
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360 s->rregs[R_INTR] |= INTR_TXINTA; |
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361 else |
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362 s->otherchn->rregs[R_INTR] |= INTR_TXINTB; |
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363 slavio_serial_update_irq(s); |
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364 } |
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365 |
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366 static inline void clr_rxint(ChannelState *s) |
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367 { |
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368 s->rxint = 0; |
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369 s->rxint_under_svc = 0; |
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370 if (s->chn == chn_a) { |
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371 if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
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372 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; |
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373 else |
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374 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; |
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375 s->rregs[R_INTR] &= ~INTR_RXINTA; |
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376 } else { |
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377 if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
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378 s->rregs[R_IVEC] = IVEC_HINOINT; |
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379 else |
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380 s->rregs[R_IVEC] = IVEC_LONOINT; |
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381 s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB; |
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382 } |
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383 if (s->txint) |
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384 set_txint(s); |
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385 slavio_serial_update_irq(s); |
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386 } |
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387 |
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388 static inline void clr_txint(ChannelState *s) |
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389 { |
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390 s->txint = 0; |
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391 s->txint_under_svc = 0; |
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392 if (s->chn == chn_a) { |
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393 if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
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394 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; |
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395 else |
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396 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; |
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397 s->rregs[R_INTR] &= ~INTR_TXINTA; |
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398 } else { |
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399 if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
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400 s->rregs[R_IVEC] = IVEC_HINOINT; |
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401 else |
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402 s->rregs[R_IVEC] = IVEC_LONOINT; |
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403 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; |
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404 } |
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405 if (s->rxint) |
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406 set_rxint(s); |
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407 slavio_serial_update_irq(s); |
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408 } |
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409 |
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410 static void slavio_serial_update_parameters(ChannelState *s) |
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411 { |
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412 int speed, parity, data_bits, stop_bits; |
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413 QEMUSerialSetParams ssp; |
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414 |
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415 if (!s->chr || s->type != ser) |
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416 return; |
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417 |
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418 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { |
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419 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) |
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420 parity = 'E'; |
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421 else |
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422 parity = 'O'; |
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423 } else { |
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424 parity = 'N'; |
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425 } |
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426 if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP) |
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427 stop_bits = 2; |
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428 else |
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429 stop_bits = 1; |
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430 switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { |
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431 case TXCTRL2_5BITS: |
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432 data_bits = 5; |
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433 break; |
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434 case TXCTRL2_7BITS: |
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435 data_bits = 7; |
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436 break; |
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437 case TXCTRL2_6BITS: |
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438 data_bits = 6; |
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439 break; |
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440 default: |
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441 case TXCTRL2_8BITS: |
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442 data_bits = 8; |
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443 break; |
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444 } |
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445 speed = 2457600 / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2); |
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446 switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) { |
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447 case TXCTRL1_CLK1X: |
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448 break; |
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449 case TXCTRL1_CLK16X: |
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450 speed /= 16; |
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451 break; |
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452 case TXCTRL1_CLK32X: |
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453 speed /= 32; |
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454 break; |
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455 default: |
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456 case TXCTRL1_CLK64X: |
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457 speed /= 64; |
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458 break; |
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459 } |
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460 ssp.speed = speed; |
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461 ssp.parity = parity; |
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462 ssp.data_bits = data_bits; |
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463 ssp.stop_bits = stop_bits; |
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464 SER_DPRINTF("channel %c: speed=%d parity=%c data=%d stop=%d\n", CHN_C(s), |
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465 speed, parity, data_bits, stop_bits); |
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466 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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467 } |
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468 |
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469 static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, |
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470 uint32_t val) |
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471 { |
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472 SerialState *serial = opaque; |
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473 ChannelState *s; |
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474 uint32_t saddr; |
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475 int newreg, channel; |
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476 |
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477 val &= 0xff; |
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478 saddr = (addr & 3) >> 1; |
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479 channel = addr >> 2; |
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480 s = &serial->chn[channel]; |
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481 switch (saddr) { |
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482 case SERIAL_CTRL: |
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483 SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, |
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484 val & 0xff); |
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485 newreg = 0; |
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486 switch (s->reg) { |
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487 case W_CMD: |
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488 newreg = val & CMD_PTR_MASK; |
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489 val &= CMD_CMD_MASK; |
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490 switch (val) { |
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491 case CMD_HI: |
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492 newreg |= CMD_HI; |
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493 break; |
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494 case CMD_CLR_TXINT: |
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495 clr_txint(s); |
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496 break; |
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497 case CMD_CLR_IUS: |
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498 if (s->rxint_under_svc) |
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499 clr_rxint(s); |
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500 else if (s->txint_under_svc) |
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501 clr_txint(s); |
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502 break; |
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503 default: |
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504 break; |
|
505 } |
|
506 break; |
|
507 case W_INTR ... W_RXCTRL: |
|
508 case W_SYNC1 ... W_TXBUF: |
|
509 case W_MISC1 ... W_CLOCK: |
|
510 case W_MISC2 ... W_EXTINT: |
|
511 s->wregs[s->reg] = val; |
|
512 break; |
|
513 case W_TXCTRL1: |
|
514 case W_TXCTRL2: |
|
515 s->wregs[s->reg] = val; |
|
516 slavio_serial_update_parameters(s); |
|
517 break; |
|
518 case W_BRGLO: |
|
519 case W_BRGHI: |
|
520 s->wregs[s->reg] = val; |
|
521 s->rregs[s->reg] = val; |
|
522 slavio_serial_update_parameters(s); |
|
523 break; |
|
524 case W_MINTR: |
|
525 switch (val & MINTR_RST_MASK) { |
|
526 case 0: |
|
527 default: |
|
528 break; |
|
529 case MINTR_RST_B: |
|
530 slavio_serial_reset_chn(&serial->chn[0]); |
|
531 return; |
|
532 case MINTR_RST_A: |
|
533 slavio_serial_reset_chn(&serial->chn[1]); |
|
534 return; |
|
535 case MINTR_RST_ALL: |
|
536 slavio_serial_reset(serial); |
|
537 return; |
|
538 } |
|
539 break; |
|
540 default: |
|
541 break; |
|
542 } |
|
543 if (s->reg == 0) |
|
544 s->reg = newreg; |
|
545 else |
|
546 s->reg = 0; |
|
547 break; |
|
548 case SERIAL_DATA: |
|
549 SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val); |
|
550 s->tx = val; |
|
551 if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled |
|
552 if (s->chr) |
|
553 qemu_chr_write(s->chr, &s->tx, 1); |
|
554 else if (s->type == kbd && !s->disabled) { |
|
555 handle_kbd_command(s, val); |
|
556 } |
|
557 } |
|
558 s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty |
|
559 s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent |
|
560 set_txint(s); |
|
561 break; |
|
562 default: |
|
563 break; |
|
564 } |
|
565 } |
|
566 |
|
567 static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr) |
|
568 { |
|
569 SerialState *serial = opaque; |
|
570 ChannelState *s; |
|
571 uint32_t saddr; |
|
572 uint32_t ret; |
|
573 int channel; |
|
574 |
|
575 saddr = (addr & 3) >> 1; |
|
576 channel = addr >> 2; |
|
577 s = &serial->chn[channel]; |
|
578 switch (saddr) { |
|
579 case SERIAL_CTRL: |
|
580 SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, |
|
581 s->rregs[s->reg]); |
|
582 ret = s->rregs[s->reg]; |
|
583 s->reg = 0; |
|
584 return ret; |
|
585 case SERIAL_DATA: |
|
586 s->rregs[R_STATUS] &= ~STATUS_RXAV; |
|
587 clr_rxint(s); |
|
588 if (s->type == kbd || s->type == mouse) |
|
589 ret = get_queue(s); |
|
590 else |
|
591 ret = s->rx; |
|
592 SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret); |
|
593 if (s->chr) |
|
594 qemu_chr_accept_input(s->chr); |
|
595 return ret; |
|
596 default: |
|
597 break; |
|
598 } |
|
599 return 0; |
|
600 } |
|
601 |
|
602 static int serial_can_receive(void *opaque) |
|
603 { |
|
604 ChannelState *s = opaque; |
|
605 int ret; |
|
606 |
|
607 if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled |
|
608 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) |
|
609 // char already available |
|
610 ret = 0; |
|
611 else |
|
612 ret = 1; |
|
613 return ret; |
|
614 } |
|
615 |
|
616 static void serial_receive_byte(ChannelState *s, int ch) |
|
617 { |
|
618 SER_DPRINTF("channel %c put ch %d\n", CHN_C(s), ch); |
|
619 s->rregs[R_STATUS] |= STATUS_RXAV; |
|
620 s->rx = ch; |
|
621 set_rxint(s); |
|
622 } |
|
623 |
|
624 static void serial_receive_break(ChannelState *s) |
|
625 { |
|
626 s->rregs[R_STATUS] |= STATUS_BRK; |
|
627 slavio_serial_update_irq(s); |
|
628 } |
|
629 |
|
630 static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
|
631 { |
|
632 ChannelState *s = opaque; |
|
633 serial_receive_byte(s, buf[0]); |
|
634 } |
|
635 |
|
636 static void serial_event(void *opaque, int event) |
|
637 { |
|
638 ChannelState *s = opaque; |
|
639 if (event == CHR_EVENT_BREAK) |
|
640 serial_receive_break(s); |
|
641 } |
|
642 |
|
643 static CPUReadMemoryFunc *slavio_serial_mem_read[3] = { |
|
644 slavio_serial_mem_readb, |
|
645 NULL, |
|
646 NULL, |
|
647 }; |
|
648 |
|
649 static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = { |
|
650 slavio_serial_mem_writeb, |
|
651 NULL, |
|
652 NULL, |
|
653 }; |
|
654 |
|
655 static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s) |
|
656 { |
|
657 uint32_t tmp = 0; |
|
658 |
|
659 qemu_put_be32s(f, &tmp); /* unused, was IRQ. */ |
|
660 qemu_put_be32s(f, &s->reg); |
|
661 qemu_put_be32s(f, &s->rxint); |
|
662 qemu_put_be32s(f, &s->txint); |
|
663 qemu_put_be32s(f, &s->rxint_under_svc); |
|
664 qemu_put_be32s(f, &s->txint_under_svc); |
|
665 qemu_put_8s(f, &s->rx); |
|
666 qemu_put_8s(f, &s->tx); |
|
667 qemu_put_buffer(f, s->wregs, SERIAL_REGS); |
|
668 qemu_put_buffer(f, s->rregs, SERIAL_REGS); |
|
669 } |
|
670 |
|
671 static void slavio_serial_save(QEMUFile *f, void *opaque) |
|
672 { |
|
673 SerialState *s = opaque; |
|
674 |
|
675 slavio_serial_save_chn(f, &s->chn[0]); |
|
676 slavio_serial_save_chn(f, &s->chn[1]); |
|
677 } |
|
678 |
|
679 static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id) |
|
680 { |
|
681 uint32_t tmp; |
|
682 |
|
683 if (version_id > 2) |
|
684 return -EINVAL; |
|
685 |
|
686 qemu_get_be32s(f, &tmp); /* unused */ |
|
687 qemu_get_be32s(f, &s->reg); |
|
688 qemu_get_be32s(f, &s->rxint); |
|
689 qemu_get_be32s(f, &s->txint); |
|
690 if (version_id >= 2) { |
|
691 qemu_get_be32s(f, &s->rxint_under_svc); |
|
692 qemu_get_be32s(f, &s->txint_under_svc); |
|
693 } |
|
694 qemu_get_8s(f, &s->rx); |
|
695 qemu_get_8s(f, &s->tx); |
|
696 qemu_get_buffer(f, s->wregs, SERIAL_REGS); |
|
697 qemu_get_buffer(f, s->rregs, SERIAL_REGS); |
|
698 return 0; |
|
699 } |
|
700 |
|
701 static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id) |
|
702 { |
|
703 SerialState *s = opaque; |
|
704 int ret; |
|
705 |
|
706 ret = slavio_serial_load_chn(f, &s->chn[0], version_id); |
|
707 if (ret != 0) |
|
708 return ret; |
|
709 ret = slavio_serial_load_chn(f, &s->chn[1], version_id); |
|
710 return ret; |
|
711 |
|
712 } |
|
713 |
|
714 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, |
|
715 CharDriverState *chr1, CharDriverState *chr2) |
|
716 { |
|
717 int slavio_serial_io_memory, i; |
|
718 SerialState *s; |
|
719 |
|
720 s = qemu_mallocz(sizeof(SerialState)); |
|
721 if (!s) |
|
722 return NULL; |
|
723 |
|
724 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, |
|
725 slavio_serial_mem_write, |
|
726 s); |
|
727 cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory); |
|
728 |
|
729 s->chn[0].chr = chr1; |
|
730 s->chn[1].chr = chr2; |
|
731 s->chn[0].disabled = 0; |
|
732 s->chn[1].disabled = 0; |
|
733 |
|
734 for (i = 0; i < 2; i++) { |
|
735 s->chn[i].irq = irq; |
|
736 s->chn[i].chn = 1 - i; |
|
737 s->chn[i].type = ser; |
|
738 if (s->chn[i].chr) { |
|
739 qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, |
|
740 serial_receive1, serial_event, &s->chn[i]); |
|
741 } |
|
742 } |
|
743 s->chn[0].otherchn = &s->chn[1]; |
|
744 s->chn[1].otherchn = &s->chn[0]; |
|
745 register_savevm("slavio_serial", base, 2, slavio_serial_save, |
|
746 slavio_serial_load, s); |
|
747 qemu_register_reset(slavio_serial_reset, s); |
|
748 slavio_serial_reset(s); |
|
749 return s; |
|
750 } |
|
751 |
|
752 static const uint8_t keycodes[128] = { |
|
753 127, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 53, |
|
754 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 89, 76, 77, 78, |
|
755 79, 80, 81, 82, 83, 84, 85, 86, 87, 42, 99, 88, 100, 101, 102, 103, |
|
756 104, 105, 106, 107, 108, 109, 110, 47, 19, 121, 119, 5, 6, 8, 10, 12, |
|
757 14, 16, 17, 18, 7, 98, 23, 68, 69, 70, 71, 91, 92, 93, 125, 112, |
|
758 113, 114, 94, 50, 0, 0, 124, 9, 11, 0, 0, 0, 0, 0, 0, 0, |
|
759 90, 0, 46, 22, 13, 111, 52, 20, 96, 24, 28, 74, 27, 123, 44, 66, |
|
760 0, 45, 2, 4, 48, 0, 0, 21, 0, 0, 0, 0, 0, 120, 122, 67, |
|
761 }; |
|
762 |
|
763 static const uint8_t e0_keycodes[128] = { |
|
764 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
|
765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 90, 76, 0, 0, |
|
766 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
|
767 0, 0, 0, 0, 0, 109, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, |
|
768 0, 0, 0, 0, 0, 0, 0, 68, 69, 70, 0, 91, 0, 93, 0, 112, |
|
769 113, 114, 94, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
|
770 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
|
771 1, 3, 25, 26, 49, 52, 72, 73, 97, 99, 111, 118, 120, 122, 67, 0, |
|
772 }; |
|
773 |
|
774 static void sunkbd_event(void *opaque, int ch) |
|
775 { |
|
776 ChannelState *s = opaque; |
|
777 int release = ch & 0x80; |
|
778 |
|
779 KBD_DPRINTF("Untranslated keycode %2.2x (%s)\n", ch, release? "release" : |
|
780 "press"); |
|
781 switch (ch) { |
|
782 case 58: // Caps lock press |
|
783 s->caps_lock_mode ^= 1; |
|
784 if (s->caps_lock_mode == 2) |
|
785 return; // Drop second press |
|
786 break; |
|
787 case 69: // Num lock press |
|
788 s->num_lock_mode ^= 1; |
|
789 if (s->num_lock_mode == 2) |
|
790 return; // Drop second press |
|
791 break; |
|
792 case 186: // Caps lock release |
|
793 s->caps_lock_mode ^= 2; |
|
794 if (s->caps_lock_mode == 3) |
|
795 return; // Drop first release |
|
796 break; |
|
797 case 197: // Num lock release |
|
798 s->num_lock_mode ^= 2; |
|
799 if (s->num_lock_mode == 3) |
|
800 return; // Drop first release |
|
801 break; |
|
802 case 0xe0: |
|
803 s->e0_mode = 1; |
|
804 return; |
|
805 default: |
|
806 break; |
|
807 } |
|
808 if (s->e0_mode) { |
|
809 s->e0_mode = 0; |
|
810 ch = e0_keycodes[ch & 0x7f]; |
|
811 } else { |
|
812 ch = keycodes[ch & 0x7f]; |
|
813 } |
|
814 KBD_DPRINTF("Translated keycode %2.2x\n", ch); |
|
815 put_queue(s, ch | release); |
|
816 } |
|
817 |
|
818 static void handle_kbd_command(ChannelState *s, int val) |
|
819 { |
|
820 KBD_DPRINTF("Command %d\n", val); |
|
821 if (s->led_mode) { // Ignore led byte |
|
822 s->led_mode = 0; |
|
823 return; |
|
824 } |
|
825 switch (val) { |
|
826 case 1: // Reset, return type code |
|
827 clear_queue(s); |
|
828 put_queue(s, 0xff); |
|
829 put_queue(s, 4); // Type 4 |
|
830 put_queue(s, 0x7f); |
|
831 break; |
|
832 case 0xe: // Set leds |
|
833 s->led_mode = 1; |
|
834 break; |
|
835 case 7: // Query layout |
|
836 case 0xf: |
|
837 clear_queue(s); |
|
838 put_queue(s, 0xfe); |
|
839 put_queue(s, 0); // XXX, layout? |
|
840 break; |
|
841 default: |
|
842 break; |
|
843 } |
|
844 } |
|
845 |
|
846 static void sunmouse_event(void *opaque, |
|
847 int dx, int dy, int dz, int buttons_state) |
|
848 { |
|
849 ChannelState *s = opaque; |
|
850 int ch; |
|
851 |
|
852 MS_DPRINTF("dx=%d dy=%d buttons=%01x\n", dx, dy, buttons_state); |
|
853 |
|
854 ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */ |
|
855 |
|
856 if (buttons_state & MOUSE_EVENT_LBUTTON) |
|
857 ch ^= 0x4; |
|
858 if (buttons_state & MOUSE_EVENT_MBUTTON) |
|
859 ch ^= 0x2; |
|
860 if (buttons_state & MOUSE_EVENT_RBUTTON) |
|
861 ch ^= 0x1; |
|
862 |
|
863 put_queue(s, ch); |
|
864 |
|
865 ch = dx; |
|
866 |
|
867 if (ch > 127) |
|
868 ch=127; |
|
869 else if (ch < -127) |
|
870 ch=-127; |
|
871 |
|
872 put_queue(s, ch & 0xff); |
|
873 |
|
874 ch = -dy; |
|
875 |
|
876 if (ch > 127) |
|
877 ch=127; |
|
878 else if (ch < -127) |
|
879 ch=-127; |
|
880 |
|
881 put_queue(s, ch & 0xff); |
|
882 |
|
883 // MSC protocol specify two extra motion bytes |
|
884 |
|
885 put_queue(s, 0); |
|
886 put_queue(s, 0); |
|
887 } |
|
888 |
|
889 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq, |
|
890 int disabled) |
|
891 { |
|
892 int slavio_serial_io_memory, i; |
|
893 SerialState *s; |
|
894 |
|
895 s = qemu_mallocz(sizeof(SerialState)); |
|
896 if (!s) |
|
897 return; |
|
898 for (i = 0; i < 2; i++) { |
|
899 s->chn[i].irq = irq; |
|
900 s->chn[i].chn = 1 - i; |
|
901 s->chn[i].chr = NULL; |
|
902 } |
|
903 s->chn[0].otherchn = &s->chn[1]; |
|
904 s->chn[1].otherchn = &s->chn[0]; |
|
905 s->chn[0].type = mouse; |
|
906 s->chn[1].type = kbd; |
|
907 s->chn[0].disabled = disabled; |
|
908 s->chn[1].disabled = disabled; |
|
909 |
|
910 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, |
|
911 slavio_serial_mem_write, |
|
912 s); |
|
913 cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory); |
|
914 |
|
915 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, |
|
916 "QEMU Sun Mouse"); |
|
917 qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]); |
|
918 register_savevm("slavio_serial_mouse", base, 2, slavio_serial_save, |
|
919 slavio_serial_load, s); |
|
920 qemu_register_reset(slavio_serial_reset, s); |
|
921 slavio_serial_reset(s); |
|
922 } |