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1 /* |
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2 * SMSC 91C111 Ethernet interface emulation |
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3 * |
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4 * Copyright (c) 2005 CodeSourcery, LLC. |
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5 * Written by Paul Brook |
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6 * |
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7 * This code is licenced under the GPL |
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8 */ |
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9 |
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10 #include "hw.h" |
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11 #include "net.h" |
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12 #include "devices.h" |
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13 /* For crc32 */ |
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14 #include <zlib.h> |
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15 |
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16 /* Number of 2k memory pages available. */ |
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17 #define NUM_PACKETS 4 |
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18 |
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19 typedef struct { |
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20 VLANClientState *vc; |
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21 uint16_t tcr; |
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22 uint16_t rcr; |
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23 uint16_t cr; |
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24 uint16_t ctr; |
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25 uint16_t gpr; |
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26 uint16_t ptr; |
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27 uint16_t ercv; |
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28 qemu_irq irq; |
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29 int bank; |
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30 int packet_num; |
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31 int tx_alloc; |
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32 /* Bitmask of allocated packets. */ |
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33 int allocated; |
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34 int tx_fifo_len; |
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35 int tx_fifo[NUM_PACKETS]; |
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36 int rx_fifo_len; |
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37 int rx_fifo[NUM_PACKETS]; |
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38 int tx_fifo_done_len; |
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39 int tx_fifo_done[NUM_PACKETS]; |
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40 /* Packet buffer memory. */ |
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41 uint8_t data[NUM_PACKETS][2048]; |
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42 uint8_t int_level; |
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43 uint8_t int_mask; |
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44 uint8_t macaddr[6]; |
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45 } smc91c111_state; |
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46 |
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47 #define RCR_SOFT_RST 0x8000 |
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48 #define RCR_STRIP_CRC 0x0200 |
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49 #define RCR_RXEN 0x0100 |
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50 |
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51 #define TCR_EPH_LOOP 0x2000 |
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52 #define TCR_NOCRC 0x0100 |
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53 #define TCR_PAD_EN 0x0080 |
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54 #define TCR_FORCOL 0x0004 |
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55 #define TCR_LOOP 0x0002 |
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56 #define TCR_TXEN 0x0001 |
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57 |
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58 #define INT_MD 0x80 |
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59 #define INT_ERCV 0x40 |
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60 #define INT_EPH 0x20 |
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61 #define INT_RX_OVRN 0x10 |
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62 #define INT_ALLOC 0x08 |
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63 #define INT_TX_EMPTY 0x04 |
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64 #define INT_TX 0x02 |
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65 #define INT_RCV 0x01 |
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66 |
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67 #define CTR_AUTO_RELEASE 0x0800 |
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68 #define CTR_RELOAD 0x0002 |
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69 #define CTR_STORE 0x0001 |
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70 |
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71 #define RS_ALGNERR 0x8000 |
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72 #define RS_BRODCAST 0x4000 |
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73 #define RS_BADCRC 0x2000 |
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74 #define RS_ODDFRAME 0x1000 |
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75 #define RS_TOOLONG 0x0800 |
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76 #define RS_TOOSHORT 0x0400 |
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77 #define RS_MULTICAST 0x0001 |
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78 |
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79 /* Update interrupt status. */ |
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80 static void smc91c111_update(smc91c111_state *s) |
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81 { |
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82 int level; |
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83 |
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84 if (s->tx_fifo_len == 0) |
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85 s->int_level |= INT_TX_EMPTY; |
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86 if (s->tx_fifo_done_len != 0) |
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87 s->int_level |= INT_TX; |
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88 level = (s->int_level & s->int_mask) != 0; |
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89 qemu_set_irq(s->irq, level); |
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90 } |
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91 |
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92 /* Try to allocate a packet. Returns 0x80 on failure. */ |
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93 static int smc91c111_allocate_packet(smc91c111_state *s) |
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94 { |
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95 int i; |
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96 if (s->allocated == (1 << NUM_PACKETS) - 1) { |
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97 return 0x80; |
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98 } |
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99 |
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100 for (i = 0; i < NUM_PACKETS; i++) { |
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101 if ((s->allocated & (1 << i)) == 0) |
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102 break; |
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103 } |
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104 s->allocated |= 1 << i; |
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105 return i; |
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106 } |
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107 |
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108 |
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109 /* Process a pending TX allocate. */ |
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110 static void smc91c111_tx_alloc(smc91c111_state *s) |
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111 { |
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112 s->tx_alloc = smc91c111_allocate_packet(s); |
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113 if (s->tx_alloc == 0x80) |
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114 return; |
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115 s->int_level |= INT_ALLOC; |
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116 smc91c111_update(s); |
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117 } |
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118 |
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119 /* Remove and item from the RX FIFO. */ |
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120 static void smc91c111_pop_rx_fifo(smc91c111_state *s) |
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121 { |
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122 int i; |
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123 |
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124 s->rx_fifo_len--; |
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125 if (s->rx_fifo_len) { |
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126 for (i = 0; i < s->rx_fifo_len; i++) |
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127 s->rx_fifo[i] = s->rx_fifo[i + 1]; |
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128 s->int_level |= INT_RCV; |
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129 } else { |
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130 s->int_level &= ~INT_RCV; |
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131 } |
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132 smc91c111_update(s); |
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133 } |
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134 |
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135 /* Remove an item from the TX completion FIFO. */ |
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136 static void smc91c111_pop_tx_fifo_done(smc91c111_state *s) |
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137 { |
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138 int i; |
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139 |
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140 if (s->tx_fifo_done_len == 0) |
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141 return; |
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142 s->tx_fifo_done_len--; |
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143 for (i = 0; i < s->tx_fifo_done_len; i++) |
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144 s->tx_fifo_done[i] = s->tx_fifo_done[i + 1]; |
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145 } |
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146 |
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147 /* Release the memory allocated to a packet. */ |
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148 static void smc91c111_release_packet(smc91c111_state *s, int packet) |
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149 { |
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150 s->allocated &= ~(1 << packet); |
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151 if (s->tx_alloc == 0x80) |
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152 smc91c111_tx_alloc(s); |
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153 } |
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154 |
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155 /* Flush the TX FIFO. */ |
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156 static void smc91c111_do_tx(smc91c111_state *s) |
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157 { |
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158 int i; |
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159 int len; |
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160 int control; |
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161 int add_crc; |
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162 int packetnum; |
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163 uint8_t *p; |
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164 |
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165 if ((s->tcr & TCR_TXEN) == 0) |
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166 return; |
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167 if (s->tx_fifo_len == 0) |
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168 return; |
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169 for (i = 0; i < s->tx_fifo_len; i++) { |
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170 packetnum = s->tx_fifo[i]; |
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171 p = &s->data[packetnum][0]; |
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172 /* Set status word. */ |
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173 *(p++) = 0x01; |
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174 *(p++) = 0x40; |
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175 len = *(p++); |
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176 len |= ((int)*(p++)) << 8; |
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177 len -= 6; |
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178 control = p[len + 1]; |
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179 if (control & 0x20) |
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180 len++; |
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181 /* ??? This overwrites the data following the buffer. |
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182 Don't know what real hardware does. */ |
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183 if (len < 64 && (s->tcr & TCR_PAD_EN)) { |
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184 memset(p + len, 0, 64 - len); |
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185 len = 64; |
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186 } |
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187 #if 0 |
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188 /* The card is supposed to append the CRC to the frame. However |
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189 none of the other network traffic has the CRC appended. |
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190 Suspect this is low level ethernet detail we don't need to worry |
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191 about. */ |
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192 add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0; |
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193 if (add_crc) { |
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194 uint32_t crc; |
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195 |
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196 crc = crc32(~0, p, len); |
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197 memcpy(p + len, &crc, 4); |
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198 len += 4; |
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199 } |
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200 #else |
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201 add_crc = 0; |
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202 #endif |
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203 if (s->ctr & CTR_AUTO_RELEASE) |
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204 /* Race? */ |
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205 smc91c111_release_packet(s, packetnum); |
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206 else if (s->tx_fifo_done_len < NUM_PACKETS) |
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207 s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum; |
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208 qemu_send_packet(s->vc, p, len); |
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209 } |
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210 s->tx_fifo_len = 0; |
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211 smc91c111_update(s); |
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212 } |
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213 |
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214 /* Add a packet to the TX FIFO. */ |
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215 static void smc91c111_queue_tx(smc91c111_state *s, int packet) |
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216 { |
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217 if (s->tx_fifo_len == NUM_PACKETS) |
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218 return; |
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219 s->tx_fifo[s->tx_fifo_len++] = packet; |
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220 smc91c111_do_tx(s); |
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221 } |
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222 |
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223 static void smc91c111_reset(smc91c111_state *s) |
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224 { |
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225 s->bank = 0; |
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226 s->tx_fifo_len = 0; |
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227 s->tx_fifo_done_len = 0; |
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228 s->rx_fifo_len = 0; |
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229 s->allocated = 0; |
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230 s->packet_num = 0; |
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231 s->tx_alloc = 0; |
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232 s->tcr = 0; |
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233 s->rcr = 0; |
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234 s->cr = 0xa0b1; |
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235 s->ctr = 0x1210; |
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236 s->ptr = 0; |
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237 s->ercv = 0x1f; |
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238 s->int_level = INT_TX_EMPTY; |
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239 s->int_mask = 0; |
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240 smc91c111_update(s); |
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241 } |
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242 |
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243 #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val |
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244 #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) |
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245 |
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246 static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, |
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247 uint32_t value) |
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248 { |
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249 smc91c111_state *s = (smc91c111_state *)opaque; |
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250 |
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251 if (offset == 14) { |
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252 s->bank = value; |
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253 return; |
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254 } |
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255 if (offset == 15) |
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256 return; |
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257 switch (s->bank) { |
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258 case 0: |
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259 switch (offset) { |
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260 case 0: /* TCR */ |
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261 SET_LOW(tcr, value); |
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262 return; |
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263 case 1: |
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264 SET_HIGH(tcr, value); |
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265 return; |
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266 case 4: /* RCR */ |
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267 SET_LOW(rcr, value); |
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268 return; |
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269 case 5: |
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270 SET_HIGH(rcr, value); |
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271 if (s->rcr & RCR_SOFT_RST) |
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272 smc91c111_reset(s); |
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273 return; |
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274 case 10: case 11: /* RPCR */ |
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275 /* Ignored */ |
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276 return; |
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277 } |
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278 break; |
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279 |
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280 case 1: |
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281 switch (offset) { |
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282 case 0: /* CONFIG */ |
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283 SET_LOW(cr, value); |
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284 return; |
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285 case 1: |
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286 SET_HIGH(cr,value); |
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287 return; |
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288 case 2: case 3: /* BASE */ |
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289 case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
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290 /* Not implemented. */ |
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291 return; |
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292 case 10: /* Genral Purpose */ |
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293 SET_LOW(gpr, value); |
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294 return; |
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295 case 11: |
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296 SET_HIGH(gpr, value); |
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297 return; |
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298 case 12: /* Control */ |
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299 if (value & 1) |
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300 fprintf(stderr, "smc91c111:EEPROM store not implemented\n"); |
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301 if (value & 2) |
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302 fprintf(stderr, "smc91c111:EEPROM reload not implemented\n"); |
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303 value &= ~3; |
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304 SET_LOW(ctr, value); |
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305 return; |
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306 case 13: |
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307 SET_HIGH(ctr, value); |
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308 return; |
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309 } |
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310 break; |
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311 |
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312 case 2: |
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313 switch (offset) { |
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314 case 0: /* MMU Command */ |
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315 switch (value >> 5) { |
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316 case 0: /* no-op */ |
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317 break; |
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318 case 1: /* Allocate for TX. */ |
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319 s->tx_alloc = 0x80; |
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320 s->int_level &= ~INT_ALLOC; |
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321 smc91c111_update(s); |
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322 smc91c111_tx_alloc(s); |
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323 break; |
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324 case 2: /* Reset MMU. */ |
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325 s->allocated = 0; |
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326 s->tx_fifo_len = 0; |
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327 s->tx_fifo_done_len = 0; |
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328 s->rx_fifo_len = 0; |
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329 s->tx_alloc = 0; |
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330 break; |
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331 case 3: /* Remove from RX FIFO. */ |
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332 smc91c111_pop_rx_fifo(s); |
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333 break; |
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334 case 4: /* Remove from RX FIFO and release. */ |
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335 if (s->rx_fifo_len > 0) { |
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336 smc91c111_release_packet(s, s->rx_fifo[0]); |
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337 } |
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338 smc91c111_pop_rx_fifo(s); |
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339 break; |
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340 case 5: /* Release. */ |
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341 smc91c111_release_packet(s, s->packet_num); |
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342 break; |
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343 case 6: /* Add to TX FIFO. */ |
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344 smc91c111_queue_tx(s, s->packet_num); |
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345 break; |
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346 case 7: /* Reset TX FIFO. */ |
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347 s->tx_fifo_len = 0; |
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348 s->tx_fifo_done_len = 0; |
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349 break; |
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350 } |
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351 return; |
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352 case 1: |
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353 /* Ignore. */ |
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354 return; |
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355 case 2: /* Packet Number Register */ |
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356 s->packet_num = value; |
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357 return; |
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358 case 3: case 4: case 5: |
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359 /* Should be readonly, but linux writes to them anyway. Ignore. */ |
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360 return; |
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361 case 6: /* Pointer */ |
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362 SET_LOW(ptr, value); |
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363 return; |
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364 case 7: |
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365 SET_HIGH(ptr, value); |
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366 return; |
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367 case 8: case 9: case 10: case 11: /* Data */ |
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368 { |
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369 int p; |
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370 int n; |
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371 |
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372 if (s->ptr & 0x8000) |
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373 n = s->rx_fifo[0]; |
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374 else |
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375 n = s->packet_num; |
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376 p = s->ptr & 0x07ff; |
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377 if (s->ptr & 0x4000) { |
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378 s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff); |
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379 } else { |
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380 p += (offset & 3); |
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381 } |
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382 s->data[n][p] = value; |
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383 } |
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384 return; |
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385 case 12: /* Interrupt ACK. */ |
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386 s->int_level &= ~(value & 0xd6); |
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387 if (value & INT_TX) |
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388 smc91c111_pop_tx_fifo_done(s); |
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389 smc91c111_update(s); |
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390 return; |
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391 case 13: /* Interrupt mask. */ |
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392 s->int_mask = value; |
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393 smc91c111_update(s); |
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394 return; |
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395 } |
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396 break;; |
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397 |
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398 case 3: |
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399 switch (offset) { |
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400 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
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401 /* Multicast table. */ |
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402 /* Not implemented. */ |
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403 return; |
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404 case 8: case 9: /* Management Interface. */ |
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405 /* Not implemented. */ |
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406 return; |
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407 case 12: /* Early receive. */ |
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408 s->ercv = value & 0x1f; |
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409 case 13: |
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410 /* Ignore. */ |
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411 return; |
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412 } |
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413 break; |
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414 } |
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415 cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n", |
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416 s->bank, (int)offset); |
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417 } |
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418 |
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419 static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) |
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420 { |
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421 smc91c111_state *s = (smc91c111_state *)opaque; |
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422 |
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423 if (offset == 14) { |
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424 return s->bank; |
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425 } |
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426 if (offset == 15) |
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427 return 0x33; |
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428 switch (s->bank) { |
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429 case 0: |
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430 switch (offset) { |
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431 case 0: /* TCR */ |
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432 return s->tcr & 0xff; |
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433 case 1: |
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434 return s->tcr >> 8; |
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435 case 2: /* EPH Status */ |
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436 return 0; |
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437 case 3: |
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438 return 0x40; |
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439 case 4: /* RCR */ |
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440 return s->rcr & 0xff; |
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441 case 5: |
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442 return s->rcr >> 8; |
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443 case 6: /* Counter */ |
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444 case 7: |
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445 /* Not implemented. */ |
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446 return 0; |
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447 case 8: /* Memory size. */ |
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448 return NUM_PACKETS; |
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449 case 9: /* Free memory available. */ |
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450 { |
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451 int i; |
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452 int n; |
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453 n = 0; |
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454 for (i = 0; i < NUM_PACKETS; i++) { |
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455 if (s->allocated & (1 << i)) |
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456 n++; |
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457 } |
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458 return n; |
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459 } |
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460 case 10: case 11: /* RPCR */ |
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461 /* Not implemented. */ |
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462 return 0; |
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463 } |
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464 break; |
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465 |
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466 case 1: |
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467 switch (offset) { |
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468 case 0: /* CONFIG */ |
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469 return s->cr & 0xff; |
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470 case 1: |
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471 return s->cr >> 8; |
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472 case 2: case 3: /* BASE */ |
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473 /* Not implemented. */ |
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474 return 0; |
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475 case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
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476 return s->macaddr[offset - 4]; |
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477 case 10: /* General Purpose */ |
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478 return s->gpr & 0xff; |
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479 case 11: |
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480 return s->gpr >> 8; |
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481 case 12: /* Control */ |
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482 return s->ctr & 0xff; |
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483 case 13: |
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484 return s->ctr >> 8; |
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485 } |
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486 break; |
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487 |
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488 case 2: |
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489 switch (offset) { |
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490 case 0: case 1: /* MMUCR Busy bit. */ |
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491 return 0; |
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492 case 2: /* Packet Number. */ |
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493 return s->packet_num; |
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494 case 3: /* Allocation Result. */ |
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495 return s->tx_alloc; |
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496 case 4: /* TX FIFO */ |
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497 if (s->tx_fifo_done_len == 0) |
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498 return 0x80; |
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499 else |
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500 return s->tx_fifo_done[0]; |
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501 case 5: /* RX FIFO */ |
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502 if (s->rx_fifo_len == 0) |
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503 return 0x80; |
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504 else |
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505 return s->rx_fifo[0]; |
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506 case 6: /* Pointer */ |
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507 return s->ptr & 0xff; |
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508 case 7: |
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509 return (s->ptr >> 8) & 0xf7; |
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510 case 8: case 9: case 10: case 11: /* Data */ |
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511 { |
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512 int p; |
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513 int n; |
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514 |
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515 if (s->ptr & 0x8000) |
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516 n = s->rx_fifo[0]; |
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517 else |
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518 n = s->packet_num; |
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519 p = s->ptr & 0x07ff; |
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520 if (s->ptr & 0x4000) { |
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521 s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff); |
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522 } else { |
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523 p += (offset & 3); |
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524 } |
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525 return s->data[n][p]; |
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526 } |
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527 case 12: /* Interrupt status. */ |
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528 return s->int_level; |
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529 case 13: /* Interrupt mask. */ |
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530 return s->int_mask; |
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531 } |
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532 break; |
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533 |
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534 case 3: |
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535 switch (offset) { |
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536 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
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537 /* Multicast table. */ |
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538 /* Not implemented. */ |
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539 return 0; |
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540 case 8: /* Management Interface. */ |
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541 /* Not implemented. */ |
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542 return 0x30; |
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543 case 9: |
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544 return 0x33; |
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545 case 10: /* Revision. */ |
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546 return 0x91; |
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547 case 11: |
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548 return 0x33; |
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549 case 12: |
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550 return s->ercv; |
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551 case 13: |
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552 return 0; |
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553 } |
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554 break; |
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555 } |
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556 cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n", |
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557 s->bank, (int)offset); |
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558 return 0; |
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559 } |
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560 |
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561 static void smc91c111_writew(void *opaque, target_phys_addr_t offset, |
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562 uint32_t value) |
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563 { |
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564 smc91c111_writeb(opaque, offset, value & 0xff); |
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565 smc91c111_writeb(opaque, offset + 1, value >> 8); |
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566 } |
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567 |
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568 static void smc91c111_writel(void *opaque, target_phys_addr_t offset, |
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569 uint32_t value) |
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570 { |
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571 /* 32-bit writes to offset 0xc only actually write to the bank select |
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572 register (offset 0xe) */ |
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573 if (offset != 0xc) |
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574 smc91c111_writew(opaque, offset, value & 0xffff); |
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575 smc91c111_writew(opaque, offset + 2, value >> 16); |
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576 } |
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577 |
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578 static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) |
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579 { |
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580 uint32_t val; |
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581 val = smc91c111_readb(opaque, offset); |
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582 val |= smc91c111_readb(opaque, offset + 1) << 8; |
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583 return val; |
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584 } |
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585 |
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586 static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset) |
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587 { |
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588 uint32_t val; |
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589 val = smc91c111_readw(opaque, offset); |
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590 val |= smc91c111_readw(opaque, offset + 2) << 16; |
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591 return val; |
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592 } |
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593 |
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594 static int smc91c111_can_receive(void *opaque) |
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595 { |
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596 smc91c111_state *s = (smc91c111_state *)opaque; |
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597 |
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598 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
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599 return 1; |
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600 if (s->allocated == (1 << NUM_PACKETS) - 1) |
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601 return 0; |
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602 return 1; |
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603 } |
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604 |
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605 static void smc91c111_receive(void *opaque, const uint8_t *buf, int size) |
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606 { |
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607 smc91c111_state *s = (smc91c111_state *)opaque; |
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608 int status; |
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609 int packetsize; |
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610 uint32_t crc; |
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611 int packetnum; |
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612 uint8_t *p; |
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613 |
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614 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
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615 return; |
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616 /* Short packets are padded with zeros. Receiving a packet |
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617 < 64 bytes long is considered an error condition. */ |
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618 if (size < 64) |
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619 packetsize = 64; |
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620 else |
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621 packetsize = (size & ~1); |
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622 packetsize += 6; |
|
623 crc = (s->rcr & RCR_STRIP_CRC) == 0; |
|
624 if (crc) |
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625 packetsize += 4; |
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626 /* TODO: Flag overrun and receive errors. */ |
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627 if (packetsize > 2048) |
|
628 return; |
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629 packetnum = smc91c111_allocate_packet(s); |
|
630 if (packetnum == 0x80) |
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631 return; |
|
632 s->rx_fifo[s->rx_fifo_len++] = packetnum; |
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633 |
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634 p = &s->data[packetnum][0]; |
|
635 /* ??? Multicast packets? */ |
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636 status = 0; |
|
637 if (size > 1518) |
|
638 status |= RS_TOOLONG; |
|
639 if (size & 1) |
|
640 status |= RS_ODDFRAME; |
|
641 *(p++) = status & 0xff; |
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642 *(p++) = status >> 8; |
|
643 *(p++) = packetsize & 0xff; |
|
644 *(p++) = packetsize >> 8; |
|
645 memcpy(p, buf, size & ~1); |
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646 p += (size & ~1); |
|
647 /* Pad short packets. */ |
|
648 if (size < 64) { |
|
649 int pad; |
|
650 |
|
651 if (size & 1) |
|
652 *(p++) = buf[size - 1]; |
|
653 pad = 64 - size; |
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654 memset(p, 0, pad); |
|
655 p += pad; |
|
656 size = 64; |
|
657 } |
|
658 /* It's not clear if the CRC should go before or after the last byte in |
|
659 odd sized packets. Linux disables the CRC, so that's no help. |
|
660 The pictures in the documentation show the CRC aligned on a 16-bit |
|
661 boundary before the last odd byte, so that's what we do. */ |
|
662 if (crc) { |
|
663 crc = crc32(~0, buf, size); |
|
664 *(p++) = crc & 0xff; crc >>= 8; |
|
665 *(p++) = crc & 0xff; crc >>= 8; |
|
666 *(p++) = crc & 0xff; crc >>= 8; |
|
667 *(p++) = crc & 0xff; crc >>= 8; |
|
668 } |
|
669 if (size & 1) { |
|
670 *(p++) = buf[size - 1]; |
|
671 *(p++) = 0x60; |
|
672 } else { |
|
673 *(p++) = 0; |
|
674 *(p++) = 0x40; |
|
675 } |
|
676 /* TODO: Raise early RX interrupt? */ |
|
677 s->int_level |= INT_RCV; |
|
678 smc91c111_update(s); |
|
679 } |
|
680 |
|
681 static CPUReadMemoryFunc *smc91c111_readfn[] = { |
|
682 smc91c111_readb, |
|
683 smc91c111_readw, |
|
684 smc91c111_readl |
|
685 }; |
|
686 |
|
687 static CPUWriteMemoryFunc *smc91c111_writefn[] = { |
|
688 smc91c111_writeb, |
|
689 smc91c111_writew, |
|
690 smc91c111_writel |
|
691 }; |
|
692 |
|
693 void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq) |
|
694 { |
|
695 smc91c111_state *s; |
|
696 int iomemtype; |
|
697 |
|
698 s = (smc91c111_state *)qemu_mallocz(sizeof(smc91c111_state)); |
|
699 iomemtype = cpu_register_io_memory(0, smc91c111_readfn, |
|
700 smc91c111_writefn, s); |
|
701 cpu_register_physical_memory(base, 16, iomemtype); |
|
702 s->irq = irq; |
|
703 memcpy(s->macaddr, nd->macaddr, 6); |
|
704 |
|
705 smc91c111_reset(s); |
|
706 |
|
707 s->vc = qemu_new_vlan_client(nd->vlan, smc91c111_receive, |
|
708 smc91c111_can_receive, s); |
|
709 /* ??? Save/restore. */ |
|
710 } |