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1 /* |
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2 * QEMU Sparc Sun4c interrupt controller emulation |
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3 * |
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4 * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "sun4m.h" |
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26 #include "console.h" |
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27 //#define DEBUG_IRQ_COUNT |
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28 //#define DEBUG_IRQ |
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29 |
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30 #ifdef DEBUG_IRQ |
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31 #define DPRINTF(fmt, args...) \ |
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32 do { printf("IRQ: " fmt , ##args); } while (0) |
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33 #else |
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34 #define DPRINTF(fmt, args...) |
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35 #endif |
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36 |
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37 /* |
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38 * Registers of interrupt controller in sun4c. |
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39 * |
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40 */ |
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41 |
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42 #define MAX_PILS 16 |
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43 |
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44 typedef struct Sun4c_INTCTLState { |
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45 #ifdef DEBUG_IRQ_COUNT |
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46 uint64_t irq_count; |
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47 #endif |
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48 qemu_irq *cpu_irqs; |
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49 const uint32_t *intbit_to_level; |
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50 uint32_t pil_out; |
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51 uint8_t reg; |
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52 uint8_t pending; |
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53 } Sun4c_INTCTLState; |
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54 |
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55 #define INTCTL_SIZE 1 |
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56 |
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57 static void sun4c_check_interrupts(void *opaque); |
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58 |
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59 static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr) |
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60 { |
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61 Sun4c_INTCTLState *s = opaque; |
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62 uint32_t ret; |
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63 |
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64 ret = s->reg; |
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65 DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
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66 |
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67 return ret; |
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68 } |
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69 |
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70 static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, |
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71 uint32_t val) |
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72 { |
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73 Sun4c_INTCTLState *s = opaque; |
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74 |
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75 DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
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76 val &= 0xbf; |
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77 s->reg = val; |
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78 sun4c_check_interrupts(s); |
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79 } |
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80 |
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81 static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = { |
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82 sun4c_intctl_mem_readb, |
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83 NULL, |
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84 NULL, |
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85 }; |
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86 |
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87 static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = { |
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88 sun4c_intctl_mem_writeb, |
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89 NULL, |
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90 NULL, |
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91 }; |
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92 |
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93 void sun4c_pic_info(void *opaque) |
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94 { |
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95 Sun4c_INTCTLState *s = opaque; |
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96 |
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97 term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending, |
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98 s->reg); |
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99 } |
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100 |
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101 void sun4c_irq_info(void *opaque) |
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102 { |
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103 #ifndef DEBUG_IRQ_COUNT |
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104 term_printf("irq statistic code not compiled.\n"); |
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105 #else |
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106 Sun4c_INTCTLState *s = opaque; |
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107 int64_t count; |
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108 |
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109 term_printf("IRQ statistics:\n"); |
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110 count = s->irq_count[i]; |
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111 if (count > 0) |
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112 term_printf("%2d: %" PRId64 "\n", i, count); |
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113 #endif |
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114 } |
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115 |
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116 static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, }; |
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117 |
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118 static void sun4c_check_interrupts(void *opaque) |
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119 { |
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120 Sun4c_INTCTLState *s = opaque; |
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121 uint32_t pil_pending; |
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122 unsigned int i; |
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123 |
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124 DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled); |
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125 pil_pending = 0; |
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126 if (s->pending && !(s->reg & 0x80000000)) { |
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127 for (i = 0; i < 8; i++) { |
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128 if (s->pending & (1 << i)) |
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129 pil_pending |= 1 << intbit_to_level[i]; |
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130 } |
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131 } |
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132 |
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133 for (i = 0; i < MAX_PILS; i++) { |
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134 if (pil_pending & (1 << i)) { |
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135 if (!(s->pil_out & (1 << i))) |
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136 qemu_irq_raise(s->cpu_irqs[i]); |
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137 } else { |
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138 if (s->pil_out & (1 << i)) |
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139 qemu_irq_lower(s->cpu_irqs[i]); |
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140 } |
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141 } |
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142 s->pil_out = pil_pending; |
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143 } |
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144 |
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145 /* |
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146 * "irq" here is the bit number in the system interrupt register |
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147 */ |
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148 static void sun4c_set_irq(void *opaque, int irq, int level) |
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149 { |
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150 Sun4c_INTCTLState *s = opaque; |
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151 uint32_t mask = 1 << irq; |
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152 uint32_t pil = intbit_to_level[irq]; |
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153 |
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154 DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil, |
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155 level); |
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156 if (pil > 0) { |
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157 if (level) { |
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158 #ifdef DEBUG_IRQ_COUNT |
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159 s->irq_count[pil]++; |
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160 #endif |
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161 s->pending |= mask; |
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162 } else { |
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163 s->pending &= ~mask; |
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164 } |
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165 sun4c_check_interrupts(s); |
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166 } |
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167 } |
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168 |
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169 static void sun4c_intctl_save(QEMUFile *f, void *opaque) |
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170 { |
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171 Sun4c_INTCTLState *s = opaque; |
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172 |
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173 qemu_put_8s(f, &s->reg); |
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174 qemu_put_8s(f, &s->pending); |
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175 } |
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176 |
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177 static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id) |
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178 { |
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179 Sun4c_INTCTLState *s = opaque; |
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180 |
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181 if (version_id != 1) |
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182 return -EINVAL; |
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183 |
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184 qemu_get_8s(f, &s->reg); |
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185 qemu_get_8s(f, &s->pending); |
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186 sun4c_check_interrupts(s); |
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187 |
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188 return 0; |
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189 } |
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190 |
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191 static void sun4c_intctl_reset(void *opaque) |
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192 { |
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193 Sun4c_INTCTLState *s = opaque; |
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194 |
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195 s->reg = 1; |
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196 s->pending = 0; |
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197 sun4c_check_interrupts(s); |
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198 } |
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199 |
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200 void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, |
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201 qemu_irq *parent_irq) |
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202 { |
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203 int sun4c_intctl_io_memory; |
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204 Sun4c_INTCTLState *s; |
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205 |
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206 s = qemu_mallocz(sizeof(Sun4c_INTCTLState)); |
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207 if (!s) |
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208 return NULL; |
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209 |
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210 sun4c_intctl_io_memory = cpu_register_io_memory(0, sun4c_intctl_mem_read, |
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211 sun4c_intctl_mem_write, s); |
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212 cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory); |
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213 s->cpu_irqs = parent_irq; |
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214 |
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215 register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save, |
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216 sun4c_intctl_load, s); |
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217 |
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218 qemu_register_reset(sun4c_intctl_reset, s); |
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219 *irq = qemu_allocate_irqs(sun4c_set_irq, s, 8); |
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220 |
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221 sun4c_intctl_reset(s); |
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222 return s; |
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223 } |