1 #ifndef SUN4M_H

     2 #define SUN4M_H

     3 

     4 /* Devices used by sparc32 system.  */

     5 

     6 /* iommu.c */

     7 void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq);

     8 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,

     9                                  uint8_t *buf, int len, int is_write);

    10 static inline void sparc_iommu_memory_read(void *opaque,

    11                                            target_phys_addr_t addr,

    12                                            uint8_t *buf, int len)

    13 {

    14     sparc_iommu_memory_rw(opaque, addr, buf, len, 0);

    15 }

    16 

    17 static inline void sparc_iommu_memory_write(void *opaque,

    18                                             target_phys_addr_t addr,

    19                                             uint8_t *buf, int len)

    20 {

    21     sparc_iommu_memory_rw(opaque, addr, buf, len, 1);

    22 }

    23 

    24 /* tcx.c */

    25 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,

    26               unsigned long vram_offset, int vram_size, int width, int height,

    27               int depth);

    28 

    29 /* slavio_intctl.c */

    30 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,

    31                          const uint32_t *intbit_to_level,

    32                          qemu_irq **irq, qemu_irq **cpu_irq,

    33                          qemu_irq **parent_irq, unsigned int cputimer);

    34 void slavio_pic_info(void *opaque);

    35 void slavio_irq_info(void *opaque);

    36 

    37 /* sbi.c */

    38 void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,

    39                qemu_irq **parent_irq);

    40 

    41 /* sun4c_intctl.c */

    42 void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,

    43                         qemu_irq *parent_irq);

    44 void sun4c_pic_info(void *opaque);

    45 void sun4c_irq_info(void *opaque);

    46 

    47 /* slavio_timer.c */

    48 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,

    49                            qemu_irq *cpu_irqs, unsigned int num_cpus);

    50 

    51 /* slavio_serial.c */

    52 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,

    53                                 CharDriverState *chr1, CharDriverState *chr2);

    54 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,

    55                                int disabled);

    56 

    57 /* slavio_misc.c */

    58 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,

    59                        target_phys_addr_t aux1_base,

    60                        target_phys_addr_t aux2_base, qemu_irq irq,

    61                        qemu_irq cpu_halt, qemu_irq **fdc_tc);

    62 void slavio_set_power_fail(void *opaque, int power_failing);

    63 

    64 /* cs4231.c */

    65 void cs_init(target_phys_addr_t base, int irq, void *intctl);

    66 

    67 /* sparc32_dma.c */

    68 #include "sparc32_dma.h"

    69 

    70 /* pcnet.c */

    71 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,

    72                 qemu_irq irq, qemu_irq *reset);

    73 

    74 /* eccmemctl.c */

    75 void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);

    76 

    77 #endif