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1 /* |
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2 * Texas Instruments TUSB6010 emulation. |
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3 * Based on reverse-engineering of a linux driver. |
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4 * |
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5 * Copyright (C) 2008 Nokia Corporation |
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6 * Written by Andrzej Zaborowski <andrew@openedhand.com> |
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7 * |
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8 * This program is free software; you can redistribute it and/or |
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9 * modify it under the terms of the GNU General Public License as |
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10 * published by the Free Software Foundation; either version 2 or |
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11 * (at your option) version 3 of the License. |
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12 * |
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13 * This program is distributed in the hope that it will be useful, |
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 * GNU General Public License for more details. |
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17 * |
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18 * You should have received a copy of the GNU General Public License |
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19 * along with this program; if not, write to the Free Software |
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20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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21 * MA 02111-1307 USA |
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22 */ |
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23 #include "qemu-common.h" |
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24 #include "qemu-timer.h" |
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25 #include "usb.h" |
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26 #include "omap.h" |
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27 #include "irq.h" |
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28 #include "devices.h" |
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29 |
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30 struct tusb_s { |
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31 int iomemtype[2]; |
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32 qemu_irq irq; |
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33 struct musb_s *musb; |
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34 QEMUTimer *otg_timer; |
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35 QEMUTimer *pwr_timer; |
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36 |
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37 int power; |
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38 uint32_t scratch; |
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39 uint16_t test_reset; |
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40 uint32_t prcm_config; |
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41 uint32_t prcm_mngmt; |
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42 uint16_t otg_status; |
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43 uint32_t dev_config; |
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44 int host_mode; |
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45 uint32_t intr; |
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46 uint32_t intr_ok; |
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47 uint32_t mask; |
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48 uint32_t usbip_intr; |
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49 uint32_t usbip_mask; |
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50 uint32_t gpio_intr; |
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51 uint32_t gpio_mask; |
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52 uint32_t gpio_config; |
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53 uint32_t dma_intr; |
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54 uint32_t dma_mask; |
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55 uint32_t dma_map; |
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56 uint32_t dma_config; |
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57 uint32_t ep0_config; |
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58 uint32_t rx_config[15]; |
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59 uint32_t tx_config[15]; |
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60 uint32_t wkup_mask; |
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61 uint32_t pullup[2]; |
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62 uint32_t control_config; |
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63 uint32_t otg_timer_val; |
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64 }; |
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65 |
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66 #define TUSB_DEVCLOCK 60000000 /* 60 MHz */ |
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67 |
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68 #define TUSB_VLYNQ_CTRL 0x004 |
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69 |
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70 /* Mentor Graphics OTG core registers. */ |
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71 #define TUSB_BASE_OFFSET 0x400 |
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72 |
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73 /* FIFO registers, 32-bit. */ |
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74 #define TUSB_FIFO_BASE 0x600 |
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75 |
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76 /* Device System & Control registers, 32-bit. */ |
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77 #define TUSB_SYS_REG_BASE 0x800 |
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78 |
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79 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) |
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80 #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) |
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81 #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) |
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82 #define TUSB_DEV_CONF_SOFT_ID (1 << 1) |
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83 #define TUSB_DEV_CONF_ID_SEL (1 << 0) |
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84 |
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85 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) |
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86 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) |
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87 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) |
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88 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) |
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89 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) |
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90 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) |
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91 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) |
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92 #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) |
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93 #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) |
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94 #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) |
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95 #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) |
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96 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) |
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97 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) |
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98 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) |
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99 #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) |
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100 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) |
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101 #define TUSB_PHY_OTG_CTRL_PD (1 << 6) |
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102 #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) |
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103 #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) |
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104 #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) |
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105 #define TUSB_PHY_OTG_CTRL_RESET (1 << 2) |
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106 #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) |
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107 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) |
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108 |
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109 /* OTG status register */ |
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110 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) |
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111 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) |
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112 #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) |
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113 #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) |
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114 #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) |
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115 #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) |
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116 #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) |
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117 #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) |
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118 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) |
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119 #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) |
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120 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) |
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121 |
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122 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) |
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123 #define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) |
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124 #define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) |
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125 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) |
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126 |
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127 /* PRCM configuration register */ |
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128 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) |
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129 #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) |
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130 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) |
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131 |
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132 /* PRCM management register */ |
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133 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) |
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134 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) |
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135 #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) |
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136 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) |
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137 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) |
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138 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) |
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139 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) |
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140 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) |
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141 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) |
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142 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) |
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143 #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) |
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144 #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) |
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145 #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) |
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146 #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) |
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147 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) |
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148 |
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149 /* Wake-up source clear and mask registers */ |
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150 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) |
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151 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) |
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152 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) |
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153 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) |
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154 #define TUSB_PRCM_WGPIO_7 (1 << 12) |
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155 #define TUSB_PRCM_WGPIO_6 (1 << 11) |
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156 #define TUSB_PRCM_WGPIO_5 (1 << 10) |
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157 #define TUSB_PRCM_WGPIO_4 (1 << 9) |
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158 #define TUSB_PRCM_WGPIO_3 (1 << 8) |
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159 #define TUSB_PRCM_WGPIO_2 (1 << 7) |
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160 #define TUSB_PRCM_WGPIO_1 (1 << 6) |
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161 #define TUSB_PRCM_WGPIO_0 (1 << 5) |
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162 #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ |
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163 #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ |
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164 #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ |
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165 #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ |
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166 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ |
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167 |
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168 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) |
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169 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) |
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170 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) |
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171 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) |
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172 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) |
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173 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) |
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174 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) |
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175 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) |
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176 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) |
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177 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) |
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178 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) |
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179 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) |
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180 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) |
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181 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) |
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182 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) |
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183 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) |
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184 |
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185 /* NOR flash interrupt source registers */ |
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186 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) |
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187 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) |
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188 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) |
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189 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) |
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190 #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) |
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191 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17) |
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192 #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) |
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193 #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) |
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194 #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) |
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195 #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) |
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196 #define TUSB_INT_SRC_DEV_READY (1 << 12) |
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197 #define TUSB_INT_SRC_USB_IP_TX (1 << 9) |
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198 #define TUSB_INT_SRC_USB_IP_RX (1 << 8) |
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199 #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) |
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200 #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) |
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201 #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) |
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202 #define TUSB_INT_SRC_USB_IP_CONN (1 << 4) |
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203 #define TUSB_INT_SRC_USB_IP_SOF (1 << 3) |
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204 #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) |
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205 #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) |
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206 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) |
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207 |
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208 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) |
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209 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) |
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210 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) |
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211 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) |
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212 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) |
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213 #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) |
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214 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) |
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215 #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) |
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216 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) |
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217 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) |
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218 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) |
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219 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) |
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220 |
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221 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) |
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222 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) |
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223 |
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224 /* Device System & Control register bitfields */ |
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225 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) |
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226 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) |
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227 #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) |
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228 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) |
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229 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) |
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230 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) |
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231 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) |
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232 #define TUSB_EP0_CONFIG_SW_EN (1 << 8) |
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233 #define TUSB_EP0_CONFIG_DIR_TX (1 << 7) |
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234 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) |
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235 #define TUSB_EP_CONFIG_SW_EN (1 << 31) |
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236 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) |
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237 #define TUSB_PROD_TEST_RESET_VAL 0xa596 |
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238 |
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239 int tusb6010_sync_io(struct tusb_s *s) |
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240 { |
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241 return s->iomemtype[0]; |
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242 } |
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243 |
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244 int tusb6010_async_io(struct tusb_s *s) |
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245 { |
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246 return s->iomemtype[1]; |
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247 } |
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248 |
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249 static void tusb_intr_update(struct tusb_s *s) |
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250 { |
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251 if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY) |
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252 qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); |
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253 else |
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254 qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); |
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255 } |
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256 |
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257 static void tusb_usbip_intr_update(struct tusb_s *s) |
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258 { |
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259 /* TX interrupt in the MUSB */ |
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260 if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) |
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261 s->intr |= TUSB_INT_SRC_USB_IP_TX; |
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262 else |
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263 s->intr &= ~TUSB_INT_SRC_USB_IP_TX; |
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264 |
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265 /* RX interrupt in the MUSB */ |
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266 if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) |
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267 s->intr |= TUSB_INT_SRC_USB_IP_RX; |
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268 else |
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269 s->intr &= ~TUSB_INT_SRC_USB_IP_RX; |
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270 |
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271 /* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */ |
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272 |
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273 tusb_intr_update(s); |
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274 } |
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275 |
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276 static void tusb_dma_intr_update(struct tusb_s *s) |
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277 { |
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278 if (s->dma_intr & ~s->dma_mask) |
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279 s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; |
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280 else |
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281 s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; |
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282 |
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283 tusb_intr_update(s); |
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284 } |
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285 |
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286 static void tusb_gpio_intr_update(struct tusb_s *s) |
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287 { |
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288 /* TODO: How is this signalled? */ |
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289 } |
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290 |
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291 extern CPUReadMemoryFunc *musb_read[]; |
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292 extern CPUWriteMemoryFunc *musb_write[]; |
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293 |
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294 static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr) |
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295 { |
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296 struct tusb_s *s = (struct tusb_s *) opaque; |
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297 |
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298 switch (addr & 0xfff) { |
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299 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
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300 return musb_read[0](s->musb, addr & 0x1ff); |
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301 |
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302 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
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303 return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
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304 } |
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305 |
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306 printf("%s: unknown register at %03x\n", |
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307 __FUNCTION__, (int) (addr & 0xfff)); |
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308 return 0; |
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309 } |
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310 |
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311 static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr) |
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312 { |
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313 struct tusb_s *s = (struct tusb_s *) opaque; |
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314 |
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315 switch (addr & 0xfff) { |
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316 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
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317 return musb_read[1](s->musb, addr & 0x1ff); |
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318 |
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319 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
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320 return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
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321 } |
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322 |
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323 printf("%s: unknown register at %03x\n", |
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324 __FUNCTION__, (int) (addr & 0xfff)); |
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325 return 0; |
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326 } |
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327 |
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328 static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr) |
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329 { |
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330 struct tusb_s *s = (struct tusb_s *) opaque; |
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331 int offset = addr & 0xfff; |
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332 int epnum; |
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333 uint32_t ret; |
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334 |
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335 switch (offset) { |
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336 case TUSB_DEV_CONF: |
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337 return s->dev_config; |
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338 |
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339 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
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340 return musb_read[2](s->musb, offset & 0x1ff); |
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341 |
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342 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
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343 return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
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344 |
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345 case TUSB_PHY_OTG_CTRL_ENABLE: |
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346 case TUSB_PHY_OTG_CTRL: |
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347 return 0x00; /* TODO */ |
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348 |
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349 case TUSB_DEV_OTG_STAT: |
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350 ret = s->otg_status; |
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351 #if 0 |
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352 if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) |
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353 ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; |
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354 #endif |
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355 return ret; |
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356 case TUSB_DEV_OTG_TIMER: |
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357 return s->otg_timer_val; |
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358 |
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359 case TUSB_PRCM_REV: |
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360 return 0x20; |
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361 case TUSB_PRCM_CONF: |
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362 return s->prcm_config; |
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363 case TUSB_PRCM_MNGMT: |
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364 return s->prcm_mngmt; |
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365 case TUSB_PRCM_WAKEUP_SOURCE: |
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366 case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ |
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367 return 0x00000000; |
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368 case TUSB_PRCM_WAKEUP_MASK: |
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369 return s->wkup_mask; |
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370 |
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371 case TUSB_PULLUP_1_CTRL: |
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372 return s->pullup[0]; |
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373 case TUSB_PULLUP_2_CTRL: |
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374 return s->pullup[1]; |
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375 |
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376 case TUSB_INT_CTRL_REV: |
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377 return 0x20; |
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378 case TUSB_INT_CTRL_CONF: |
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379 return s->control_config; |
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380 |
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381 case TUSB_USBIP_INT_SRC: |
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382 case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ |
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383 case TUSB_USBIP_INT_CLEAR: |
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384 return s->usbip_intr; |
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385 case TUSB_USBIP_INT_MASK: |
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386 return s->usbip_mask; |
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387 |
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388 case TUSB_DMA_INT_SRC: |
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389 case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ |
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390 case TUSB_DMA_INT_CLEAR: |
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391 return s->dma_intr; |
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392 case TUSB_DMA_INT_MASK: |
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393 return s->dma_mask; |
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394 |
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395 case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ |
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396 case TUSB_GPIO_INT_SET: |
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397 case TUSB_GPIO_INT_CLEAR: |
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398 return s->gpio_intr; |
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399 case TUSB_GPIO_INT_MASK: |
|
400 return s->gpio_mask; |
|
401 |
|
402 case TUSB_INT_SRC: |
|
403 case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ |
|
404 case TUSB_INT_SRC_CLEAR: |
|
405 return s->intr; |
|
406 case TUSB_INT_MASK: |
|
407 return s->mask; |
|
408 |
|
409 case TUSB_GPIO_REV: |
|
410 return 0x30; |
|
411 case TUSB_GPIO_CONF: |
|
412 return s->gpio_config; |
|
413 |
|
414 case TUSB_DMA_CTRL_REV: |
|
415 return 0x30; |
|
416 case TUSB_DMA_REQ_CONF: |
|
417 return s->dma_config; |
|
418 case TUSB_EP0_CONF: |
|
419 return s->ep0_config; |
|
420 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
|
421 epnum = (offset - TUSB_EP_IN_SIZE) >> 2; |
|
422 return s->tx_config[epnum]; |
|
423 case TUSB_DMA_EP_MAP: |
|
424 return s->dma_map; |
|
425 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
|
426 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2; |
|
427 return s->rx_config[epnum]; |
|
428 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ... |
|
429 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b): |
|
430 epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2; |
|
431 return 0x00000000; /* TODO */ |
|
432 case TUSB_WAIT_COUNT: |
|
433 return 0x00; /* TODO */ |
|
434 |
|
435 case TUSB_SCRATCH_PAD: |
|
436 return s->scratch; |
|
437 |
|
438 case TUSB_PROD_TEST_RESET: |
|
439 return s->test_reset; |
|
440 |
|
441 /* DIE IDs */ |
|
442 case TUSB_DIDR1_LO: |
|
443 return 0xa9453c59; |
|
444 case TUSB_DIDR1_HI: |
|
445 return 0x54059adf; |
|
446 } |
|
447 |
|
448 printf("%s: unknown register at %03x\n", __FUNCTION__, offset); |
|
449 return 0; |
|
450 } |
|
451 |
|
452 static void tusb_async_writeb(void *opaque, target_phys_addr_t addr, |
|
453 uint32_t value) |
|
454 { |
|
455 struct tusb_s *s = (struct tusb_s *) opaque; |
|
456 |
|
457 switch (addr & 0xfff) { |
|
458 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
|
459 musb_write[0](s->musb, addr & 0x1ff, value); |
|
460 break; |
|
461 |
|
462 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
|
463 musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
|
464 break; |
|
465 |
|
466 default: |
|
467 printf("%s: unknown register at %03x\n", |
|
468 __FUNCTION__, (int) (addr & 0xfff)); |
|
469 return; |
|
470 } |
|
471 } |
|
472 |
|
473 static void tusb_async_writeh(void *opaque, target_phys_addr_t addr, |
|
474 uint32_t value) |
|
475 { |
|
476 struct tusb_s *s = (struct tusb_s *) opaque; |
|
477 |
|
478 switch (addr & 0xfff) { |
|
479 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
|
480 musb_write[1](s->musb, addr & 0x1ff, value); |
|
481 break; |
|
482 |
|
483 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
|
484 musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
|
485 break; |
|
486 |
|
487 default: |
|
488 printf("%s: unknown register at %03x\n", |
|
489 __FUNCTION__, (int) (addr & 0xfff)); |
|
490 return; |
|
491 } |
|
492 } |
|
493 |
|
494 static void tusb_async_writew(void *opaque, target_phys_addr_t addr, |
|
495 uint32_t value) |
|
496 { |
|
497 struct tusb_s *s = (struct tusb_s *) opaque; |
|
498 int offset = addr & 0xfff; |
|
499 int epnum; |
|
500 |
|
501 switch (offset) { |
|
502 case TUSB_VLYNQ_CTRL: |
|
503 break; |
|
504 |
|
505 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
|
506 musb_write[2](s->musb, offset & 0x1ff, value); |
|
507 break; |
|
508 |
|
509 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
|
510 musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
|
511 break; |
|
512 |
|
513 case TUSB_DEV_CONF: |
|
514 s->dev_config = value; |
|
515 s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); |
|
516 if (value & TUSB_DEV_CONF_PROD_TEST_MODE) |
|
517 cpu_abort(cpu_single_env, "%s: Product Test mode not allowed\n", |
|
518 __FUNCTION__); |
|
519 break; |
|
520 |
|
521 case TUSB_PHY_OTG_CTRL_ENABLE: |
|
522 case TUSB_PHY_OTG_CTRL: |
|
523 return; /* TODO */ |
|
524 case TUSB_DEV_OTG_TIMER: |
|
525 s->otg_timer_val = value; |
|
526 if (value & TUSB_DEV_OTG_TIMER_ENABLE) |
|
527 qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) + |
|
528 muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), |
|
529 ticks_per_sec, TUSB_DEVCLOCK)); |
|
530 else |
|
531 qemu_del_timer(s->otg_timer); |
|
532 break; |
|
533 |
|
534 case TUSB_PRCM_CONF: |
|
535 s->prcm_config = value; |
|
536 break; |
|
537 case TUSB_PRCM_MNGMT: |
|
538 s->prcm_mngmt = value; |
|
539 break; |
|
540 case TUSB_PRCM_WAKEUP_CLEAR: |
|
541 break; |
|
542 case TUSB_PRCM_WAKEUP_MASK: |
|
543 s->wkup_mask = value; |
|
544 break; |
|
545 |
|
546 case TUSB_PULLUP_1_CTRL: |
|
547 s->pullup[0] = value; |
|
548 break; |
|
549 case TUSB_PULLUP_2_CTRL: |
|
550 s->pullup[1] = value; |
|
551 break; |
|
552 case TUSB_INT_CTRL_CONF: |
|
553 s->control_config = value; |
|
554 tusb_intr_update(s); |
|
555 break; |
|
556 |
|
557 case TUSB_USBIP_INT_SET: |
|
558 s->usbip_intr |= value; |
|
559 tusb_usbip_intr_update(s); |
|
560 break; |
|
561 case TUSB_USBIP_INT_CLEAR: |
|
562 s->usbip_intr &= ~value; |
|
563 tusb_usbip_intr_update(s); |
|
564 musb_core_intr_clear(s->musb, ~value); |
|
565 break; |
|
566 case TUSB_USBIP_INT_MASK: |
|
567 s->usbip_mask = value; |
|
568 tusb_usbip_intr_update(s); |
|
569 break; |
|
570 |
|
571 case TUSB_DMA_INT_SET: |
|
572 s->dma_intr |= value; |
|
573 tusb_dma_intr_update(s); |
|
574 break; |
|
575 case TUSB_DMA_INT_CLEAR: |
|
576 s->dma_intr &= ~value; |
|
577 tusb_dma_intr_update(s); |
|
578 break; |
|
579 case TUSB_DMA_INT_MASK: |
|
580 s->dma_mask = value; |
|
581 tusb_dma_intr_update(s); |
|
582 break; |
|
583 |
|
584 case TUSB_GPIO_INT_SET: |
|
585 s->gpio_intr |= value; |
|
586 tusb_gpio_intr_update(s); |
|
587 break; |
|
588 case TUSB_GPIO_INT_CLEAR: |
|
589 s->gpio_intr &= ~value; |
|
590 tusb_gpio_intr_update(s); |
|
591 break; |
|
592 case TUSB_GPIO_INT_MASK: |
|
593 s->gpio_mask = value; |
|
594 tusb_gpio_intr_update(s); |
|
595 break; |
|
596 |
|
597 case TUSB_INT_SRC_SET: |
|
598 s->intr |= value; |
|
599 tusb_intr_update(s); |
|
600 break; |
|
601 case TUSB_INT_SRC_CLEAR: |
|
602 s->intr &= ~value; |
|
603 tusb_intr_update(s); |
|
604 break; |
|
605 case TUSB_INT_MASK: |
|
606 s->mask = value; |
|
607 tusb_intr_update(s); |
|
608 break; |
|
609 |
|
610 case TUSB_GPIO_CONF: |
|
611 s->gpio_config = value; |
|
612 break; |
|
613 case TUSB_DMA_REQ_CONF: |
|
614 s->dma_config = value; |
|
615 break; |
|
616 case TUSB_EP0_CONF: |
|
617 s->ep0_config = value & 0x1ff; |
|
618 musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value), |
|
619 value & TUSB_EP0_CONFIG_DIR_TX); |
|
620 break; |
|
621 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
|
622 epnum = (offset - TUSB_EP_IN_SIZE) >> 2; |
|
623 s->tx_config[epnum] = value; |
|
624 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); |
|
625 break; |
|
626 case TUSB_DMA_EP_MAP: |
|
627 s->dma_map = value; |
|
628 break; |
|
629 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
|
630 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2; |
|
631 s->rx_config[epnum] = value; |
|
632 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); |
|
633 break; |
|
634 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ... |
|
635 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b): |
|
636 epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2; |
|
637 return; /* TODO */ |
|
638 case TUSB_WAIT_COUNT: |
|
639 return; /* TODO */ |
|
640 |
|
641 case TUSB_SCRATCH_PAD: |
|
642 s->scratch = value; |
|
643 break; |
|
644 |
|
645 case TUSB_PROD_TEST_RESET: |
|
646 s->test_reset = value; |
|
647 break; |
|
648 |
|
649 default: |
|
650 printf("%s: unknown register at %03x\n", __FUNCTION__, offset); |
|
651 return; |
|
652 } |
|
653 } |
|
654 |
|
655 static CPUReadMemoryFunc *tusb_async_readfn[] = { |
|
656 tusb_async_readb, |
|
657 tusb_async_readh, |
|
658 tusb_async_readw, |
|
659 }; |
|
660 |
|
661 static CPUWriteMemoryFunc *tusb_async_writefn[] = { |
|
662 tusb_async_writeb, |
|
663 tusb_async_writeh, |
|
664 tusb_async_writew, |
|
665 }; |
|
666 |
|
667 static void tusb_otg_tick(void *opaque) |
|
668 { |
|
669 struct tusb_s *s = (struct tusb_s *) opaque; |
|
670 |
|
671 s->otg_timer_val = 0; |
|
672 s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; |
|
673 tusb_intr_update(s); |
|
674 } |
|
675 |
|
676 static void tusb_power_tick(void *opaque) |
|
677 { |
|
678 struct tusb_s *s = (struct tusb_s *) opaque; |
|
679 |
|
680 if (s->power) { |
|
681 s->intr_ok = ~0; |
|
682 tusb_intr_update(s); |
|
683 } |
|
684 } |
|
685 |
|
686 static void tusb_musb_core_intr(void *opaque, int source, int level) |
|
687 { |
|
688 struct tusb_s *s = (struct tusb_s *) opaque; |
|
689 uint16_t otg_status = s->otg_status; |
|
690 |
|
691 switch (source) { |
|
692 case musb_set_vbus: |
|
693 if (level) |
|
694 otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; |
|
695 else |
|
696 otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; |
|
697 |
|
698 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */ |
|
699 /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */ |
|
700 if (s->otg_status != otg_status) { |
|
701 s->otg_status = otg_status; |
|
702 s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; |
|
703 tusb_intr_update(s); |
|
704 } |
|
705 break; |
|
706 |
|
707 case musb_set_session: |
|
708 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */ |
|
709 /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */ |
|
710 if (level) { |
|
711 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; |
|
712 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; |
|
713 } else { |
|
714 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; |
|
715 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; |
|
716 } |
|
717 |
|
718 /* XXX: some IRQ or anything? */ |
|
719 break; |
|
720 |
|
721 case musb_irq_tx: |
|
722 case musb_irq_rx: |
|
723 s->usbip_intr = musb_core_intr_get(s->musb); |
|
724 /* Fall through. */ |
|
725 default: |
|
726 if (level) |
|
727 s->intr |= 1 << source; |
|
728 else |
|
729 s->intr &= ~(1 << source); |
|
730 tusb_intr_update(s); |
|
731 break; |
|
732 } |
|
733 } |
|
734 |
|
735 struct tusb_s *tusb6010_init(qemu_irq intr) |
|
736 { |
|
737 struct tusb_s *s = qemu_mallocz(sizeof(*s)); |
|
738 |
|
739 s->test_reset = TUSB_PROD_TEST_RESET_VAL; |
|
740 s->host_mode = 0; |
|
741 s->dev_config = 0; |
|
742 s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ |
|
743 s->power = 0; |
|
744 s->mask = 0xffffffff; |
|
745 s->intr = 0x00000000; |
|
746 s->otg_timer_val = 0; |
|
747 s->iomemtype[1] = cpu_register_io_memory(0, tusb_async_readfn, |
|
748 tusb_async_writefn, s); |
|
749 s->irq = intr; |
|
750 s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s); |
|
751 s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s); |
|
752 s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s, |
|
753 __musb_irq_max)); |
|
754 |
|
755 return s; |
|
756 } |
|
757 |
|
758 void tusb6010_power(struct tusb_s *s, int on) |
|
759 { |
|
760 if (!on) |
|
761 s->power = 0; |
|
762 else if (!s->power && on) { |
|
763 s->power = 1; |
|
764 |
|
765 /* Pull the interrupt down after TUSB6010 comes up. */ |
|
766 s->intr_ok = 0; |
|
767 tusb_intr_update(s); |
|
768 qemu_mod_timer(s->pwr_timer, |
|
769 qemu_get_clock(vm_clock) + ticks_per_sec / 2); |
|
770 } |
|
771 } |