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1 /* |
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2 * ARM Versatile Platform/Application Baseboard System emulation. |
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3 * |
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4 * Copyright (c) 2005-2007 CodeSourcery. |
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5 * Written by Paul Brook |
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6 * |
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7 * This code is licenced under the GPL. |
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8 */ |
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9 |
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10 #include "hw.h" |
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11 #include "arm-misc.h" |
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12 #include "primecell.h" |
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13 #include "devices.h" |
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14 #include "net.h" |
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15 #include "sysemu.h" |
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16 #include "pci.h" |
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17 #include "boards.h" |
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18 |
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19 /* Primary interrupt controller. */ |
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20 |
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21 typedef struct vpb_sic_state |
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22 { |
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23 uint32_t level; |
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24 uint32_t mask; |
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25 uint32_t pic_enable; |
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26 qemu_irq *parent; |
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27 int irq; |
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28 } vpb_sic_state; |
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29 |
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30 static void vpb_sic_update(vpb_sic_state *s) |
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31 { |
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32 uint32_t flags; |
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33 |
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34 flags = s->level & s->mask; |
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35 qemu_set_irq(s->parent[s->irq], flags != 0); |
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36 } |
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37 |
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38 static void vpb_sic_update_pic(vpb_sic_state *s) |
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39 { |
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40 int i; |
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41 uint32_t mask; |
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42 |
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43 for (i = 21; i <= 30; i++) { |
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44 mask = 1u << i; |
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45 if (!(s->pic_enable & mask)) |
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46 continue; |
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47 qemu_set_irq(s->parent[i], (s->level & mask) != 0); |
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48 } |
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49 } |
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50 |
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51 static void vpb_sic_set_irq(void *opaque, int irq, int level) |
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52 { |
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53 vpb_sic_state *s = (vpb_sic_state *)opaque; |
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54 if (level) |
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55 s->level |= 1u << irq; |
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56 else |
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57 s->level &= ~(1u << irq); |
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58 if (s->pic_enable & (1u << irq)) |
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59 qemu_set_irq(s->parent[irq], level); |
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60 vpb_sic_update(s); |
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61 } |
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62 |
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63 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) |
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64 { |
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65 vpb_sic_state *s = (vpb_sic_state *)opaque; |
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66 |
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67 switch (offset >> 2) { |
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68 case 0: /* STATUS */ |
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69 return s->level & s->mask; |
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70 case 1: /* RAWSTAT */ |
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71 return s->level; |
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72 case 2: /* ENABLE */ |
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73 return s->mask; |
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74 case 4: /* SOFTINT */ |
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75 return s->level & 1; |
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76 case 8: /* PICENABLE */ |
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77 return s->pic_enable; |
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78 default: |
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79 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
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80 return 0; |
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81 } |
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82 } |
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83 |
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84 static void vpb_sic_write(void *opaque, target_phys_addr_t offset, |
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85 uint32_t value) |
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86 { |
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87 vpb_sic_state *s = (vpb_sic_state *)opaque; |
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88 |
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89 switch (offset >> 2) { |
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90 case 2: /* ENSET */ |
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91 s->mask |= value; |
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92 break; |
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93 case 3: /* ENCLR */ |
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94 s->mask &= ~value; |
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95 break; |
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96 case 4: /* SOFTINTSET */ |
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97 if (value) |
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98 s->mask |= 1; |
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99 break; |
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100 case 5: /* SOFTINTCLR */ |
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101 if (value) |
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102 s->mask &= ~1u; |
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103 break; |
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104 case 8: /* PICENSET */ |
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105 s->pic_enable |= (value & 0x7fe00000); |
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106 vpb_sic_update_pic(s); |
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107 break; |
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108 case 9: /* PICENCLR */ |
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109 s->pic_enable &= ~value; |
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110 vpb_sic_update_pic(s); |
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111 break; |
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112 default: |
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113 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
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114 return; |
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115 } |
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116 vpb_sic_update(s); |
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117 } |
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118 |
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119 static CPUReadMemoryFunc *vpb_sic_readfn[] = { |
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120 vpb_sic_read, |
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121 vpb_sic_read, |
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122 vpb_sic_read |
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123 }; |
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124 |
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125 static CPUWriteMemoryFunc *vpb_sic_writefn[] = { |
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126 vpb_sic_write, |
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127 vpb_sic_write, |
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128 vpb_sic_write |
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129 }; |
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130 |
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131 static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq) |
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132 { |
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133 vpb_sic_state *s; |
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134 qemu_irq *qi; |
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135 int iomemtype; |
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136 |
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137 s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state)); |
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138 if (!s) |
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139 return NULL; |
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140 qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32); |
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141 s->parent = parent; |
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142 s->irq = irq; |
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143 iomemtype = cpu_register_io_memory(0, vpb_sic_readfn, |
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144 vpb_sic_writefn, s); |
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145 cpu_register_physical_memory(base, 0x00001000, iomemtype); |
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146 /* ??? Save/restore. */ |
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147 return qi; |
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148 } |
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149 |
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150 /* Board init. */ |
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151 |
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152 /* The AB and PB boards both use the same core, just with different |
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153 peripherans and expansion busses. For now we emulate a subset of the |
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154 PB peripherals and just change the board ID. */ |
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155 |
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156 static struct arm_boot_info versatile_binfo; |
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157 |
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158 static void versatile_init(ram_addr_t ram_size, int vga_ram_size, |
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159 const char *boot_device, DisplayState *ds, |
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160 const char *kernel_filename, const char *kernel_cmdline, |
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161 const char *initrd_filename, const char *cpu_model, |
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162 int board_id) |
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163 { |
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164 CPUState *env; |
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165 qemu_irq *pic; |
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166 qemu_irq *sic; |
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167 void *scsi_hba; |
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168 PCIBus *pci_bus; |
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169 NICInfo *nd; |
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170 int n; |
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171 int done_smc = 0; |
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172 int index; |
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173 |
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174 if (!cpu_model) |
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175 cpu_model = "arm926"; |
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176 env = cpu_init(cpu_model); |
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177 if (!env) { |
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178 fprintf(stderr, "Unable to find CPU definition\n"); |
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179 exit(1); |
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180 } |
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181 /* ??? RAM should repeat to fill physical memory space. */ |
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182 /* SDRAM at address zero. */ |
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183 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
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184 |
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185 arm_sysctl_init(0x10000000, 0x41007004); |
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186 pic = arm_pic_init_cpu(env); |
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187 pic = pl190_init(0x10140000, pic[0], pic[1]); |
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188 sic = vpb_sic_init(0x10003000, pic, 31); |
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189 pl050_init(0x10006000, sic[3], 0); |
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190 pl050_init(0x10007000, sic[4], 1); |
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191 |
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192 pci_bus = pci_vpb_init(sic, 27, 0); |
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193 /* The Versatile PCI bridge does not provide access to PCI IO space, |
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194 so many of the qemu PCI devices are not useable. */ |
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195 for(n = 0; n < nb_nics; n++) { |
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196 nd = &nd_table[n]; |
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197 if (!nd->model) |
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198 nd->model = done_smc ? "rtl8139" : "smc91c111"; |
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199 if (strcmp(nd->model, "smc91c111") == 0) { |
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200 smc91c111_init(nd, 0x10010000, sic[25]); |
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201 } else { |
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202 pci_nic_init(pci_bus, nd, -1); |
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203 } |
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204 } |
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205 if (usb_enabled) { |
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206 usb_ohci_init_pci(pci_bus, 3, -1); |
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207 } |
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208 if (drive_get_max_bus(IF_SCSI) > 0) { |
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209 fprintf(stderr, "qemu: too many SCSI bus\n"); |
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210 exit(1); |
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211 } |
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212 scsi_hba = lsi_scsi_init(pci_bus, -1); |
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213 for (n = 0; n < LSI_MAX_DEVS; n++) { |
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214 index = drive_get_index(IF_SCSI, 0, n); |
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215 if (index == -1) |
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216 continue; |
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217 lsi_scsi_attach(scsi_hba, drives_table[index].bdrv, n); |
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218 } |
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219 |
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220 pl011_init(0x101f1000, pic[12], serial_hds[0], PL011_ARM); |
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221 pl011_init(0x101f2000, pic[13], serial_hds[1], PL011_ARM); |
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222 pl011_init(0x101f3000, pic[14], serial_hds[2], PL011_ARM); |
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223 pl011_init(0x10009000, sic[6], serial_hds[3], PL011_ARM); |
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224 |
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225 pl080_init(0x10130000, pic[17], 8); |
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226 sp804_init(0x101e2000, pic[4]); |
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227 sp804_init(0x101e3000, pic[5]); |
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228 |
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229 /* The versatile/PB actually has a modified Color LCD controller |
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230 that includes hardware cursor support from the PL111. */ |
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231 pl110_init(ds, 0x10120000, pic[16], 1); |
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232 |
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233 index = drive_get_index(IF_SD, 0, 0); |
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234 if (index == -1) { |
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235 fprintf(stderr, "qemu: missing SecureDigital card\n"); |
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236 exit(1); |
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237 } |
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238 |
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239 pl181_init(0x10005000, drives_table[index].bdrv, sic[22], sic[1]); |
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240 #if 0 |
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241 /* Disabled because there's no way of specifying a block device. */ |
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242 pl181_init(0x1000b000, NULL, sic, 23, 2); |
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243 #endif |
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244 |
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245 /* Add PL031 Real Time Clock. */ |
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246 pl031_init(0x101e8000,pic[10]); |
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247 |
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248 /* Memory map for Versatile/PB: */ |
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249 /* 0x10000000 System registers. */ |
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250 /* 0x10001000 PCI controller config registers. */ |
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251 /* 0x10002000 Serial bus interface. */ |
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252 /* 0x10003000 Secondary interrupt controller. */ |
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253 /* 0x10004000 AACI (audio). */ |
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254 /* 0x10005000 MMCI0. */ |
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255 /* 0x10006000 KMI0 (keyboard). */ |
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256 /* 0x10007000 KMI1 (mouse). */ |
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257 /* 0x10008000 Character LCD Interface. */ |
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258 /* 0x10009000 UART3. */ |
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259 /* 0x1000a000 Smart card 1. */ |
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260 /* 0x1000b000 MMCI1. */ |
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261 /* 0x10010000 Ethernet. */ |
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262 /* 0x10020000 USB. */ |
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263 /* 0x10100000 SSMC. */ |
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264 /* 0x10110000 MPMC. */ |
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265 /* 0x10120000 CLCD Controller. */ |
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266 /* 0x10130000 DMA Controller. */ |
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267 /* 0x10140000 Vectored interrupt controller. */ |
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268 /* 0x101d0000 AHB Monitor Interface. */ |
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269 /* 0x101e0000 System Controller. */ |
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270 /* 0x101e1000 Watchdog Interface. */ |
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271 /* 0x101e2000 Timer 0/1. */ |
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272 /* 0x101e3000 Timer 2/3. */ |
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273 /* 0x101e4000 GPIO port 0. */ |
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274 /* 0x101e5000 GPIO port 1. */ |
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275 /* 0x101e6000 GPIO port 2. */ |
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276 /* 0x101e7000 GPIO port 3. */ |
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277 /* 0x101e8000 RTC. */ |
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278 /* 0x101f0000 Smart card 0. */ |
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279 /* 0x101f1000 UART0. */ |
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280 /* 0x101f2000 UART1. */ |
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281 /* 0x101f3000 UART2. */ |
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282 /* 0x101f4000 SSPI. */ |
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283 |
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284 versatile_binfo.ram_size = ram_size; |
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285 versatile_binfo.kernel_filename = kernel_filename; |
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286 versatile_binfo.kernel_cmdline = kernel_cmdline; |
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287 versatile_binfo.initrd_filename = initrd_filename; |
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288 versatile_binfo.board_id = board_id; |
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289 arm_load_kernel(env, &versatile_binfo); |
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290 } |
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291 |
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292 static void vpb_init(ram_addr_t ram_size, int vga_ram_size, |
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293 const char *boot_device, DisplayState *ds, |
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294 const char *kernel_filename, const char *kernel_cmdline, |
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295 const char *initrd_filename, const char *cpu_model) |
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296 { |
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297 versatile_init(ram_size, vga_ram_size, |
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298 boot_device, ds, |
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299 kernel_filename, kernel_cmdline, |
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300 initrd_filename, cpu_model, 0x183); |
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301 } |
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302 |
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303 static void vab_init(ram_addr_t ram_size, int vga_ram_size, |
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304 const char *boot_device, DisplayState *ds, |
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305 const char *kernel_filename, const char *kernel_cmdline, |
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306 const char *initrd_filename, const char *cpu_model) |
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307 { |
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308 versatile_init(ram_size, vga_ram_size, |
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309 boot_device, ds, |
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310 kernel_filename, kernel_cmdline, |
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311 initrd_filename, cpu_model, 0x25e); |
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312 } |
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313 |
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314 QEMUMachine versatilepb_machine = { |
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315 .name = "versatilepb", |
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316 .desc = "ARM Versatile/PB (ARM926EJ-S)", |
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317 .init = vpb_init, |
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318 .use_scsi = 1, |
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319 }; |
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320 |
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321 QEMUMachine versatileab_machine = { |
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322 .name = "versatileab", |
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323 .desc = "ARM Versatile/AB (ARM926EJ-S)", |
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324 .init = vab_init, |
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325 .use_scsi = 1, |
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326 }; |