1 /*

     2  * QEMU VGA Emulator.

     3  *

     4  * Copyright (c) 2003 Fabrice Bellard

     5  *

     6  * Permission is hereby granted, free of charge, to any person obtaining a copy

     7  * of this software and associated documentation files (the "Software"), to deal

     8  * in the Software without restriction, including without limitation the rights

     9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    10  * copies of the Software, and to permit persons to whom the Software is

    11  * furnished to do so, subject to the following conditions:

    12  *

    13  * The above copyright notice and this permission notice shall be included in

    14  * all copies or substantial portions of the Software.

    15  *

    16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    22  * THE SOFTWARE.

    23  */

    24 #include "hw.h"

    25 #include "console.h"

    26 #include "pc.h"

    27 #include "pci.h"

    28 #include "vga_int.h"

    29 #include "pixel_ops.h"

    30 #include "qemu-timer.h"

    31 #include "kvm.h"

    32 

    33 //#define DEBUG_VGA

    34 //#define DEBUG_VGA_MEM

    35 //#define DEBUG_VGA_REG

    36 

    37 //#define DEBUG_BOCHS_VBE

    38 

    39 /* force some bits to zero */

    40 const uint8_t sr_mask[8] = {

    41     (uint8_t)~0xfc,

    42     (uint8_t)~0xc2,

    43     (uint8_t)~0xf0,

    44     (uint8_t)~0xc0,

    45     (uint8_t)~0xf1,

    46     (uint8_t)~0xff,

    47     (uint8_t)~0xff,

    48     (uint8_t)~0x00,

    49 };

    50 

    51 const uint8_t gr_mask[16] = {

    52     (uint8_t)~0xf0, /* 0x00 */

    53     (uint8_t)~0xf0, /* 0x01 */

    54     (uint8_t)~0xf0, /* 0x02 */

    55     (uint8_t)~0xe0, /* 0x03 */

    56     (uint8_t)~0xfc, /* 0x04 */

    57     (uint8_t)~0x84, /* 0x05 */

    58     (uint8_t)~0xf0, /* 0x06 */

    59     (uint8_t)~0xf0, /* 0x07 */

    60     (uint8_t)~0x00, /* 0x08 */

    61     (uint8_t)~0xff, /* 0x09 */

    62     (uint8_t)~0xff, /* 0x0a */

    63     (uint8_t)~0xff, /* 0x0b */

    64     (uint8_t)~0xff, /* 0x0c */

    65     (uint8_t)~0xff, /* 0x0d */

    66     (uint8_t)~0xff, /* 0x0e */

    67     (uint8_t)~0xff, /* 0x0f */

    68 };

    69 

    70 #define cbswap_32(__x) \

    71 ((uint32_t)( \

    72 		(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \

    73 		(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) <<  8) | \

    74 		(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >>  8) | \

    75 		(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))

    76 

    77 #ifdef WORDS_BIGENDIAN

    78 #define PAT(x) cbswap_32(x)

    79 #else

    80 #define PAT(x) (x)

    81 #endif

    82 

    83 #ifdef WORDS_BIGENDIAN

    84 #define BIG 1

    85 #else

    86 #define BIG 0

    87 #endif

    88 

    89 #ifdef WORDS_BIGENDIAN

    90 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)

    91 #else

    92 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)

    93 #endif

    94 

    95 static const uint32_t mask16[16] = {

    96     PAT(0x00000000),

    97     PAT(0x000000ff),

    98     PAT(0x0000ff00),

    99     PAT(0x0000ffff),

   100     PAT(0x00ff0000),

   101     PAT(0x00ff00ff),

   102     PAT(0x00ffff00),

   103     PAT(0x00ffffff),

   104     PAT(0xff000000),

   105     PAT(0xff0000ff),

   106     PAT(0xff00ff00),

   107     PAT(0xff00ffff),

   108     PAT(0xffff0000),

   109     PAT(0xffff00ff),

   110     PAT(0xffffff00),

   111     PAT(0xffffffff),

   112 };

   113 

   114 #undef PAT

   115 

   116 #ifdef WORDS_BIGENDIAN

   117 #define PAT(x) (x)

   118 #else

   119 #define PAT(x) cbswap_32(x)

   120 #endif

   121 

   122 static const uint32_t dmask16[16] = {

   123     PAT(0x00000000),

   124     PAT(0x000000ff),

   125     PAT(0x0000ff00),

   126     PAT(0x0000ffff),

   127     PAT(0x00ff0000),

   128     PAT(0x00ff00ff),

   129     PAT(0x00ffff00),

   130     PAT(0x00ffffff),

   131     PAT(0xff000000),

   132     PAT(0xff0000ff),

   133     PAT(0xff00ff00),

   134     PAT(0xff00ffff),

   135     PAT(0xffff0000),

   136     PAT(0xffff00ff),

   137     PAT(0xffffff00),

   138     PAT(0xffffffff),

   139 };

   140 

   141 static const uint32_t dmask4[4] = {

   142     PAT(0x00000000),

   143     PAT(0x0000ffff),

   144     PAT(0xffff0000),

   145     PAT(0xffffffff),

   146 };

   147 

   148 static uint32_t expand4[256];

   149 static uint16_t expand2[256];

   150 static uint8_t expand4to8[16];

   151 

   152 static void vga_screen_dump(void *opaque, const char *filename);

   153 

   154 static void vga_dumb_update_retrace_info(VGAState *s)

   155 {

   156     (void) s;

   157 }

   158 

   159 static void vga_precise_update_retrace_info(VGAState *s)

   160 {

   161     int htotal_chars;

   162     int hretr_start_char;

   163     int hretr_skew_chars;

   164     int hretr_end_char;

   165 

   166     int vtotal_lines;

   167     int vretr_start_line;

   168     int vretr_end_line;

   169 

   170     int div2, sldiv2, dots;

   171     int clocking_mode;

   172     int clock_sel;

   173     const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};

   174     int64_t chars_per_sec;

   175     struct vga_precise_retrace *r = &s->retrace_info.precise;

   176 

   177     htotal_chars = s->cr[0x00] + 5;

   178     hretr_start_char = s->cr[0x04];

   179     hretr_skew_chars = (s->cr[0x05] >> 5) & 3;

   180     hretr_end_char = s->cr[0x05] & 0x1f;

   181 

   182     vtotal_lines = (s->cr[0x06]

   183                     | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2

   184         ;

   185     vretr_start_line = s->cr[0x10]

   186         | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)

   187         ;

   188     vretr_end_line = s->cr[0x11] & 0xf;

   189 

   190 

   191     div2 = (s->cr[0x17] >> 2) & 1;

   192     sldiv2 = (s->cr[0x17] >> 3) & 1;

   193 

   194     clocking_mode = (s->sr[0x01] >> 3) & 1;

   195     clock_sel = (s->msr >> 2) & 3;

   196     dots = (s->msr & 1) ? 8 : 9;

   197 

   198     chars_per_sec = clk_hz[clock_sel] / dots;

   199 

   200     htotal_chars <<= clocking_mode;

   201 

   202     r->total_chars = vtotal_lines * htotal_chars;

   203     if (r->freq) {

   204         r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);

   205     } else {

   206         r->ticks_per_char = ticks_per_sec / chars_per_sec;

   207     }

   208 

   209     r->vstart = vretr_start_line;

   210     r->vend = r->vstart + vretr_end_line + 1;

   211 

   212     r->hstart = hretr_start_char + hretr_skew_chars;

   213     r->hend = r->hstart + hretr_end_char + 1;

   214     r->htotal = htotal_chars;

   215 

   216 #if 0

   217     printf (

   218         "hz=%f\n"

   219         "htotal = %d\n"

   220         "hretr_start = %d\n"

   221         "hretr_skew = %d\n"

   222         "hretr_end = %d\n"

   223         "vtotal = %d\n"

   224         "vretr_start = %d\n"

   225         "vretr_end = %d\n"

   226         "div2 = %d sldiv2 = %d\n"

   227         "clocking_mode = %d\n"

   228         "clock_sel = %d %d\n"

   229         "dots = %d\n"

   230         "ticks/char = %lld\n"

   231         "\n",

   232         (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),

   233         htotal_chars,

   234         hretr_start_char,

   235         hretr_skew_chars,

   236         hretr_end_char,

   237         vtotal_lines,

   238         vretr_start_line,

   239         vretr_end_line,

   240         div2, sldiv2,

   241         clocking_mode,

   242         clock_sel,

   243         clk_hz[clock_sel],

   244         dots,

   245         r->ticks_per_char

   246         );

   247 #endif

   248 }

   249 

   250 static uint8_t vga_precise_retrace(VGAState *s)

   251 {

   252     struct vga_precise_retrace *r = &s->retrace_info.precise;

   253     uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);

   254 

   255     if (r->total_chars) {

   256         int cur_line, cur_line_char, cur_char;

   257         int64_t cur_tick;

   258 

   259         cur_tick = qemu_get_clock(vm_clock);

   260 

   261         cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;

   262         cur_line = cur_char / r->htotal;

   263 

   264         if (cur_line >= r->vstart && cur_line <= r->vend) {

   265             val |= ST01_V_RETRACE | ST01_DISP_ENABLE;

   266         } else {

   267             cur_line_char = cur_char % r->htotal;

   268             if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {

   269                 val |= ST01_DISP_ENABLE;

   270             }

   271         }

   272 

   273         return val;

   274     } else {

   275         return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);

   276     }

   277 }

   278 

   279 static uint8_t vga_dumb_retrace(VGAState *s)

   280 {

   281     return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);

   282 }

   283 

   284 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)

   285 {

   286     VGAState *s = opaque;

   287     int val, index;

   288 

   289     /* check port range access depending on color/monochrome mode */

   290     if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||

   291         (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {

   292         val = 0xff;

   293     } else {

   294         switch(addr) {

   295         case 0x3c0:

   296             if (s->ar_flip_flop == 0) {

   297                 val = s->ar_index;

   298             } else {

   299                 val = 0;

   300             }

   301             break;

   302         case 0x3c1:

   303             index = s->ar_index & 0x1f;

   304             if (index < 21)

   305                 val = s->ar[index];

   306             else

   307                 val = 0;

   308             break;

   309         case 0x3c2:

   310             val = s->st00;

   311             break;

   312         case 0x3c4:

   313             val = s->sr_index;

   314             break;

   315         case 0x3c5:

   316             val = s->sr[s->sr_index];

   317 #ifdef DEBUG_VGA_REG

   318             printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);

   319 #endif

   320             break;

   321         case 0x3c7:

   322             val = s->dac_state;

   323             break;

   324 	case 0x3c8:

   325 	    val = s->dac_write_index;

   326 	    break;

   327         case 0x3c9:

   328             val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];

   329             if (++s->dac_sub_index == 3) {

   330                 s->dac_sub_index = 0;

   331                 s->dac_read_index++;

   332             }

   333             break;

   334         case 0x3ca:

   335             val = s->fcr;

   336             break;

   337         case 0x3cc:

   338             val = s->msr;

   339             break;

   340         case 0x3ce:

   341             val = s->gr_index;

   342             break;

   343         case 0x3cf:

   344             val = s->gr[s->gr_index];

   345 #ifdef DEBUG_VGA_REG

   346             printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);

   347 #endif

   348             break;

   349         case 0x3b4:

   350         case 0x3d4:

   351             val = s->cr_index;

   352             break;

   353         case 0x3b5:

   354         case 0x3d5:

   355             val = s->cr[s->cr_index];

   356 #ifdef DEBUG_VGA_REG

   357             printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);

   358 #endif

   359             break;

   360         case 0x3ba:

   361         case 0x3da:

   362             /* just toggle to fool polling */

   363             val = s->st01 = s->retrace(s);

   364             s->ar_flip_flop = 0;

   365             break;

   366         default:

   367             val = 0x00;

   368             break;

   369         }

   370     }

   371 #if defined(DEBUG_VGA)

   372     printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);

   373 #endif

   374     return val;

   375 }

   376 

   377 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)

   378 {

   379     VGAState *s = opaque;

   380     int index;

   381 

   382     /* check port range access depending on color/monochrome mode */

   383     if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||

   384         (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))

   385         return;

   386 

   387 #ifdef DEBUG_VGA

   388     printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);

   389 #endif

   390 

   391     switch(addr) {

   392     case 0x3c0:

   393         if (s->ar_flip_flop == 0) {

   394             val &= 0x3f;

   395             s->ar_index = val;

   396         } else {

   397             index = s->ar_index & 0x1f;

   398             switch(index) {

   399             case 0x00 ... 0x0f:

   400                 s->ar[index] = val & 0x3f;

   401                 break;

   402             case 0x10:

   403                 s->ar[index] = val & ~0x10;

   404                 break;

   405             case 0x11:

   406                 s->ar[index] = val;

   407                 break;

   408             case 0x12:

   409                 s->ar[index] = val & ~0xc0;

   410                 break;

   411             case 0x13:

   412                 s->ar[index] = val & ~0xf0;

   413                 break;

   414             case 0x14:

   415                 s->ar[index] = val & ~0xf0;

   416                 break;

   417             default:

   418                 break;

   419             }

   420         }

   421         s->ar_flip_flop ^= 1;

   422         break;

   423     case 0x3c2:

   424         s->msr = val & ~0x10;

   425         s->update_retrace_info(s);

   426         break;

   427     case 0x3c4:

   428         s->sr_index = val & 7;

   429         break;

   430     case 0x3c5:

   431 #ifdef DEBUG_VGA_REG

   432         printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);

   433 #endif

   434         s->sr[s->sr_index] = val & sr_mask[s->sr_index];

   435         if (s->sr_index == 1) s->update_retrace_info(s);

   436         break;

   437     case 0x3c7:

   438         s->dac_read_index = val;

   439         s->dac_sub_index = 0;

   440         s->dac_state = 3;

   441         break;

   442     case 0x3c8:

   443         s->dac_write_index = val;

   444         s->dac_sub_index = 0;

   445         s->dac_state = 0;

   446         break;

   447     case 0x3c9:

   448         s->dac_cache[s->dac_sub_index] = val;

   449         if (++s->dac_sub_index == 3) {

   450             memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);

   451             s->dac_sub_index = 0;

   452             s->dac_write_index++;

   453         }

   454         break;

   455     case 0x3ce:

   456         s->gr_index = val & 0x0f;

   457         break;

   458     case 0x3cf:

   459 #ifdef DEBUG_VGA_REG

   460         printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);

   461 #endif

   462         s->gr[s->gr_index] = val & gr_mask[s->gr_index];

   463         break;

   464     case 0x3b4:

   465     case 0x3d4:

   466         s->cr_index = val;

   467         break;

   468     case 0x3b5:

   469     case 0x3d5:

   470 #ifdef DEBUG_VGA_REG

   471         printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);

   472 #endif

   473         /* handle CR0-7 protection */

   474         if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {

   475             /* can always write bit 4 of CR7 */

   476             if (s->cr_index == 7)

   477                 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);

   478             return;

   479         }

   480         switch(s->cr_index) {

   481         case 0x01: /* horizontal display end */

   482         case 0x07:

   483         case 0x09:

   484         case 0x0c:

   485         case 0x0d:

   486         case 0x12: /* vertical display end */

   487             s->cr[s->cr_index] = val;

   488             break;

   489         default:

   490             s->cr[s->cr_index] = val;

   491             break;

   492         }

   493 

   494         switch(s->cr_index) {

   495         case 0x00:

   496         case 0x04:

   497         case 0x05:

   498         case 0x06:

   499         case 0x07:

   500         case 0x11:

   501         case 0x17:

   502             s->update_retrace_info(s);

   503             break;

   504         }

   505         break;

   506     case 0x3ba:

   507     case 0x3da:

   508         s->fcr = val & 0x10;

   509         break;

   510     }

   511 }

   512 

   513 #ifdef CONFIG_BOCHS_VBE

   514 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)

   515 {

   516     VGAState *s = opaque;

   517     uint32_t val;

   518     val = s->vbe_index;

   519     return val;

   520 }

   521 

   522 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)

   523 {

   524     VGAState *s = opaque;

   525     uint32_t val;

   526 

   527     if (s->vbe_index <= VBE_DISPI_INDEX_NB) {

   528         if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {

   529             switch(s->vbe_index) {

   530                 /* XXX: do not hardcode ? */

   531             case VBE_DISPI_INDEX_XRES:

   532                 val = VBE_DISPI_MAX_XRES;

   533                 break;

   534             case VBE_DISPI_INDEX_YRES:

   535                 val = VBE_DISPI_MAX_YRES;

   536                 break;

   537             case VBE_DISPI_INDEX_BPP:

   538                 val = VBE_DISPI_MAX_BPP;

   539                 break;

   540             default:

   541                 val = s->vbe_regs[s->vbe_index];

   542                 break;

   543             }

   544         } else {

   545             val = s->vbe_regs[s->vbe_index];

   546         }

   547     } else {

   548         val = 0;

   549     }

   550 #ifdef DEBUG_BOCHS_VBE

   551     printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);

   552 #endif

   553     return val;

   554 }

   555 

   556 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)

   557 {

   558     VGAState *s = opaque;

   559     s->vbe_index = val;

   560 }

   561 

   562 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)

   563 {

   564     VGAState *s = opaque;

   565 

   566     if (s->vbe_index <= VBE_DISPI_INDEX_NB) {

   567 #ifdef DEBUG_BOCHS_VBE

   568         printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);

   569 #endif

   570         switch(s->vbe_index) {

   571         case VBE_DISPI_INDEX_ID:

   572             if (val == VBE_DISPI_ID0 ||

   573                 val == VBE_DISPI_ID1 ||

   574                 val == VBE_DISPI_ID2 ||

   575                 val == VBE_DISPI_ID3 ||

   576                 val == VBE_DISPI_ID4) {

   577                 s->vbe_regs[s->vbe_index] = val;

   578             }

   579             break;

   580         case VBE_DISPI_INDEX_XRES:

   581             if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {

   582                 s->vbe_regs[s->vbe_index] = val;

   583             }

   584             break;

   585         case VBE_DISPI_INDEX_YRES:

   586             if (val <= VBE_DISPI_MAX_YRES) {

   587                 s->vbe_regs[s->vbe_index] = val;

   588             }

   589             break;

   590         case VBE_DISPI_INDEX_BPP:

   591             if (val == 0)

   592                 val = 8;

   593             if (val == 4 || val == 8 || val == 15 ||

   594                 val == 16 || val == 24 || val == 32) {

   595                 s->vbe_regs[s->vbe_index] = val;

   596             }

   597             break;

   598         case VBE_DISPI_INDEX_BANK:

   599             if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {

   600               val &= (s->vbe_bank_mask >> 2);

   601             } else {

   602               val &= s->vbe_bank_mask;

   603             }

   604             s->vbe_regs[s->vbe_index] = val;

   605             s->bank_offset = (val << 16);

   606             break;

   607         case VBE_DISPI_INDEX_ENABLE:

   608             if ((val & VBE_DISPI_ENABLED) &&

   609                 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {

   610                 int h, shift_control;

   611 

   612                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =

   613                     s->vbe_regs[VBE_DISPI_INDEX_XRES];

   614                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =

   615                     s->vbe_regs[VBE_DISPI_INDEX_YRES];

   616                 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;

   617                 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;

   618 

   619                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

   620                     s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;

   621                 else

   622                     s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *

   623                         ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

   624                 s->vbe_start_addr = 0;

   625 

   626                 /* clear the screen (should be done in BIOS) */

   627                 if (!(val & VBE_DISPI_NOCLEARMEM)) {

   628                     memset(s->vram_ptr, 0,

   629                            s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);

   630                 }

   631 

   632                 /* we initialize the VGA graphic mode (should be done

   633                    in BIOS) */

   634                 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */

   635                 s->cr[0x17] |= 3; /* no CGA modes */

   636                 s->cr[0x13] = s->vbe_line_offset >> 3;

   637                 /* width */

   638                 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;

   639                 /* height (only meaningful if < 1024) */

   640                 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;

   641                 s->cr[0x12] = h;

   642                 s->cr[0x07] = (s->cr[0x07] & ~0x42) |

   643                     ((h >> 7) & 0x02) | ((h >> 3) & 0x40);

   644                 /* line compare to 1023 */

   645                 s->cr[0x18] = 0xff;

   646                 s->cr[0x07] |= 0x10;

   647                 s->cr[0x09] |= 0x40;

   648 

   649                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {

   650                     shift_control = 0;

   651                     s->sr[0x01] &= ~8; /* no double line */

   652                 } else {

   653                     shift_control = 2;

   654                     s->sr[4] |= 0x08; /* set chain 4 mode */

   655                     s->sr[2] |= 0x0f; /* activate all planes */

   656                 }

   657                 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);

   658                 s->cr[0x09] &= ~0x9f; /* no double scan */

   659             } else {

   660                 /* XXX: the bios should do that */

   661                 s->bank_offset = 0;

   662             }

   663             s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;

   664             s->vbe_regs[s->vbe_index] = val;

   665             break;

   666         case VBE_DISPI_INDEX_VIRT_WIDTH:

   667             {

   668                 int w, h, line_offset;

   669 

   670                 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])

   671                     return;

   672                 w = val;

   673                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

   674                     line_offset = w >> 1;

   675                 else

   676                     line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

   677                 h = s->vram_size / line_offset;

   678                 /* XXX: support weird bochs semantics ? */

   679                 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])

   680                     return;

   681                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;

   682                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;

   683                 s->vbe_line_offset = line_offset;

   684             }

   685             break;

   686         case VBE_DISPI_INDEX_X_OFFSET:

   687         case VBE_DISPI_INDEX_Y_OFFSET:

   688             {

   689                 int x;

   690                 s->vbe_regs[s->vbe_index] = val;

   691                 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];

   692                 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];

   693                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

   694                     s->vbe_start_addr += x >> 1;

   695                 else

   696                     s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

   697                 s->vbe_start_addr >>= 2;

   698             }

   699             break;

   700         default:

   701             break;

   702         }

   703     }

   704 }

   705 #endif

   706 

   707 /* called for accesses between 0xa0000 and 0xc0000 */

   708 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)

   709 {

   710     VGAState *s = opaque;

   711     int memory_map_mode, plane;

   712     uint32_t ret;

   713 

   714     /* convert to VGA memory offset */

   715     memory_map_mode = (s->gr[6] >> 2) & 3;

   716     addr &= 0x1ffff;

   717     switch(memory_map_mode) {

   718     case 0:

   719         break;

   720     case 1:

   721         if (addr >= 0x10000)

   722             return 0xff;

   723         addr += s->bank_offset;

   724         break;

   725     case 2:

   726         addr -= 0x10000;

   727         if (addr >= 0x8000)

   728             return 0xff;

   729         break;

   730     default:

   731     case 3:

   732         addr -= 0x18000;

   733         if (addr >= 0x8000)

   734             return 0xff;

   735         break;

   736     }

   737 

   738     if (s->sr[4] & 0x08) {

   739         /* chain 4 mode : simplest access */

   740         ret = s->vram_ptr[addr];

   741     } else if (s->gr[5] & 0x10) {

   742         /* odd/even mode (aka text mode mapping) */

   743         plane = (s->gr[4] & 2) | (addr & 1);

   744         ret = s->vram_ptr[((addr & ~1) << 1) | plane];

   745     } else {

   746         /* standard VGA latched access */

   747         s->latch = ((uint32_t *)s->vram_ptr)[addr];

   748 

   749         if (!(s->gr[5] & 0x08)) {

   750             /* read mode 0 */

   751             plane = s->gr[4];

   752             ret = GET_PLANE(s->latch, plane);

   753         } else {

   754             /* read mode 1 */

   755             ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];

   756             ret |= ret >> 16;

   757             ret |= ret >> 8;

   758             ret = (~ret) & 0xff;

   759         }

   760     }

   761     return ret;

   762 }

   763 

   764 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)

   765 {

   766     uint32_t v;

   767 #ifdef TARGET_WORDS_BIGENDIAN

   768     v = vga_mem_readb(opaque, addr) << 8;

   769     v |= vga_mem_readb(opaque, addr + 1);

   770 #else

   771     v = vga_mem_readb(opaque, addr);

   772     v |= vga_mem_readb(opaque, addr + 1) << 8;

   773 #endif

   774     return v;

   775 }

   776 

   777 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)

   778 {

   779     uint32_t v;

   780 #ifdef TARGET_WORDS_BIGENDIAN

   781     v = vga_mem_readb(opaque, addr) << 24;

   782     v |= vga_mem_readb(opaque, addr + 1) << 16;

   783     v |= vga_mem_readb(opaque, addr + 2) << 8;

   784     v |= vga_mem_readb(opaque, addr + 3);

   785 #else

   786     v = vga_mem_readb(opaque, addr);

   787     v |= vga_mem_readb(opaque, addr + 1) << 8;

   788     v |= vga_mem_readb(opaque, addr + 2) << 16;

   789     v |= vga_mem_readb(opaque, addr + 3) << 24;

   790 #endif

   791     return v;

   792 }

   793 

   794 /* called for accesses between 0xa0000 and 0xc0000 */

   795 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)

   796 {

   797     VGAState *s = opaque;

   798     int memory_map_mode, plane, write_mode, b, func_select, mask;

   799     uint32_t write_mask, bit_mask, set_mask;

   800 

   801 #ifdef DEBUG_VGA_MEM

   802     printf("vga: [0x%x] = 0x%02x\n", addr, val);

   803 #endif

   804     /* convert to VGA memory offset */

   805     memory_map_mode = (s->gr[6] >> 2) & 3;

   806     addr &= 0x1ffff;

   807     switch(memory_map_mode) {

   808     case 0:

   809         break;

   810     case 1:

   811         if (addr >= 0x10000)

   812             return;

   813         addr += s->bank_offset;

   814         break;

   815     case 2:

   816         addr -= 0x10000;

   817         if (addr >= 0x8000)

   818             return;

   819         break;

   820     default:

   821     case 3:

   822         addr -= 0x18000;

   823         if (addr >= 0x8000)

   824             return;

   825         break;

   826     }

   827 

   828     if (s->sr[4] & 0x08) {

   829         /* chain 4 mode : simplest access */

   830         plane = addr & 3;

   831         mask = (1 << plane);

   832         if (s->sr[2] & mask) {

   833             s->vram_ptr[addr] = val;

   834 #ifdef DEBUG_VGA_MEM

   835             printf("vga: chain4: [0x%x]\n", addr);

   836 #endif

   837             s->plane_updated |= mask; /* only used to detect font change */

   838             cpu_physical_memory_set_dirty(s->vram_offset + addr);

   839         }

   840     } else if (s->gr[5] & 0x10) {

   841         /* odd/even mode (aka text mode mapping) */

   842         plane = (s->gr[4] & 2) | (addr & 1);

   843         mask = (1 << plane);

   844         if (s->sr[2] & mask) {

   845             addr = ((addr & ~1) << 1) | plane;

   846             s->vram_ptr[addr] = val;

   847 #ifdef DEBUG_VGA_MEM

   848             printf("vga: odd/even: [0x%x]\n", addr);

   849 #endif

   850             s->plane_updated |= mask; /* only used to detect font change */

   851             cpu_physical_memory_set_dirty(s->vram_offset + addr);

   852         }

   853     } else {

   854         /* standard VGA latched access */

   855         write_mode = s->gr[5] & 3;

   856         switch(write_mode) {

   857         default:

   858         case 0:

   859             /* rotate */

   860             b = s->gr[3] & 7;

   861             val = ((val >> b) | (val << (8 - b))) & 0xff;

   862             val |= val << 8;

   863             val |= val << 16;

   864 

   865             /* apply set/reset mask */

   866             set_mask = mask16[s->gr[1]];

   867             val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);

   868             bit_mask = s->gr[8];

   869             break;

   870         case 1:

   871             val = s->latch;

   872             goto do_write;

   873         case 2:

   874             val = mask16[val & 0x0f];

   875             bit_mask = s->gr[8];

   876             break;

   877         case 3:

   878             /* rotate */

   879             b = s->gr[3] & 7;

   880             val = (val >> b) | (val << (8 - b));

   881 

   882             bit_mask = s->gr[8] & val;

   883             val = mask16[s->gr[0]];

   884             break;

   885         }

   886 

   887         /* apply logical operation */

   888         func_select = s->gr[3] >> 3;

   889         switch(func_select) {

   890         case 0:

   891         default:

   892             /* nothing to do */

   893             break;

   894         case 1:

   895             /* and */

   896             val &= s->latch;

   897             break;

   898         case 2:

   899             /* or */

   900             val |= s->latch;

   901             break;

   902         case 3:

   903             /* xor */

   904             val ^= s->latch;

   905             break;

   906         }

   907 

   908         /* apply bit mask */

   909         bit_mask |= bit_mask << 8;

   910         bit_mask |= bit_mask << 16;

   911         val = (val & bit_mask) | (s->latch & ~bit_mask);

   912 

   913     do_write:

   914         /* mask data according to sr[2] */

   915         mask = s->sr[2];

   916         s->plane_updated |= mask; /* only used to detect font change */

   917         write_mask = mask16[mask];

   918         ((uint32_t *)s->vram_ptr)[addr] =

   919             (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |

   920             (val & write_mask);

   921 #ifdef DEBUG_VGA_MEM

   922             printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",

   923                    addr * 4, write_mask, val);

   924 #endif

   925             cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));

   926     }

   927 }

   928 

   929 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)

   930 {

   931 #ifdef TARGET_WORDS_BIGENDIAN

   932     vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);

   933     vga_mem_writeb(opaque, addr + 1, val & 0xff);

   934 #else

   935     vga_mem_writeb(opaque, addr, val & 0xff);

   936     vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);

   937 #endif

   938 }

   939 

   940 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)

   941 {

   942 #ifdef TARGET_WORDS_BIGENDIAN

   943     vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);

   944     vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);

   945     vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);

   946     vga_mem_writeb(opaque, addr + 3, val & 0xff);

   947 #else

   948     vga_mem_writeb(opaque, addr, val & 0xff);

   949     vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);

   950     vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);

   951     vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);

   952 #endif

   953 }

   954 

   955 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,

   956                              const uint8_t *font_ptr, int h,

   957                              uint32_t fgcol, uint32_t bgcol);

   958 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,

   959                                   const uint8_t *font_ptr, int h,

   960                                   uint32_t fgcol, uint32_t bgcol, int dup9);

   961 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,

   962                                 const uint8_t *s, int width);

   963 

   964 #define DEPTH 8

   965 #include "vga_template.h"

   966 

   967 #define DEPTH 15

   968 #include "vga_template.h"

   969 

   970 #define BGR_FORMAT

   971 #define DEPTH 15

   972 #include "vga_template.h"

   973 

   974 #define DEPTH 16

   975 #include "vga_template.h"

   976 

   977 #define BGR_FORMAT

   978 #define DEPTH 16

   979 #include "vga_template.h"

   980 

   981 #define DEPTH 32

   982 #include "vga_template.h"

   983 

   984 #define BGR_FORMAT

   985 #define DEPTH 32

   986 #include "vga_template.h"

   987 

   988 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)

   989 {

   990     unsigned int col;

   991     col = rgb_to_pixel8(r, g, b);

   992     col |= col << 8;

   993     col |= col << 16;

   994     return col;

   995 }

   996 

   997 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)

   998 {

   999     unsigned int col;

  1000     col = rgb_to_pixel15(r, g, b);

  1001     col |= col << 16;

  1002     return col;

  1003 }

  1004 

  1005 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,

  1006                                           unsigned int b)

  1007 {

  1008     unsigned int col;

  1009     col = rgb_to_pixel15bgr(r, g, b);

  1010     col |= col << 16;

  1011     return col;

  1012 }

  1013 

  1014 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)

  1015 {

  1016     unsigned int col;

  1017     col = rgb_to_pixel16(r, g, b);

  1018     col |= col << 16;

  1019     return col;

  1020 }

  1021 

  1022 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,

  1023                                           unsigned int b)

  1024 {

  1025     unsigned int col;

  1026     col = rgb_to_pixel16bgr(r, g, b);

  1027     col |= col << 16;

  1028     return col;

  1029 }

  1030 

  1031 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)

  1032 {

  1033     unsigned int col;

  1034     col = rgb_to_pixel32(r, g, b);

  1035     return col;

  1036 }

  1037 

  1038 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)

  1039 {

  1040     unsigned int col;

  1041     col = rgb_to_pixel32bgr(r, g, b);

  1042     return col;

  1043 }

  1044 

  1045 /* return true if the palette was modified */

  1046 static int update_palette16(VGAState *s)

  1047 {

  1048     int full_update, i;

  1049     uint32_t v, col, *palette;

  1050 

  1051     full_update = 0;

  1052     palette = s->last_palette;

  1053     for(i = 0; i < 16; i++) {

  1054         v = s->ar[i];

  1055         if (s->ar[0x10] & 0x80)

  1056             v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);

  1057         else

  1058             v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);

  1059         v = v * 3;

  1060         col = s->rgb_to_pixel(c6_to_8(s->palette[v]),

  1061                               c6_to_8(s->palette[v + 1]),

  1062                               c6_to_8(s->palette[v + 2]));

  1063         if (col != palette[i]) {

  1064             full_update = 1;

  1065             palette[i] = col;

  1066         }

  1067     }

  1068     return full_update;

  1069 }

  1070 

  1071 /* return true if the palette was modified */

  1072 static int update_palette256(VGAState *s)

  1073 {

  1074     int full_update, i;

  1075     uint32_t v, col, *palette;

  1076 

  1077     full_update = 0;

  1078     palette = s->last_palette;

  1079     v = 0;

  1080     for(i = 0; i < 256; i++) {

  1081         if (s->dac_8bit) {

  1082           col = s->rgb_to_pixel(s->palette[v],

  1083                                 s->palette[v + 1],

  1084                                 s->palette[v + 2]);

  1085         } else {

  1086           col = s->rgb_to_pixel(c6_to_8(s->palette[v]),

  1087                                 c6_to_8(s->palette[v + 1]),

  1088                                 c6_to_8(s->palette[v + 2]));

  1089         }

  1090         if (col != palette[i]) {

  1091             full_update = 1;

  1092             palette[i] = col;

  1093         }

  1094         v += 3;

  1095     }

  1096     return full_update;

  1097 }

  1098 

  1099 static void vga_get_offsets(VGAState *s,

  1100                             uint32_t *pline_offset,

  1101                             uint32_t *pstart_addr,

  1102                             uint32_t *pline_compare)

  1103 {

  1104     uint32_t start_addr, line_offset, line_compare;

  1105 #ifdef CONFIG_BOCHS_VBE

  1106     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {

  1107         line_offset = s->vbe_line_offset;

  1108         start_addr = s->vbe_start_addr;

  1109         line_compare = 65535;

  1110     } else

  1111 #endif

  1112     {

  1113         /* compute line_offset in bytes */

  1114         line_offset = s->cr[0x13];

  1115         line_offset <<= 3;

  1116 

  1117         /* starting address */

  1118         start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);

  1119 

  1120         /* line compare */

  1121         line_compare = s->cr[0x18] |

  1122             ((s->cr[0x07] & 0x10) << 4) |

  1123             ((s->cr[0x09] & 0x40) << 3);

  1124     }

  1125     *pline_offset = line_offset;

  1126     *pstart_addr = start_addr;

  1127     *pline_compare = line_compare;

  1128 }

  1129 

  1130 /* update start_addr and line_offset. Return TRUE if modified */

  1131 static int update_basic_params(VGAState *s)

  1132 {

  1133     int full_update;

  1134     uint32_t start_addr, line_offset, line_compare;

  1135