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1 /* s390-dis.c -- Disassemble S390 instructions |
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2 Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. |
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3 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
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4 |
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5 This file is part of GDB, GAS and the GNU binutils. |
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6 |
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7 This program is free software; you can redistribute it and/or modify |
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8 it under the terms of the GNU General Public License as published by |
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9 the Free Software Foundation; either version 2 of the License, or |
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10 (at your option) any later version. |
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11 |
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12 This program is distributed in the hope that it will be useful, |
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 GNU General Public License for more details. |
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16 |
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17 You should have received a copy of the GNU General Public License |
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18 along with this program; if not, write to the Free Software |
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19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
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20 02110-1301, USA. */ |
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21 |
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22 #include <stdio.h> |
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23 #include "dis-asm.h" |
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24 |
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25 /* s390.h -- Header file for S390 opcode table |
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26 Copyright 2000, 2001, 2003 Free Software Foundation, Inc. |
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27 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
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28 |
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29 This file is part of BFD, the Binary File Descriptor library. |
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30 |
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31 This program is free software; you can redistribute it and/or modify |
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32 it under the terms of the GNU General Public License as published by |
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33 the Free Software Foundation; either version 2 of the License, or |
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34 (at your option) any later version. |
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35 |
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36 This program is distributed in the hope that it will be useful, |
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37 but WITHOUT ANY WARRANTY; without even the implied warranty of |
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38 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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39 GNU General Public License for more details. |
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40 |
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41 You should have received a copy of the GNU General Public License |
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42 along with this program; if not, write to the Free Software |
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43 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
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44 02110-1301, USA. */ |
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45 |
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46 #ifndef S390_H |
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47 #define S390_H |
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48 |
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49 /* List of instruction sets variations. */ |
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50 |
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51 enum s390_opcode_mode_val |
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52 { |
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53 S390_OPCODE_ESA = 0, |
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54 S390_OPCODE_ZARCH |
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55 }; |
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56 |
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57 enum s390_opcode_cpu_val |
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58 { |
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59 S390_OPCODE_G5 = 0, |
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60 S390_OPCODE_G6, |
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61 S390_OPCODE_Z900, |
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62 S390_OPCODE_Z990, |
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63 S390_OPCODE_Z9_109, |
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64 S390_OPCODE_Z9_EC |
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65 }; |
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66 |
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67 /* The opcode table is an array of struct s390_opcode. */ |
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68 |
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69 struct s390_opcode |
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70 { |
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71 /* The opcode name. */ |
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72 const char * name; |
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73 |
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74 /* The opcode itself. Those bits which will be filled in with |
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75 operands are zeroes. */ |
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76 unsigned char opcode[6]; |
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77 |
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78 /* The opcode mask. This is used by the disassembler. This is a |
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79 mask containing ones indicating those bits which must match the |
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80 opcode field, and zeroes indicating those bits which need not |
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81 match (and are presumably filled in by operands). */ |
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82 unsigned char mask[6]; |
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83 |
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84 /* The opcode length in bytes. */ |
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85 int oplen; |
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86 |
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87 /* An array of operand codes. Each code is an index into the |
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88 operand table. They appear in the order which the operands must |
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89 appear in assembly code, and are terminated by a zero. */ |
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90 unsigned char operands[6]; |
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91 |
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92 /* Bitmask of execution modes this opcode is available for. */ |
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93 unsigned int modes; |
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94 |
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95 /* First cpu this opcode is available for. */ |
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96 enum s390_opcode_cpu_val min_cpu; |
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97 }; |
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98 |
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99 /* The table itself is sorted by major opcode number, and is otherwise |
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100 in the order in which the disassembler should consider |
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101 instructions. */ |
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102 extern const struct s390_opcode s390_opcodes[]; |
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103 extern const int s390_num_opcodes; |
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104 |
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105 /* A opcode format table for the .insn pseudo mnemonic. */ |
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106 extern const struct s390_opcode s390_opformats[]; |
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107 extern const int s390_num_opformats; |
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108 |
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109 /* Values defined for the flags field of a struct powerpc_opcode. */ |
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110 |
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111 /* The operands table is an array of struct s390_operand. */ |
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112 |
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113 struct s390_operand |
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114 { |
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115 /* The number of bits in the operand. */ |
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116 int bits; |
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117 |
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118 /* How far the operand is left shifted in the instruction. */ |
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119 int shift; |
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120 |
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121 /* One bit syntax flags. */ |
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122 unsigned long flags; |
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123 }; |
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124 |
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125 /* Elements in the table are retrieved by indexing with values from |
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126 the operands field of the powerpc_opcodes table. */ |
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127 |
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128 extern const struct s390_operand s390_operands[]; |
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129 |
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130 /* Values defined for the flags field of a struct s390_operand. */ |
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131 |
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132 /* This operand names a register. The disassembler uses this to print |
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133 register names with a leading 'r'. */ |
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134 #define S390_OPERAND_GPR 0x1 |
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135 |
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136 /* This operand names a floating point register. The disassembler |
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137 prints these with a leading 'f'. */ |
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138 #define S390_OPERAND_FPR 0x2 |
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139 |
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140 /* This operand names an access register. The disassembler |
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141 prints these with a leading 'a'. */ |
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142 #define S390_OPERAND_AR 0x4 |
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143 |
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144 /* This operand names a control register. The disassembler |
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145 prints these with a leading 'c'. */ |
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146 #define S390_OPERAND_CR 0x8 |
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147 |
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148 /* This operand is a displacement. */ |
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149 #define S390_OPERAND_DISP 0x10 |
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150 |
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151 /* This operand names a base register. */ |
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152 #define S390_OPERAND_BASE 0x20 |
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153 |
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154 /* This operand names an index register, it can be skipped. */ |
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155 #define S390_OPERAND_INDEX 0x40 |
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156 |
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157 /* This operand is a relative branch displacement. The disassembler |
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158 prints these symbolically if possible. */ |
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159 #define S390_OPERAND_PCREL 0x80 |
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160 |
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161 /* This operand takes signed values. */ |
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162 #define S390_OPERAND_SIGNED 0x100 |
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163 |
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164 /* This operand is a length. */ |
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165 #define S390_OPERAND_LENGTH 0x200 |
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166 |
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167 /* This operand is optional. Only a single operand at the end of |
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168 the instruction may be optional. */ |
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169 #define S390_OPERAND_OPTIONAL 0x400 |
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170 |
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171 #endif /* S390_H */ |
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172 |
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173 |
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174 static int init_flag = 0; |
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175 static int opc_index[256]; |
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176 static int current_arch_mask = 0; |
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177 |
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178 /* Set up index table for first opcode byte. */ |
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179 |
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180 static void |
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181 init_disasm (struct disassemble_info *info) |
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182 { |
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183 const struct s390_opcode *opcode; |
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184 const struct s390_opcode *opcode_end; |
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185 |
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186 memset (opc_index, 0, sizeof (opc_index)); |
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187 opcode_end = s390_opcodes + s390_num_opcodes; |
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188 for (opcode = s390_opcodes; opcode < opcode_end; opcode++) |
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189 { |
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190 opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; |
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191 while ((opcode < opcode_end) && |
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192 (opcode[1].opcode[0] == opcode->opcode[0])) |
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193 opcode++; |
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194 } |
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195 // switch (info->mach) |
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196 // { |
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197 // case bfd_mach_s390_31: |
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198 current_arch_mask = 1 << S390_OPCODE_ESA; |
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199 // break; |
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200 // case bfd_mach_s390_64: |
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201 // current_arch_mask = 1 << S390_OPCODE_ZARCH; |
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202 // break; |
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203 // default: |
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204 // abort (); |
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205 // } |
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206 init_flag = 1; |
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207 } |
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208 |
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209 /* Extracts an operand value from an instruction. */ |
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210 |
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211 static inline unsigned int |
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212 s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) |
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213 { |
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214 unsigned int val; |
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215 int bits; |
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216 |
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217 /* Extract fragments of the operand byte for byte. */ |
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218 insn += operand->shift / 8; |
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219 bits = (operand->shift & 7) + operand->bits; |
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220 val = 0; |
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221 do |
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222 { |
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223 val <<= 8; |
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224 val |= (unsigned int) *insn++; |
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225 bits -= 8; |
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226 } |
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227 while (bits > 0); |
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228 val >>= -bits; |
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229 val &= ((1U << (operand->bits - 1)) << 1) - 1; |
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230 |
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231 /* Check for special long displacement case. */ |
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232 if (operand->bits == 20 && operand->shift == 20) |
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233 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; |
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234 |
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235 /* Sign extend value if the operand is signed or pc relative. */ |
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236 if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) |
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237 && (val & (1U << (operand->bits - 1)))) |
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238 val |= (-1U << (operand->bits - 1)) << 1; |
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239 |
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240 /* Double value if the operand is pc relative. */ |
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241 if (operand->flags & S390_OPERAND_PCREL) |
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242 val <<= 1; |
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243 |
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244 /* Length x in an instructions has real length x + 1. */ |
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245 if (operand->flags & S390_OPERAND_LENGTH) |
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246 val++; |
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247 return val; |
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248 } |
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249 |
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250 /* Print a S390 instruction. */ |
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251 |
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252 int |
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253 print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) |
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254 { |
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255 bfd_byte buffer[6]; |
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256 const struct s390_opcode *opcode; |
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257 const struct s390_opcode *opcode_end; |
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258 unsigned int value; |
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259 int status, opsize, bufsize; |
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260 char separator; |
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261 |
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262 if (init_flag == 0) |
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263 init_disasm (info); |
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264 |
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265 /* The output looks better if we put 6 bytes on a line. */ |
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266 info->bytes_per_line = 6; |
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267 |
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268 /* Every S390 instruction is max 6 bytes long. */ |
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269 memset (buffer, 0, 6); |
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270 status = (*info->read_memory_func) (memaddr, buffer, 6, info); |
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271 if (status != 0) |
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272 { |
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273 for (bufsize = 0; bufsize < 6; bufsize++) |
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274 if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) |
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275 break; |
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276 if (bufsize <= 0) |
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277 { |
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278 (*info->memory_error_func) (status, memaddr, info); |
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279 return -1; |
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280 } |
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281 /* Opsize calculation looks strange but it works |
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282 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes, |
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283 11xxxxxx -> 6 bytes. */ |
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284 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; |
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285 status = opsize > bufsize; |
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286 } |
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287 else |
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288 { |
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289 bufsize = 6; |
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290 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; |
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291 } |
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292 |
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293 if (status == 0) |
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294 { |
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295 /* Find the first match in the opcode table. */ |
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296 opcode_end = s390_opcodes + s390_num_opcodes; |
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297 for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; |
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298 (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); |
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299 opcode++) |
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300 { |
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301 const struct s390_operand *operand; |
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302 const unsigned char *opindex; |
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303 |
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304 /* Check architecture. */ |
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305 if (!(opcode->modes & current_arch_mask)) |
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306 continue; |
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307 /* Check signature of the opcode. */ |
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308 if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] |
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309 || (buffer[2] & opcode->mask[2]) != opcode->opcode[2] |
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310 || (buffer[3] & opcode->mask[3]) != opcode->opcode[3] |
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311 || (buffer[4] & opcode->mask[4]) != opcode->opcode[4] |
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312 || (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) |
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313 continue; |
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314 |
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315 /* The instruction is valid. */ |
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316 if (opcode->operands[0] != 0) |
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317 (*info->fprintf_func) (info->stream, "%s\t", opcode->name); |
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318 else |
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319 (*info->fprintf_func) (info->stream, "%s", opcode->name); |
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320 |
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321 /* Extract the operands. */ |
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322 separator = 0; |
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323 for (opindex = opcode->operands; *opindex != 0; opindex++) |
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324 { |
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325 unsigned int value; |
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326 |
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327 operand = s390_operands + *opindex; |
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328 value = s390_extract_operand (buffer, operand); |
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329 |
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330 if ((operand->flags & S390_OPERAND_INDEX) && value == 0) |
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331 continue; |
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332 if ((operand->flags & S390_OPERAND_BASE) && |
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333 value == 0 && separator == '(') |
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334 { |
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335 separator = ','; |
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336 continue; |
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337 } |
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338 |
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339 if (separator) |
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340 (*info->fprintf_func) (info->stream, "%c", separator); |
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341 |
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342 if (operand->flags & S390_OPERAND_GPR) |
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343 (*info->fprintf_func) (info->stream, "%%r%i", value); |
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344 else if (operand->flags & S390_OPERAND_FPR) |
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345 (*info->fprintf_func) (info->stream, "%%f%i", value); |
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346 else if (operand->flags & S390_OPERAND_AR) |
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347 (*info->fprintf_func) (info->stream, "%%a%i", value); |
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348 else if (operand->flags & S390_OPERAND_CR) |
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349 (*info->fprintf_func) (info->stream, "%%c%i", value); |
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350 else if (operand->flags & S390_OPERAND_PCREL) |
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351 (*info->print_address_func) (memaddr + (int) value, info); |
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352 else if (operand->flags & S390_OPERAND_SIGNED) |
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353 (*info->fprintf_func) (info->stream, "%i", (int) value); |
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354 else |
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355 (*info->fprintf_func) (info->stream, "%u", value); |
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356 |
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357 if (operand->flags & S390_OPERAND_DISP) |
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358 { |
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359 separator = '('; |
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360 } |
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361 else if (operand->flags & S390_OPERAND_BASE) |
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362 { |
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363 (*info->fprintf_func) (info->stream, ")"); |
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364 separator = ','; |
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365 } |
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366 else |
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367 separator = ','; |
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368 } |
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369 |
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370 /* Found instruction, printed it, return its size. */ |
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371 return opsize; |
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372 } |
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373 /* No matching instruction found, fall through to hex print. */ |
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374 } |
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375 |
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376 if (bufsize >= 4) |
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377 { |
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378 value = (unsigned int) buffer[0]; |
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379 value = (value << 8) + (unsigned int) buffer[1]; |
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380 value = (value << 8) + (unsigned int) buffer[2]; |
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381 value = (value << 8) + (unsigned int) buffer[3]; |
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382 (*info->fprintf_func) (info->stream, ".long\t0x%08x", value); |
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383 return 4; |
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384 } |
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385 else if (bufsize >= 2) |
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386 { |
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387 value = (unsigned int) buffer[0]; |
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388 value = (value << 8) + (unsigned int) buffer[1]; |
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389 (*info->fprintf_func) (info->stream, ".short\t0x%04x", value); |
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390 return 2; |
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391 } |
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392 else |
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393 { |
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394 value = (unsigned int) buffer[0]; |
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395 (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value); |
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396 return 1; |
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397 } |
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398 } |
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399 /* s390-opc.c -- S390 opcode list |
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400 Copyright 2000, 2001, 2003 Free Software Foundation, Inc. |
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401 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
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402 |
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403 This file is part of GDB, GAS, and the GNU binutils. |
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404 |
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405 This program is free software; you can redistribute it and/or modify |
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406 it under the terms of the GNU General Public License as published by |
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407 the Free Software Foundation; either version 2 of the License, or |
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408 (at your option) any later version. |
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409 |
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410 This program is distributed in the hope that it will be useful, |
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411 but WITHOUT ANY WARRANTY; without even the implied warranty of |
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412 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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413 GNU General Public License for more details. |
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414 |
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415 You should have received a copy of the GNU General Public License |
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416 along with this program; if not, write to the Free Software |
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417 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
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418 02110-1301, USA. */ |
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419 |
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420 #include <stdio.h> |
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421 |
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422 /* This file holds the S390 opcode table. The opcode table |
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423 includes almost all of the extended instruction mnemonics. This |
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424 permits the disassembler to use them, and simplifies the assembler |
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425 logic, at the cost of increasing the table size. The table is |
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426 strictly constant data, so the compiler should be able to put it in |
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427 the .text section. |
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428 |
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429 This file also holds the operand table. All knowledge about |
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430 inserting operands into instructions and vice-versa is kept in this |
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431 file. */ |
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432 |
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433 /* The operands table. |
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434 The fields are bits, shift, insert, extract, flags. */ |
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435 |
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436 const struct s390_operand s390_operands[] = |
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437 { |
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438 #define UNUSED 0 |
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439 { 0, 0, 0 }, /* Indicates the end of the operand list */ |
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440 |
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441 #define R_8 1 /* GPR starting at position 8 */ |
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442 { 4, 8, S390_OPERAND_GPR }, |
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443 #define R_12 2 /* GPR starting at position 12 */ |
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444 { 4, 12, S390_OPERAND_GPR }, |
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445 #define R_16 3 /* GPR starting at position 16 */ |
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446 { 4, 16, S390_OPERAND_GPR }, |
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447 #define R_20 4 /* GPR starting at position 20 */ |
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448 { 4, 20, S390_OPERAND_GPR }, |
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449 #define R_24 5 /* GPR starting at position 24 */ |
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450 { 4, 24, S390_OPERAND_GPR }, |
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451 #define R_28 6 /* GPR starting at position 28 */ |
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452 { 4, 28, S390_OPERAND_GPR }, |
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453 #define R_32 7 /* GPR starting at position 32 */ |
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454 { 4, 32, S390_OPERAND_GPR }, |
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455 |
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456 #define F_8 8 /* FPR starting at position 8 */ |
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457 { 4, 8, S390_OPERAND_FPR }, |
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458 #define F_12 9 /* FPR starting at position 12 */ |
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459 { 4, 12, S390_OPERAND_FPR }, |
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460 #define F_16 10 /* FPR starting at position 16 */ |
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461 { 4, 16, S390_OPERAND_FPR }, |
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462 #define F_20 11 /* FPR starting at position 16 */ |
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463 { 4, 16, S390_OPERAND_FPR }, |
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464 #define F_24 12 /* FPR starting at position 24 */ |
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465 { 4, 24, S390_OPERAND_FPR }, |
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466 #define F_28 13 /* FPR starting at position 28 */ |
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467 { 4, 28, S390_OPERAND_FPR }, |
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468 #define F_32 14 /* FPR starting at position 32 */ |
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469 { 4, 32, S390_OPERAND_FPR }, |
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470 |
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471 #define A_8 15 /* Access reg. starting at position 8 */ |
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472 { 4, 8, S390_OPERAND_AR }, |
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473 #define A_12 16 /* Access reg. starting at position 12 */ |
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474 { 4, 12, S390_OPERAND_AR }, |
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475 #define A_24 17 /* Access reg. starting at position 24 */ |
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476 { 4, 24, S390_OPERAND_AR }, |
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477 #define A_28 18 /* Access reg. starting at position 28 */ |
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478 { 4, 28, S390_OPERAND_AR }, |
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479 |
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480 #define C_8 19 /* Control reg. starting at position 8 */ |
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481 { 4, 8, S390_OPERAND_CR }, |
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482 #define C_12 20 /* Control reg. starting at position 12 */ |
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483 { 4, 12, S390_OPERAND_CR }, |
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484 |
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485 #define B_16 21 /* Base register starting at position 16 */ |
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486 { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
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487 #define B_32 22 /* Base register starting at position 32 */ |
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488 { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
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489 |
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490 #define X_12 23 /* Index register starting at position 12 */ |
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491 { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, |
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492 |
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493 #define D_20 24 /* Displacement starting at position 20 */ |
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494 { 12, 20, S390_OPERAND_DISP }, |
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495 #define D_36 25 /* Displacement starting at position 36 */ |
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496 { 12, 36, S390_OPERAND_DISP }, |
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497 #define D20_20 26 /* 20 bit displacement starting at 20 */ |
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498 { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, |
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499 |
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500 #define L4_8 27 /* 4 bit length starting at position 8 */ |
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501 { 4, 8, S390_OPERAND_LENGTH }, |
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502 #define L4_12 28 /* 4 bit length starting at position 12 */ |
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503 { 4, 12, S390_OPERAND_LENGTH }, |
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504 #define L8_8 29 /* 8 bit length starting at position 8 */ |
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505 { 8, 8, S390_OPERAND_LENGTH }, |
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506 |
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507 #define U4_8 30 /* 4 bit unsigned value starting at 8 */ |
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508 { 4, 8, 0 }, |
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509 #define U4_12 31 /* 4 bit unsigned value starting at 12 */ |
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510 { 4, 12, 0 }, |
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511 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ |
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512 { 4, 16, 0 }, |
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513 #define U4_20 33 /* 4 bit unsigned value starting at 20 */ |
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514 { 4, 20, 0 }, |
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515 #define U8_8 34 /* 8 bit unsigned value starting at 8 */ |
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516 { 8, 8, 0 }, |
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517 #define U8_16 35 /* 8 bit unsigned value starting at 16 */ |
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518 { 8, 16, 0 }, |
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519 #define I16_16 36 /* 16 bit signed value starting at 16 */ |
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520 { 16, 16, S390_OPERAND_SIGNED }, |
|
521 #define U16_16 37 /* 16 bit unsigned value starting at 16 */ |
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522 { 16, 16, 0 }, |
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523 #define J16_16 38 /* PC relative jump offset at 16 */ |
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524 { 16, 16, S390_OPERAND_PCREL }, |
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525 #define J32_16 39 /* PC relative long offset at 16 */ |
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526 { 32, 16, S390_OPERAND_PCREL }, |
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527 #define I32_16 40 /* 32 bit signed value starting at 16 */ |
|
528 { 32, 16, S390_OPERAND_SIGNED }, |
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529 #define U32_16 41 /* 32 bit unsigned value starting at 16 */ |
|
530 { 32, 16, 0 }, |
|
531 #define M_16 42 /* 4 bit optional mask starting at 16 */ |
|
532 { 4, 16, S390_OPERAND_OPTIONAL }, |
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533 #define RO_28 43 /* optional GPR starting at position 28 */ |
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534 { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) } |
|
535 |
|
536 }; |
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537 |
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538 |
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539 /* Macros used to form opcodes. */ |
|
540 |
|
541 /* 8/16/48 bit opcodes. */ |
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542 #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
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543 #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
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544 #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ |
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545 (x >> 16) & 255, (x >> 8) & 255, x & 255} |
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546 |
|
547 /* The new format of the INSTR_x_y and MASK_x_y defines is based |
|
548 on the following rules: |
|
549 1) the middle part of the definition (x in INSTR_x_y) is the official |
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550 names of the instruction format that you can find in the principals |
|
551 of operation. |
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552 2) the last part of the definition (y in INSTR_x_y) gives you an idea |
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553 which operands the binary represenation of the instruction has. |
|
554 The meanings of the letters in y are: |
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555 a - access register |
|
556 c - control register |
|
557 d - displacement, 12 bit |
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558 f - floating pointer register |
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559 i - signed integer, 4, 8, 16 or 32 bit |
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560 l - length, 4 or 8 bit |
|
561 p - pc relative |
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562 r - general purpose register |
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563 u - unsigned integer, 4, 8, 16 or 32 bit |
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564 m - mode field, 4 bit |
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565 0 - operand skipped. |
|
566 The order of the letters reflects the layout of the format in |
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567 storage and not the order of the paramaters of the instructions. |
|
568 The use of the letters is not a 100% match with the PoP but it is |
|
569 quite close. |
|
570 |
|
571 For example the instruction "mvo" is defined in the PoP as follows: |
|
572 |
|
573 MVO D1(L1,B1),D2(L2,B2) [SS] |
|
574 |
|
575 -------------------------------------- |
|
576 | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | |
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577 -------------------------------------- |
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578 0 8 12 16 20 32 36 |
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579 |
|
580 The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ |
|
581 |
|
582 #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ |
|
583 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ |
|
584 #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ |
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585 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ |
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586 #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ |
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587 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
|
588 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ |
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589 #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
|
590 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ |
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591 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ |
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592 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ |
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593 #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ |
|
594 #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ |
|
595 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ |
|
596 #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ |
|
597 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ |
|
598 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ |
|
599 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ |
|
600 #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ |
|
601 #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ |
|
602 #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ |
|
603 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ |
|
604 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
|
605 /* Actually efpc and sfpc do not take an optional operand. |
|
606 This is just a workaround for existing code e.g. glibc. */ |
|
607 #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ |
|
608 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
|
609 #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
|
610 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ |
|
611 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
|
612 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ |
|
613 #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ |
|
614 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ |
|
615 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ |
|
616 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
|
617 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ |
|
618 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ |
|
619 #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ |
|
620 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
|
621 #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ |
|
622 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ |
|
623 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ |
|
624 #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ |
|
625 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ |
|
626 #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
|
627 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
|
628 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ |
|
629 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
|
630 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ |
|
631 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
|
632 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
|
633 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ |
|
634 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
|
635 #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
|
636 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
|
637 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ |
|
638 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ |
|
639 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ |
|
640 #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ |
|
641 #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ |
|
642 #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ |
|
643 #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ |
|
644 #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ |
|
645 #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
|
646 #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ |
|
647 #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
|
648 #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ |
|
649 #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ |
|
650 #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ |
|
651 #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ |
|
652 #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
|
653 #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ |
|
654 #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ |
|
655 #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
|
656 #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
|
657 #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ |
|
658 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ |
|
659 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ |
|
660 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ |
|
661 #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ |
|
662 #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ |
|
663 #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
|
664 |
|
665 #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
666 #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
667 #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
668 #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
669 #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
670 #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
671 #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
672 #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
673 #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
674 #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
675 #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
676 #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
677 #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
|
678 #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } |
|
679 #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
680 #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
681 #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
|
682 #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
683 #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
|
684 #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
685 #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
686 #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
687 #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
688 #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
|
689 #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
|
690 #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
|
691 #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
|
692 #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
693 #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
694 #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
695 #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
|
696 #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
|
697 #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
698 #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
|
699 #define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
700 #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
|
701 #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
|
702 #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
703 #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
704 #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
705 #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
706 #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
707 #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
|
708 #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
709 #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
710 #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
711 #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
712 #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
713 #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
714 #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
715 #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
|
716 #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
717 #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
718 #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
719 #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
720 #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
721 #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
722 #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
723 #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
724 #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
725 #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
726 #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
727 #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
728 #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
|
729 #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
730 #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
731 #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
732 #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
733 #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
|
734 #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
|
735 #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
736 #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
737 #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
738 #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
739 #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
740 #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
|
741 #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
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742 #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
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743 #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
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744 #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
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745 |
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746 /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ |
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747 |
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748 const struct s390_opcode s390_opformats[] = |
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749 { |
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750 { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, |
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751 { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, |
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752 { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, |
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753 { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, |
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754 { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, |
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755 { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, |
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756 { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, |
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757 { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, |
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758 { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, |
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759 { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, |
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760 { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, |
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761 { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, |
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762 { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, |
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763 { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, |
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764 { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, |
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765 { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, |
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766 { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, |
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767 { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, |
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768 { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, |
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769 { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, |
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770 { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, |
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771 { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, |
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772 }; |
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773 |
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774 const int s390_num_opformats = |
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775 sizeof (s390_opformats) / sizeof (s390_opformats[0]); |
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776 |
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777 /* The opcode table. This file was generated by s390-mkopc. |
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778 |
|
779 The format of the opcode table is: |
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780 |
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781 NAME OPCODE MASK OPERANDS |
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782 |
|
783 Name is the name of the instruction. |
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784 OPCODE is the instruction opcode. |
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785 MASK is the opcode mask; this is used to tell the disassembler |
|
786 which bits in the actual opcode must match OPCODE. |
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787 OPERANDS is the list of operands. |
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788 |
|
789 The disassembler reads the table in order and prints the first |
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790 instruction which matches. */ |
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791 |
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792 const struct s390_opcode s390_opcodes[] = |
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793 { |
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794 { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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795 { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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796 { "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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797 { "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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798 { "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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799 { "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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800 { "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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801 { "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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802 { "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
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803 { "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0}, |
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804 { "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2}, |
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805 { "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0}, |
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806 { "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
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807 { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
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808 { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
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809 { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
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810 { "tgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
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811 { "tcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
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812 { "tgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
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813 { "tcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
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814 { "tget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
|
815 { "tcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
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816 { "srxt", OP48(0xed0000000049LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
|
817 { "slxt", OP48(0xed0000000048LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
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818 { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
|
819 { "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
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820 { "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
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821 { "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
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822 { "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
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823 { "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
|
824 { "my", OP48(0xed000000003bLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
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825 { "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
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826 { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
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827 { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
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828 { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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829 { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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830 { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
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831 { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
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832 { "lxe", OP48(0xed0000000026LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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833 { "lxd", OP48(0xed0000000025LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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834 { "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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835 { "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
|
836 { "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
|
837 { "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
838 { "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
839 { "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
840 { "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
841 { "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
842 { "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
843 { "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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844 { "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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845 { "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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846 { "tcxb", OP48(0xed0000000012LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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847 { "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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848 { "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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849 { "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
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850 { "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
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851 { "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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852 { "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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853 { "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
854 { "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
855 { "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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856 { "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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857 { "mxdb", OP48(0xed0000000007LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
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858 { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
859 { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
860 { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
|
861 { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2}, |
|
862 { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2}, |
|
863 { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0}, |
|
864 { "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3}, |
|
865 { "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3}, |
|
866 { "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
867 { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
868 { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
869 { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
870 { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
871 { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3}, |
|
872 { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0}, |
|
873 { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
|
874 { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
|
875 { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2}, |
|
876 { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
|
877 { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
|
878 { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
|
879 { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
|
880 { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
|
881 { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
|
882 { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
883 { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
884 { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
885 { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
886 { "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
887 { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
888 { "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
889 { "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
890 { "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
891 { "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3}, |
|
892 { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2}, |
|
893 { "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
|
894 { "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
|
895 { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2}, |
|
896 { "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
897 { "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
898 { "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3}, |
|
899 { "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2}, |
|
900 { "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
901 { "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
902 { "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
|
903 { "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
|
904 { "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2}, |
|
905 { "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3}, |
|
906 { "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2}, |
|
907 { "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
908 { "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
909 { "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
910 { "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
911 { "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
912 { "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
913 { "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
914 { "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
915 { "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
916 { "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
917 { "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
918 { "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
919 { "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
920 { "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
|
921 { "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
|
922 { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
923 { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0}, |
|
924 { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
925 { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
|
926 { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
|
927 { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
|
928 { "strag", OP48(0xe50000000002LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2}, |
|
929 { "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
|
930 { "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
|
931 { "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
932 { "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
|
933 { "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
934 { "dl", OP48(0xe30000000097LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
|
935 { "dl", OP48(0xe30000000097LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
936 { "ml", OP48(0xe30000000096LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
|
937 { "ml", OP48(0xe30000000096LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
938 { "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
|
939 { "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
|
940 { "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
941 { "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
942 { "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
943 { "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
944 { "lpq", OP48(0xe3000000008fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
945 { "lpq", OP48(0xe3000000008fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
946 { "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
947 { "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
948 { "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
949 { "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
950 { "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
951 { "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
952 { "dlg", OP48(0xe30000000087LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
953 { "dlg", OP48(0xe30000000087LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
954 { "mlg", OP48(0xe30000000086LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
955 { "mlg", OP48(0xe30000000086LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
956 { "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
957 { "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
958 { "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
959 { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
960 { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
961 { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
962 { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
963 { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
964 { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
965 { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
966 { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
967 { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
968 { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
969 { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
970 { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
971 { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
972 { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
973 { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
974 { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
975 { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
976 { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
977 { "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
978 { "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
979 { "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
980 { "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
981 { "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
982 { "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
983 { "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
984 { "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
985 { "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
986 { "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
987 { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
988 { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
|
989 { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
990 { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
991 { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
992 { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
993 { "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
994 { "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
995 { "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
996 { "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
997 { "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
998 { "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
999 { "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1000 { "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1001 { "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1002 { "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1003 { "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1004 { "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1005 { "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
|
1006 { "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
1007 { "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
|
1008 { "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
|
1009 { "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1010 { "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1011 { "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1012 { "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1013 { "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1014 { "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1015 { "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1016 { "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1017 { "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1018 { "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1019 { "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1020 { "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1021 { "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1022 { "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1023 { "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1024 { "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1025 { "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1026 { "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1027 { "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1028 { "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1029 { "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1030 { "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
|
1031 { "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1032 { "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1033 { "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1034 { "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1035 { "dsg", OP48(0xe3000000000dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1036 { "dsg", OP48(0xe3000000000dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1037 { "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1038 { "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1039 { "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1040 { "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1041 { "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1042 { "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1043 { "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1044 { "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1045 { "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1046 { "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1047 { "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1048 { "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1049 { "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1050 { "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
|
1051 { "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
|
1052 { "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
|
1053 { "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1054 { "pku", OP8(0xe1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1055 { "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1056 { "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1057 { "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1058 { "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1059 { "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0}, |
|
1060 { "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0}, |
|
1061 { "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0}, |
|
1062 { "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1063 { "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1064 { "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1065 { "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1066 { "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1067 { "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1068 { "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
|
1069 { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5}, |
|
1070 { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5}, |
|
1071 { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4}, |
|
1072 { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1073 { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1074 { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
|
1075 { "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
|
1076 { "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1077 { "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1078 { "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
|
1079 { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
|
1080 { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1081 { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1082 { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1083 { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1084 { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1085 { "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1086 { "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1087 { "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1088 { "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1089 { "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1090 { "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1091 { "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1092 { "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1093 { "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1094 { "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1095 { "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1096 { "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1097 { "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1098 { "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1099 { "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1100 { "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1101 { "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1102 { "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
|
1103 { "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1104 { "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1105 { "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1106 { "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1107 { "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1108 { "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1109 { "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1110 { "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1111 { "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1112 { "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
|
1113 { "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2}, |
|
1114 { "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2}, |
|
1115 { "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
|
1116 { "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2}, |
|
1117 { "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0}, |
|
1118 { "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0}, |
|
1119 { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0}, |
|
1120 { "cds", OP8(0xbbLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1121 { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1122 { "cu42", OP16(0xb9b3LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1123 { "cu41", OP16(0xb9b2LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1124 { "cu24", OP16(0xb9b1LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1125 { "cu14", OP16(0xb9b0LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1126 { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 4}, |
|
1127 { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2}, |
|
1128 { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
|
1129 { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
|
1130 { "dlr", OP16(0xb997LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
|
1131 { "mlr", OP16(0xb996LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
|
1132 { "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1133 { "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1134 { "troo", OP16(0xb993LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
|
1135 { "troo", OP16(0xb993LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1136 { "trot", OP16(0xb992LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
|
1137 { "trot", OP16(0xb992LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1138 { "trto", OP16(0xb991LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
|
1139 { "trto", OP16(0xb991LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1140 { "trtt", OP16(0xb990LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
|
1141 { "trtt", OP16(0xb990LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1142 { "idte", OP16(0xb98eLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 3}, |
|
1143 { "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
|
1144 { "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3}, |
|
1145 { "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1146 { "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1147 { "dlgr", OP16(0xb987LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1148 { "mlgr", OP16(0xb986LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1149 { "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1150 { "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1151 { "flogr", OP16(0xb983LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1152 { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1153 { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1154 { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1155 { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1156 { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
|
1157 { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
|
1158 { "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1159 { "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1160 { "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
|
1161 { "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
|
1162 { "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1163 { "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1164 { "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1165 { "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1166 { "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1167 { "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
|
1168 { "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
|
1169 { "dsgfr", OP16(0xb91dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1170 { "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1171 { "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1172 { "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1173 { "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1174 { "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1175 { "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1176 { "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1177 { "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1178 { "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1179 { "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1180 { "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1181 { "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1182 { "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1183 { "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1184 { "dsgr", OP16(0xb90dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1185 { "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1186 { "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1187 { "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1188 { "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1189 { "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1190 { "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1191 { "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
|
1192 { "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1193 { "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1194 { "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1195 { "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1196 { "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1197 { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1198 { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0}, |
|
1199 { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0}, |
|
1200 { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
|
1201 { "iextr", OP16(0xb3feLL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5}, |
|
1202 { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
|
1203 { "cextr", OP16(0xb3fcLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1204 { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
|
1205 { "cxutr", OP16(0xb3faLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
|
1206 { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
|
1207 { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
|
1208 { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5}, |
|
1209 { "qadtr", OP16(0xb3f5LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
|
1210 { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1211 { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
|
1212 { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
|
1213 { "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
|
1214 { "esxtr", OP16(0xb3efLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1215 { "eextr", OP16(0xb3edLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1216 { "cxtr", OP16(0xb3ecLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1217 { "csxtr", OP16(0xb3ebLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1218 { "cuxtr", OP16(0xb3eaLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1219 { "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5}, |
|
1220 { "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1221 { "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1222 { "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1223 { "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1224 { "csdtr", OP16(0xb3e3LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1225 { "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1226 { "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5}, |
|
1227 { "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1228 { "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
|
1229 { "ltxtr", OP16(0xb3deLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1230 { "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
|
1231 { "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5}, |
|
1232 { "sxtr", OP16(0xb3dbLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1233 { "axtr", OP16(0xb3daLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1234 { "dxtr", OP16(0xb3d9LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1235 { "mxtr", OP16(0xb3d8LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1236 { "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
|
1237 { "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1238 { "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
|
1239 { "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5}, |
|
1240 { "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1241 { "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1242 { "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1243 { "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
|
1244 { "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
|
1245 { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1246 { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1247 { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1248 { "cxgr", OP16(0xb3c6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1249 { "cdgr", OP16(0xb3c5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1250 { "cegr", OP16(0xb3c4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1251 { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
|
1252 { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1253 { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1254 { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1255 { "cxfr", OP16(0xb3b6LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
|
1256 { "cdfr", OP16(0xb3b5LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
|
1257 { "cefr", OP16(0xb3b4LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
|
1258 { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1259 { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1260 { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
|
1261 { "cxgbr", OP16(0xb3a6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1262 { "cdgbr", OP16(0xb3a5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1263 { "cegbr", OP16(0xb3a4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
|
1264 { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, |
|
1265 { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, |
|
1266 { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, |
|
1267 { "cxfbr", OP16(0xb396LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
|
1268 { "cdfbr", OP16(0xb395LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
|
1269 { "cefbr", OP16(0xb394LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
|
1270 { "efpc", OP16(0xb38cLL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0}, |
|
1271 { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5}, |
|
1272 { "sfpc", OP16(0xb384LL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0}, |
|
1273 { "fidr", OP16(0xb37fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1274 { "fier", OP16(0xb377LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1275 { "lzxr", OP16(0xb376LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1276 { "lzdr", OP16(0xb375LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1277 { "lzer", OP16(0xb374LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1278 { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1279 { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5}, |
|
1280 { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1281 { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
|
1282 { "cxr", OP16(0xb369LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1283 { "fixr", OP16(0xb367LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1284 { "lexr", OP16(0xb366LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1285 { "lxr", OP16(0xb365LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1286 { "lcxr", OP16(0xb363LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1287 { "ltxr", OP16(0xb362LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1288 { "lnxr", OP16(0xb361LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1289 { "lpxr", OP16(0xb360LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1290 { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1291 { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0}, |
|
1292 { "thdr", OP16(0xb359LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1293 { "thder", OP16(0xb358LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1294 { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1295 { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0}, |
|
1296 { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1297 { "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1298 { "dxbr", OP16(0xb34dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1299 { "mxbr", OP16(0xb34cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1300 { "sxbr", OP16(0xb34bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1301 { "axbr", OP16(0xb34aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1302 { "cxbr", OP16(0xb349LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1303 { "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1304 { "fixbr", OP16(0xb347LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
|
1305 { "lexbr", OP16(0xb346LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1306 { "ldxbr", OP16(0xb345LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1307 { "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1308 { "lcxbr", OP16(0xb343LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1309 { "ltxbr", OP16(0xb342LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1310 { "lnxbr", OP16(0xb341LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1311 { "lpxbr", OP16(0xb340LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1312 { "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
|
1313 { "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
|
1314 { "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
|
1315 { "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
|
1316 { "myr", OP16(0xb33bLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
|
1317 { "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
|
1318 { "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
|
1319 { "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
|
1320 { "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1321 { "sqxr", OP16(0xb336LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1322 { "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
|
1323 { "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
|
1324 { "lxer", OP16(0xb326LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1325 { "lxdr", OP16(0xb325LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1326 { "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1327 { "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
|
1328 { "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
|
1329 { "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1330 { "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1331 { "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1332 { "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1333 { "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1334 { "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1335 { "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1336 { "sqxbr", OP16(0xb316LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1337 { "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1338 { "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1339 { "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1340 { "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1341 { "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1342 { "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1343 { "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
|
1344 { "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
|
1345 { "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1346 { "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1347 { "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1348 { "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1349 { "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1350 { "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1351 { "mxdbr", OP16(0xb307LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1352 { "lxebr", OP16(0xb306LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1353 { "lxdbr", OP16(0xb305LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1354 { "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1355 { "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1356 { "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1357 { "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1358 { "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
|
1359 { "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1360 { "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5}, |
|
1361 { "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5}, |
|
1362 { "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2}, |
|
1363 { "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2}, |
|
1364 { "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4}, |
|
1365 { "cu12", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1366 { "cutfu", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1367 { "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1368 { "cu21", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1369 { "cuutf", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1370 { "cuutf", OP16(0xb2a6LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1371 { "tre", OP16(0xb2a5LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1372 { "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1373 { "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1374 { "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1375 { "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1376 { "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4}, |
|
1377 { "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1378 { "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1379 { "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1380 { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1381 { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1382 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1383 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1384 { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1385 { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1386 { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1387 { "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1388 { "cuse", OP16(0xb257LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1389 { "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1390 { "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1391 { "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1392 { "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1393 { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0}, |
|
1394 { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0}, |
|
1395 { "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0}, |
|
1396 { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0}, |
|
1397 { "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1398 { "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1399 { "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1400 { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0}, |
|
1401 { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1402 { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1403 { "sqer", OP16(0xb245LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, |
|
1404 { "sqdr", OP16(0xb244LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, |
|
1405 { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1406 { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1407 { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1408 { "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1409 { "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1410 { "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1411 { "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1412 { "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1413 { "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1414 { "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1415 { "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1416 { "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1417 { "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1418 { "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1419 { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1420 { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1421 { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1422 { "dxr", OP16(0xb22dLL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, |
|
1423 { "tb", OP16(0xb22cLL), MASK_RRE_0R, INSTR_RRE_0R, 3, 0}, |
|
1424 { "sske", OP16(0xb22bLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
|
1425 { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1426 { "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1427 { "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1428 { "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1429 { "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1430 { "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1431 { "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1432 { "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1433 { "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1434 { "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
|
1435 { "ipte", OP16(0xb221LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
|
1436 { "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1437 { "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1438 { "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1439 { "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1440 { "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1441 { "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1442 { "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1443 { "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1444 { "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0}, |
|
1445 { "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1446 { "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1447 { "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1448 { "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1449 { "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1450 { "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1451 { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1452 { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1453 { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1454 { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1455 { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1456 { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1457 { "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1458 { "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1459 { "mvcle", OP8(0xa8LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1460 { "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1461 { "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1462 { "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1463 { "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1464 { "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1465 { "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1466 { "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1467 { "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1468 { "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1469 { "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1470 { "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1471 { "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1472 { "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1473 { "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1474 { "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1475 { "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1476 { "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1477 { "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1478 { "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1479 { "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1480 { "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
|
1481 { "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
|
1482 { "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
|
1483 { "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
|
1484 { "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
|
1485 { "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
|
1486 { "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
|
1487 { "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
|
1488 { "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
|
1489 { "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2}, |
|
1490 { "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0}, |
|
1491 { "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0}, |
|
1492 { "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0}, |
|
1493 { "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1494 { "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1495 { "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
|
1496 { "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
|
1497 { "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
|
1498 { "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
|
1499 { "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1500 { "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1501 { "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1502 { "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1503 { "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1504 { "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1505 { "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1506 { "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1507 { "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1508 { "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1509 { "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1510 { "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1511 { "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1512 { "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1513 { "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1514 { "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
|
1515 { "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0}, |
|
1516 { "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0}, |
|
1517 { "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1518 { "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1519 { "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1520 { "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1521 { "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1522 { "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1523 { "ts", OP8(0x93LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1524 { "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1525 { "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
|
1526 { "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1527 { "slda", OP8(0x8fLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1528 { "srda", OP8(0x8eLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1529 { "sldl", OP8(0x8dLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1530 { "srdl", OP8(0x8cLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1531 { "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1532 { "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1533 { "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1534 { "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
|
1535 { "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1536 { "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1537 { "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0}, |
|
1538 { "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0}, |
|
1539 { "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
|
1540 { "lpsw", OP8(0x82LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1541 { "ssm", OP8(0x80LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
|
1542 { "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1543 { "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1544 { "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1545 { "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1546 { "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1547 { "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1548 { "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1549 { "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1550 { "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1551 { "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1552 { "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1553 { "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1554 { "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1555 { "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1556 { "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1557 { "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1558 { "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1559 { "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1560 { "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1561 { "mxd", OP8(0x67LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1562 { "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
|
1563 { "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1564 { "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1565 { "d", OP8(0x5dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1566 { "m", OP8(0x5cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1567 { "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1568 { "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1569 { "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1570 { "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1571 { "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1572 { "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1573 { "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1574 { "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1575 { "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1576 { "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1577 { "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1578 { "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1579 { "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1580 { "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1581 { "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1582 { "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1583 { "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1584 { "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1585 { "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1586 { "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1587 { "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1588 { "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1589 { "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1590 { "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1591 { "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1592 { "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1593 { "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1594 { "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1595 { "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1596 { "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1597 { "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1598 { "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1599 { "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1600 { "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1601 { "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1602 { "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1603 { "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1604 { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1605 { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1606 { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0}, |
|
1607 { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
|
1608 { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1609 { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1610 { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1611 { "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1612 { "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1613 { "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1614 { "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
|
1615 { "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1616 { "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1617 { "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1618 { "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1619 { "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1620 { "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1621 { "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1622 { "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1623 { "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1624 { "sxr", OP8(0x37LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1625 { "axr", OP8(0x36LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1626 { "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1627 { "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1628 { "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1629 { "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1630 { "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1631 { "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1632 { "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1633 { "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1634 { "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1635 { "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1636 { "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1637 { "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1638 { "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1639 { "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1640 { "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1641 { "mxdr", OP8(0x27LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1642 { "mxr", OP8(0x26LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1643 { "lrdr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1644 { "ldxr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1645 { "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1646 { "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1647 { "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1648 { "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1649 { "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
|
1650 { "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1651 { "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1652 { "dr", OP8(0x1dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1653 { "mr", OP8(0x1cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1654 { "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1655 { "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1656 { "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1657 { "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1658 { "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1659 { "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1660 { "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1661 { "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1662 { "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1663 { "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1664 { "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1665 { "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1666 { "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1667 { "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1668 { "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1669 { "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1670 { "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1671 { "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0}, |
|
1672 { "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1673 { "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1674 { "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1675 { "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1676 { "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1677 { "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1678 { "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1679 { "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1680 { "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1681 { "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1682 { "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1683 { "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1684 { "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1685 { "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1686 { "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1687 { "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1688 { "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1689 { "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1690 { "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1691 { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1692 { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1693 { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0}, |
|
1694 { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
|
1695 { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1696 { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
|
1697 { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0}, |
|
1698 { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0}, |
|
1699 { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2}, |
|
1700 { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2}, |
|
1701 { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2}, |
|
1702 { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2}, |
|
1703 { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5}, |
|
1704 { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0}, |
|
1705 { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0}, |
|
1706 { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0} |
|
1707 }; |
|
1708 |
|
1709 const int s390_num_opcodes = |
|
1710 sizeof (s390_opcodes) / sizeof (s390_opcodes[0]); |