1 #include "hw/hw.h"

     2 #include "hw/boards.h"

     3 

     4 void register_machines(void)

     5 {

     6     qemu_register_machine(&integratorcp_machine);

     7     qemu_register_machine(&versatilepb_machine);

     8     qemu_register_machine(&versatileab_machine);

     9     qemu_register_machine(&realview_machine);

    10     qemu_register_machine(&akitapda_machine);

    11     qemu_register_machine(&spitzpda_machine);

    12     qemu_register_machine(&borzoipda_machine);

    13     qemu_register_machine(&terrierpda_machine);

    14     qemu_register_machine(&sx1_machine_v1);

    15     qemu_register_machine(&sx1_machine_v2);

    16     qemu_register_machine(&palmte_machine);

    17     qemu_register_machine(&n800_machine);

    18     qemu_register_machine(&n810_machine);

    19     qemu_register_machine(&lm3s811evb_machine);

    20     qemu_register_machine(&lm3s6965evb_machine);

    21     qemu_register_machine(&connex_machine);

    22     qemu_register_machine(&verdex_machine);

    23     qemu_register_machine(&mainstone2_machine);

    24     qemu_register_machine(&musicpal_machine);

    25     qemu_register_machine(&tosapda_machine);

    26 }

    27 

    28 void cpu_save(QEMUFile *f, void *opaque)

    29 {

    30     int i;

    31     CPUARMState *env = (CPUARMState *)opaque;

    32 

    33     for (i = 0; i < 16; i++) {

    34         qemu_put_be32(f, env->regs[i]);

    35     }

    36     qemu_put_be32(f, cpsr_read(env));

    37     qemu_put_be32(f, env->spsr);

    38     for (i = 0; i < 6; i++) {

    39         qemu_put_be32(f, env->banked_spsr[i]);

    40         qemu_put_be32(f, env->banked_r13[i]);

    41         qemu_put_be32(f, env->banked_r14[i]);

    42     }

    43     for (i = 0; i < 5; i++) {

    44         qemu_put_be32(f, env->usr_regs[i]);

    45         qemu_put_be32(f, env->fiq_regs[i]);

    46     }

    47     qemu_put_be32(f, env->cp15.c0_cpuid);

    48     qemu_put_be32(f, env->cp15.c0_cachetype);

    49     qemu_put_be32(f, env->cp15.c0_cssel);

    50     qemu_put_be32(f, env->cp15.c1_sys);

    51     qemu_put_be32(f, env->cp15.c1_coproc);

    52     qemu_put_be32(f, env->cp15.c1_xscaleauxcr);

    53     qemu_put_be32(f, env->cp15.c2_base0);

    54     qemu_put_be32(f, env->cp15.c2_base1);

    55     qemu_put_be32(f, env->cp15.c2_control);

    56     qemu_put_be32(f, env->cp15.c2_mask);

    57     qemu_put_be32(f, env->cp15.c2_base_mask);

    58     qemu_put_be32(f, env->cp15.c2_data);

    59     qemu_put_be32(f, env->cp15.c2_insn);

    60     qemu_put_be32(f, env->cp15.c3);

    61     qemu_put_be32(f, env->cp15.c5_insn);

    62     qemu_put_be32(f, env->cp15.c5_data);

    63     for (i = 0; i < 8; i++) {

    64         qemu_put_be32(f, env->cp15.c6_region[i]);

    65     }

    66     qemu_put_be32(f, env->cp15.c6_insn);

    67     qemu_put_be32(f, env->cp15.c6_data);

    68     qemu_put_be32(f, env->cp15.c9_insn);

    69     qemu_put_be32(f, env->cp15.c9_data);

    70     qemu_put_be32(f, env->cp15.c13_fcse);

    71     qemu_put_be32(f, env->cp15.c13_context);

    72     qemu_put_be32(f, env->cp15.c13_tls1);

    73     qemu_put_be32(f, env->cp15.c13_tls2);

    74     qemu_put_be32(f, env->cp15.c13_tls3);

    75     qemu_put_be32(f, env->cp15.c15_cpar);

    76 

    77     qemu_put_be32(f, env->features);

    78 

    79     if (arm_feature(env, ARM_FEATURE_VFP)) {

    80         for (i = 0;  i < 16; i++) {

    81             CPU_DoubleU u;

    82             u.d = env->vfp.regs[i];

    83             qemu_put_be32(f, u.l.upper);

    84             qemu_put_be32(f, u.l.lower);

    85         }

    86         for (i = 0; i < 16; i++) {

    87             qemu_put_be32(f, env->vfp.xregs[i]);

    88         }

    89 

    90         /* TODO: Should use proper FPSCR access functions.  */

    91         qemu_put_be32(f, env->vfp.vec_len);

    92         qemu_put_be32(f, env->vfp.vec_stride);

    93 

    94         if (arm_feature(env, ARM_FEATURE_VFP3)) {

    95             for (i = 16;  i < 32; i++) {

    96                 CPU_DoubleU u;

    97                 u.d = env->vfp.regs[i];

    98                 qemu_put_be32(f, u.l.upper);

    99                 qemu_put_be32(f, u.l.lower);

   100             }

   101         }

   102     }

   103 

   104     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {

   105         for (i = 0; i < 16; i++) {

   106             qemu_put_be64(f, env->iwmmxt.regs[i]);

   107         }

   108         for (i = 0; i < 16; i++) {

   109             qemu_put_be32(f, env->iwmmxt.cregs[i]);

   110         }

   111     }

   112 

   113     if (arm_feature(env, ARM_FEATURE_M)) {

   114         qemu_put_be32(f, env->v7m.other_sp);

   115         qemu_put_be32(f, env->v7m.vecbase);

   116         qemu_put_be32(f, env->v7m.basepri);

   117         qemu_put_be32(f, env->v7m.control);

   118         qemu_put_be32(f, env->v7m.current_sp);

   119         qemu_put_be32(f, env->v7m.exception);

   120     }

   121 

   122     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {

   123         qemu_put_be32(f, env->teecr);

   124         qemu_put_be32(f, env->teehbr);

   125     }

   126 }

   127 

   128 int cpu_load(QEMUFile *f, void *opaque, int version_id)

   129 {

   130     CPUARMState *env = (CPUARMState *)opaque;

   131     int i;

   132     uint32_t val;

   133 

   134     if (version_id != CPU_SAVE_VERSION)

   135         return -EINVAL;

   136 

   137     for (i = 0; i < 16; i++) {

   138         env->regs[i] = qemu_get_be32(f);

   139     }

   140     val = qemu_get_be32(f);

   141     /* Avoid mode switch when restoring CPSR.  */

   142     env->uncached_cpsr = val & CPSR_M;

   143     cpsr_write(env, val, 0xffffffff);

   144     env->spsr = qemu_get_be32(f);

   145     for (i = 0; i < 6; i++) {

   146         env->banked_spsr[i] = qemu_get_be32(f);

   147         env->banked_r13[i] = qemu_get_be32(f);

   148         env->banked_r14[i] = qemu_get_be32(f);

   149     }

   150     for (i = 0; i < 5; i++) {

   151         env->usr_regs[i] = qemu_get_be32(f);

   152         env->fiq_regs[i] = qemu_get_be32(f);

   153     }

   154     env->cp15.c0_cpuid = qemu_get_be32(f);

   155     env->cp15.c0_cachetype = qemu_get_be32(f);

   156     env->cp15.c0_cssel = qemu_get_be32(f);

   157     env->cp15.c1_sys = qemu_get_be32(f);

   158     env->cp15.c1_coproc = qemu_get_be32(f);

   159     env->cp15.c1_xscaleauxcr = qemu_get_be32(f);

   160     env->cp15.c2_base0 = qemu_get_be32(f);

   161     env->cp15.c2_base1 = qemu_get_be32(f);

   162     env->cp15.c2_control = qemu_get_be32(f);

   163     env->cp15.c2_mask = qemu_get_be32(f);

   164     env->cp15.c2_base_mask = qemu_get_be32(f);

   165     env->cp15.c2_data = qemu_get_be32(f);

   166     env->cp15.c2_insn = qemu_get_be32(f);

   167     env->cp15.c3 = qemu_get_be32(f);

   168     env->cp15.c5_insn = qemu_get_be32(f);

   169     env->cp15.c5_data = qemu_get_be32(f);

   170     for (i = 0; i < 8; i++) {

   171         env->cp15.c6_region[i] = qemu_get_be32(f);

   172     }

   173     env->cp15.c6_insn = qemu_get_be32(f);

   174     env->cp15.c6_data = qemu_get_be32(f);

   175     env->cp15.c9_insn = qemu_get_be32(f);

   176     env->cp15.c9_data = qemu_get_be32(f);

   177     env->cp15.c13_fcse = qemu_get_be32(f);

   178     env->cp15.c13_context = qemu_get_be32(f);

   179     env->cp15.c13_tls1 = qemu_get_be32(f);

   180     env->cp15.c13_tls2 = qemu_get_be32(f);

   181     env->cp15.c13_tls3 = qemu_get_be32(f);

   182     env->cp15.c15_cpar = qemu_get_be32(f);

   183 

   184     env->features = qemu_get_be32(f);

   185 

   186     if (arm_feature(env, ARM_FEATURE_VFP)) {

   187         for (i = 0;  i < 16; i++) {

   188             CPU_DoubleU u;

   189             u.l.upper = qemu_get_be32(f);

   190             u.l.lower = qemu_get_be32(f);

   191             env->vfp.regs[i] = u.d;

   192         }

   193         for (i = 0; i < 16; i++) {

   194             env->vfp.xregs[i] = qemu_get_be32(f);

   195         }

   196 

   197         /* TODO: Should use proper FPSCR access functions.  */

   198         env->vfp.vec_len = qemu_get_be32(f);

   199         env->vfp.vec_stride = qemu_get_be32(f);

   200 

   201         if (arm_feature(env, ARM_FEATURE_VFP3)) {

   202             for (i = 0;  i < 16; i++) {

   203                 CPU_DoubleU u;

   204                 u.l.upper = qemu_get_be32(f);

   205                 u.l.lower = qemu_get_be32(f);

   206                 env->vfp.regs[i] = u.d;

   207             }

   208         }

   209     }

   210 

   211     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {

   212         for (i = 0; i < 16; i++) {

   213             env->iwmmxt.regs[i] = qemu_get_be64(f);

   214         }

   215         for (i = 0; i < 16; i++) {

   216             env->iwmmxt.cregs[i] = qemu_get_be32(f);

   217         }

   218     }

   219 

   220     if (arm_feature(env, ARM_FEATURE_M)) {

   221         env->v7m.other_sp = qemu_get_be32(f);

   222         env->v7m.vecbase = qemu_get_be32(f);

   223         env->v7m.basepri = qemu_get_be32(f);

   224         env->v7m.control = qemu_get_be32(f);

   225         env->v7m.current_sp = qemu_get_be32(f);

   226         env->v7m.exception = qemu_get_be32(f);

   227     }

   228 

   229     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {

   230         env->teecr = qemu_get_be32(f);

   231         env->teehbr = qemu_get_be32(f);

   232     }

   233 

   234     return 0;

   235 }