1 /*

     2  *  ARM translation

     3  *

     4  *  Copyright (c) 2003 Fabrice Bellard

     5  *  Copyright (c) 2005-2007 CodeSourcery

     6  *  Copyright (c) 2007 OpenedHand, Ltd.

     7  *

     8  * This library is free software; you can redistribute it and/or

     9  * modify it under the terms of the GNU Lesser General Public

    10  * License as published by the Free Software Foundation; either

    11  * version 2 of the License, or (at your option) any later version.

    12  *

    13  * This library is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    16  * Lesser General Public License for more details.

    17  *

    18  * You should have received a copy of the GNU Lesser General Public

    19  * License along with this library; if not, write to the Free Software

    20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    21  */

    22 #include <stdarg.h>

    23 #include <stdlib.h>

    24 #include <stdio.h>

    25 #include <string.h>

    26 #include <inttypes.h>

    27 

    28 #include "cpu.h"

    29 #include "exec-all.h"

    30 #include "disas.h"

    31 #include "tcg-op.h"

    32 #include "qemu-log.h"

    33 

    34 #include "helpers.h"

    35 #define GEN_HELPER 1

    36 #include "helpers.h"

    37 

    38 #define ENABLE_ARCH_5J    0

    39 #define ENABLE_ARCH_6     arm_feature(env, ARM_FEATURE_V6)

    40 #define ENABLE_ARCH_6K   arm_feature(env, ARM_FEATURE_V6K)

    41 #define ENABLE_ARCH_6T2   arm_feature(env, ARM_FEATURE_THUMB2)

    42 #define ENABLE_ARCH_7     arm_feature(env, ARM_FEATURE_V7)

    43 

    44 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)

    45 

    46 /* internal defines */

    47 typedef struct DisasContext {

    48     target_ulong pc;

    49     int is_jmp;

    50     /* Nonzero if this instruction has been conditionally skipped.  */

    51     int condjmp;

    52     /* The label that will be jumped to when the instruction is skipped.  */

    53     int condlabel;

    54     /* Thumb-2 condtional execution bits.  */

    55     int condexec_mask;

    56     int condexec_cond;

    57     struct TranslationBlock *tb;

    58     int singlestep_enabled;

    59     int thumb;

    60 #if !defined(CONFIG_USER_ONLY)

    61     int user;

    62 #endif

    63 } DisasContext;

    64 

    65 #if defined(CONFIG_USER_ONLY)

    66 #define IS_USER(s) 1

    67 #else

    68 #define IS_USER(s) (s->user)

    69 #endif

    70 

    71 /* These instructions trap after executing, so defer them until after the

    72    conditional executions state has been updated.  */

    73 #define DISAS_WFI 4

    74 #define DISAS_SWI 5

    75 

    76 static TCGv_ptr cpu_env;

    77 /* We reuse the same 64-bit temporaries for efficiency.  */

    78 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;

    79 

    80 /* FIXME:  These should be removed.  */

    81 static TCGv cpu_T[2];

    82 static TCGv cpu_F0s, cpu_F1s;

    83 static TCGv_i64 cpu_F0d, cpu_F1d;

    84 

    85 #define ICOUNT_TEMP cpu_T[0]

    86 #include "gen-icount.h"

    87 

    88 /* initialize TCG globals.  */

    89 void arm_translate_init(void)

    90 {

    91     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    92 

    93     cpu_T[0] = tcg_global_reg_new_i32(TCG_AREG1, "T0");

    94     cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1");

    95 

    96 #define GEN_HELPER 2

    97 #include "helpers.h"

    98 }

    99 

   100 /* The code generator doesn't like lots of temporaries, so maintain our own

   101    cache for reuse within a function.  */

   102 #define MAX_TEMPS 8

   103 static int num_temps;

   104 static TCGv temps[MAX_TEMPS];

   105 

   106 /* Allocate a temporary variable.  */

   107 static TCGv_i32 new_tmp(void)

   108 {

   109     TCGv tmp;

   110     if (num_temps == MAX_TEMPS)

   111         abort();

   112 

   113     if (GET_TCGV_I32(temps[num_temps]))

   114       return temps[num_temps++];

   115 

   116     tmp = tcg_temp_new_i32();

   117     temps[num_temps++] = tmp;

   118     return tmp;

   119 }

   120 

   121 /* Release a temporary variable.  */

   122 static void dead_tmp(TCGv tmp)

   123 {

   124     int i;

   125     num_temps--;

   126     i = num_temps;

   127     if (TCGV_EQUAL(temps[i], tmp))

   128         return;

   129 

   130     /* Shuffle this temp to the last slot.  */

   131     while (!TCGV_EQUAL(temps[i], tmp))

   132         i--;

   133     while (i < num_temps) {

   134         temps[i] = temps[i + 1];

   135         i++;

   136     }

   137     temps[i] = tmp;

   138 }

   139 

   140 static inline TCGv load_cpu_offset(int offset)

   141 {

   142     TCGv tmp = new_tmp();

   143     tcg_gen_ld_i32(tmp, cpu_env, offset);

   144     return tmp;

   145 }

   146 

   147 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))

   148 

   149 static inline void store_cpu_offset(TCGv var, int offset)

   150 {

   151     tcg_gen_st_i32(var, cpu_env, offset);

   152     dead_tmp(var);

   153 }

   154 

   155 #define store_cpu_field(var, name) \

   156     store_cpu_offset(var, offsetof(CPUState, name))

   157 

   158 /* Set a variable to the value of a CPU register.  */

   159 static void load_reg_var(DisasContext *s, TCGv var, int reg)

   160 {

   161     if (reg == 15) {

   162         uint32_t addr;

   163         /* normaly, since we updated PC, we need only to add one insn */

   164         if (s->thumb)

   165             addr = (long)s->pc + 2;

   166         else

   167             addr = (long)s->pc + 4;

   168         tcg_gen_movi_i32(var, addr);

   169     } else {

   170         tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg]));

   171     }

   172 }

   173 

   174 /* Create a new temporary and set it to the value of a CPU register.  */

   175 static inline TCGv load_reg(DisasContext *s, int reg)

   176 {

   177     TCGv tmp = new_tmp();

   178     load_reg_var(s, tmp, reg);

   179     return tmp;

   180 }

   181 

   182 /* Set a CPU register.  The source must be a temporary and will be

   183    marked as dead.  */

   184 static void store_reg(DisasContext *s, int reg, TCGv var)

   185 {

   186     if (reg == 15) {

   187         tcg_gen_andi_i32(var, var, ~1);

   188         s->is_jmp = DISAS_JUMP;

   189     }

   190     tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg]));

   191     dead_tmp(var);

   192 }

   193 

   194 

   195 /* Basic operations.  */

   196 #define gen_op_movl_T0_T1() tcg_gen_mov_i32(cpu_T[0], cpu_T[1])

   197 #define gen_op_movl_T0_im(im) tcg_gen_movi_i32(cpu_T[0], im)

   198 #define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im)

   199 

   200 #define gen_op_addl_T1_im(im) tcg_gen_addi_i32(cpu_T[1], cpu_T[1], im)

   201 #define gen_op_addl_T0_T1() tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1])

   202 #define gen_op_subl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1])

   203 #define gen_op_rsbl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[1], cpu_T[0])

   204 

   205 #define gen_op_addl_T0_T1_cc() gen_helper_add_cc(cpu_T[0], cpu_T[0], cpu_T[1])

   206 #define gen_op_adcl_T0_T1_cc() gen_helper_adc_cc(cpu_T[0], cpu_T[0], cpu_T[1])

   207 #define gen_op_subl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[0], cpu_T[1])

   208 #define gen_op_sbcl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[0], cpu_T[1])

   209 #define gen_op_rsbl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[1], cpu_T[0])

   210 #define gen_op_rscl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[1], cpu_T[0])

   211 

   212 #define gen_op_andl_T0_T1() tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1])

   213 #define gen_op_xorl_T0_T1() tcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_T[1])

   214 #define gen_op_orl_T0_T1() tcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1])

   215 #define gen_op_notl_T0() tcg_gen_not_i32(cpu_T[0], cpu_T[0])

   216 #define gen_op_notl_T1() tcg_gen_not_i32(cpu_T[1], cpu_T[1])

   217 #define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]);

   218 #define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]);

   219 

   220 #define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im)

   221 #define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im)

   222 

   223 /* Value extensions.  */

   224 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)

   225 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)

   226 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)

   227 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)

   228 

   229 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)

   230 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)

   231 

   232 #define gen_op_mul_T0_T1() tcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1])

   233 

   234 #define gen_set_cpsr(var, mask) gen_helper_cpsr_write(var, tcg_const_i32(mask))

   235 /* Set NZCV flags from the high 4 bits of var.  */

   236 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)

   237 

   238 static void gen_exception(int excp)

   239 {

   240     TCGv tmp = new_tmp();

   241     tcg_gen_movi_i32(tmp, excp);

   242     gen_helper_exception(tmp);

   243     dead_tmp(tmp);

   244 }

   245 

   246 static void gen_smul_dual(TCGv a, TCGv b)

   247 {

   248     TCGv tmp1 = new_tmp();

   249     TCGv tmp2 = new_tmp();

   250     tcg_gen_ext16s_i32(tmp1, a);

   251     tcg_gen_ext16s_i32(tmp2, b);

   252     tcg_gen_mul_i32(tmp1, tmp1, tmp2);

   253     dead_tmp(tmp2);

   254     tcg_gen_sari_i32(a, a, 16);

   255     tcg_gen_sari_i32(b, b, 16);

   256     tcg_gen_mul_i32(b, b, a);

   257     tcg_gen_mov_i32(a, tmp1);

   258     dead_tmp(tmp1);

   259 }

   260 

   261 /* Byteswap each halfword.  */

   262 static void gen_rev16(TCGv var)

   263 {

   264     TCGv tmp = new_tmp();

   265     tcg_gen_shri_i32(tmp, var, 8);

   266     tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);

   267     tcg_gen_shli_i32(var, var, 8);

   268     tcg_gen_andi_i32(var, var, 0xff00ff00);

   269     tcg_gen_or_i32(var, var, tmp);

   270     dead_tmp(tmp);

   271 }

   272 

   273 /* Byteswap low halfword and sign extend.  */

   274 static void gen_revsh(TCGv var)

   275 {

   276     TCGv tmp = new_tmp();

   277     tcg_gen_shri_i32(tmp, var, 8);

   278     tcg_gen_andi_i32(tmp, tmp, 0x00ff);

   279     tcg_gen_shli_i32(var, var, 8);

   280     tcg_gen_ext8s_i32(var, var);

   281     tcg_gen_or_i32(var, var, tmp);

   282     dead_tmp(tmp);

   283 }

   284 

   285 /* Unsigned bitfield extract.  */

   286 static void gen_ubfx(TCGv var, int shift, uint32_t mask)

   287 {

   288     if (shift)

   289         tcg_gen_shri_i32(var, var, shift);

   290     tcg_gen_andi_i32(var, var, mask);

   291 }

   292 

   293 /* Signed bitfield extract.  */

   294 static void gen_sbfx(TCGv var, int shift, int width)

   295 {

   296     uint32_t signbit;

   297 

   298     if (shift)

   299         tcg_gen_sari_i32(var, var, shift);

   300     if (shift + width < 32) {

   301         signbit = 1u << (width - 1);

   302         tcg_gen_andi_i32(var, var, (1u << width) - 1);

   303         tcg_gen_xori_i32(var, var, signbit);

   304         tcg_gen_subi_i32(var, var, signbit);

   305     }

   306 }

   307 

   308 /* Bitfield insertion.  Insert val into base.  Clobbers base and val.  */

   309 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)

   310 {

   311     tcg_gen_andi_i32(val, val, mask);

   312     tcg_gen_shli_i32(val, val, shift);

   313     tcg_gen_andi_i32(base, base, ~(mask << shift));

   314     tcg_gen_or_i32(dest, base, val);

   315 }

   316 

   317 /* Round the top 32 bits of a 64-bit value.  */

   318 static void gen_roundqd(TCGv a, TCGv b)

   319 {

   320     tcg_gen_shri_i32(a, a, 31);

   321     tcg_gen_add_i32(a, a, b);

   322 }

   323 

   324 /* FIXME: Most targets have native widening multiplication.

   325    It would be good to use that instead of a full wide multiply.  */

   326 /* 32x32->64 multiply.  Marks inputs as dead.  */

   327 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)

   328 {

   329     TCGv_i64 tmp1 = tcg_temp_new_i64();

   330     TCGv_i64 tmp2 = tcg_temp_new_i64();

   331 

   332     tcg_gen_extu_i32_i64(tmp1, a);

   333     dead_tmp(a);

   334     tcg_gen_extu_i32_i64(tmp2, b);

   335     dead_tmp(b);

   336     tcg_gen_mul_i64(tmp1, tmp1, tmp2);

   337     return tmp1;

   338 }

   339 

   340 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)

   341 {

   342     TCGv_i64 tmp1 = tcg_temp_new_i64();

   343     TCGv_i64 tmp2 = tcg_temp_new_i64();

   344 

   345     tcg_gen_ext_i32_i64(tmp1, a);

   346     dead_tmp(a);

   347     tcg_gen_ext_i32_i64(tmp2, b);

   348     dead_tmp(b);

   349     tcg_gen_mul_i64(tmp1, tmp1, tmp2);

   350     return tmp1;

   351 }

   352 

   353 /* Unsigned 32x32->64 multiply.  */

   354 static void gen_op_mull_T0_T1(void)

   355 {

   356     TCGv_i64 tmp1 = tcg_temp_new_i64();

   357     TCGv_i64 tmp2 = tcg_temp_new_i64();

   358 

   359     tcg_gen_extu_i32_i64(tmp1, cpu_T[0]);

   360     tcg_gen_extu_i32_i64(tmp2, cpu_T[1]);

   361     tcg_gen_mul_i64(tmp1, tmp1, tmp2);

   362     tcg_gen_trunc_i64_i32(cpu_T[0], tmp1);

   363     tcg_gen_shri_i64(tmp1, tmp1, 32);

   364     tcg_gen_trunc_i64_i32(cpu_T[1], tmp1);

   365 }

   366 

   367 /* Signed 32x32->64 multiply.  */

   368 static void gen_imull(TCGv a, TCGv b)

   369 {

   370     TCGv_i64 tmp1 = tcg_temp_new_i64();

   371     TCGv_i64 tmp2 = tcg_temp_new_i64();

   372 

   373     tcg_gen_ext_i32_i64(tmp1, a);

   374     tcg_gen_ext_i32_i64(tmp2, b);

   375     tcg_gen_mul_i64(tmp1, tmp1, tmp2);

   376     tcg_gen_trunc_i64_i32(a, tmp1);

   377     tcg_gen_shri_i64(tmp1, tmp1, 32);

   378     tcg_gen_trunc_i64_i32(b, tmp1);

   379 }

   380 

   381 /* Swap low and high halfwords.  */

   382 static void gen_swap_half(TCGv var)

   383 {

   384     TCGv tmp = new_tmp();

   385     tcg_gen_shri_i32(tmp, var, 16);

   386     tcg_gen_shli_i32(var, var, 16);

   387     tcg_gen_or_i32(var, var, tmp);

   388     dead_tmp(tmp);

   389 }

   390 

   391 /* Dual 16-bit add.  Result placed in t0 and t1 is marked as dead.

   392     tmp = (t0 ^ t1) & 0x8000;

   393     t0 &= ~0x8000;

   394     t1 &= ~0x8000;

   395     t0 = (t0 + t1) ^ tmp;

   396  */

   397 

   398 static void gen_add16(TCGv t0, TCGv t1)

   399 {

   400     TCGv tmp = new_tmp();

   401     tcg_gen_xor_i32(tmp, t0, t1);

   402     tcg_gen_andi_i32(tmp, tmp, 0x8000);

   403     tcg_gen_andi_i32(t0, t0, ~0x8000);

   404     tcg_gen_andi_i32(t1, t1, ~0x8000);

   405     tcg_gen_add_i32(t0, t0, t1);

   406     tcg_gen_xor_i32(t0, t0, tmp);

   407     dead_tmp(tmp);

   408     dead_tmp(t1);

   409 }

   410 

   411 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))

   412 

   413 /* Set CF to the top bit of var.  */

   414 static void gen_set_CF_bit31(TCGv var)

   415 {

   416     TCGv tmp = new_tmp();

   417     tcg_gen_shri_i32(tmp, var, 31);

   418     gen_set_CF(tmp);

   419     dead_tmp(tmp);

   420 }

   421 

   422 /* Set N and Z flags from var.  */

   423 static inline void gen_logic_CC(TCGv var)

   424 {

   425     tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));

   426     tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));

   427 }

   428 

   429 /* T0 += T1 + CF.  */

   430 static void gen_adc_T0_T1(void)

   431 {

   432     TCGv tmp;

   433     gen_op_addl_T0_T1();

   434     tmp = load_cpu_field(CF);

   435     tcg_gen_add_i32(cpu_T[0], cpu_T[0], tmp);

   436     dead_tmp(tmp);

   437 }

   438 

   439 /* dest = T0 - T1 + CF - 1.  */

   440 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)

   441 {

   442     TCGv tmp;

   443     tcg_gen_sub_i32(dest, t0, t1);

   444     tmp = load_cpu_field(CF);

   445     tcg_gen_add_i32(dest, dest, tmp);

   446     tcg_gen_subi_i32(dest, dest, 1);

   447     dead_tmp(tmp);

   448 }

   449 

   450 #define gen_sbc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[0], cpu_T[1])

   451 #define gen_rsc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[1], cpu_T[0])

   452 

   453 /* T0 &= ~T1.  Clobbers T1.  */

   454 /* FIXME: Implement bic natively.  */

   455 static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1)

   456 {

   457     TCGv tmp = new_tmp();

   458     tcg_gen_not_i32(tmp, t1);

   459     tcg_gen_and_i32(dest, t0, tmp);

   460     dead_tmp(tmp);

   461 }

   462 static inline void gen_op_bicl_T0_T1(void)

   463 {

   464     gen_op_notl_T1();

   465     gen_op_andl_T0_T1();

   466 }

   467 

   468 /* FIXME:  Implement this natively.  */

   469 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)

   470 

   471 /* FIXME:  Implement this natively.  */

   472 static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i)

   473 {

   474     TCGv tmp;

   475 

   476     if (i == 0)

   477         return;

   478 

   479     tmp = new_tmp();

   480     tcg_gen_shri_i32(tmp, t1, i);

   481     tcg_gen_shli_i32(t1, t1, 32 - i);

   482     tcg_gen_or_i32(t0, t1, tmp);

   483     dead_tmp(tmp);

   484 }

   485 

   486 static void shifter_out_im(TCGv var, int shift)

   487 {

   488     TCGv tmp = new_tmp();

   489     if (shift == 0) {

   490         tcg_gen_andi_i32(tmp, var, 1);

   491     } else {

   492         tcg_gen_shri_i32(tmp, var, shift);

   493         if (shift != 31)

   494             tcg_gen_andi_i32(tmp, tmp, 1);

   495     }

   496     gen_set_CF(tmp);

   497     dead_tmp(tmp);

   498 }

   499 

   500 /* Shift by immediate.  Includes special handling for shift == 0.  */

   501 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)

   502 {

   503     switch (shiftop) {

   504     case 0: /* LSL */

   505         if (shift != 0) {

   506             if (flags)

   507                 shifter_out_im(var, 32 - shift);

   508             tcg_gen_shli_i32(var, var, shift);

   509         }

   510         break;

   511     case 1: /* LSR */

   512         if (shift == 0) {

   513             if (flags) {

   514                 tcg_gen_shri_i32(var, var, 31);

   515                 gen_set_CF(var);

   516             }

   517             tcg_gen_movi_i32(var, 0);

   518         } else {

   519             if (flags)

   520                 shifter_out_im(var, shift - 1);

   521             tcg_gen_shri_i32(var, var, shift);

   522         }

   523         break;

   524     case 2: /* ASR */

   525         if (shift == 0)

   526             shift = 32;

   527         if (flags)

   528             shifter_out_im(var, shift - 1);

   529         if (shift == 32)

   530           shift = 31;

   531         tcg_gen_sari_i32(var, var, shift);

   532         break;

   533     case 3: /* ROR/RRX */

   534         if (shift != 0) {

   535             if (flags)

   536                 shifter_out_im(var, shift - 1);

   537             tcg_gen_rori_i32(var, var, shift); break;

   538         } else {

   539             TCGv tmp = load_cpu_field(CF);

   540             if (flags)

   541                 shifter_out_im(var, 0);

   542             tcg_gen_shri_i32(var, var, 1);

   543             tcg_gen_shli_i32(tmp, tmp, 31);

   544             tcg_gen_or_i32(var, var, tmp);

   545             dead_tmp(tmp);

   546         }

   547     }

   548 };

   549 

   550 static inline void gen_arm_shift_reg(TCGv var, int shiftop,

   551                                      TCGv shift, int flags)

   552 {

   553     if (flags) {

   554         switch (shiftop) {

   555         case 0: gen_helper_shl_cc(var, var, shift); break;

   556         case 1: gen_helper_shr_cc(var, var, shift); break;

   557         case 2: gen_helper_sar_cc(var, var, shift); break;

   558         case 3: gen_helper_ror_cc(var, var, shift); break;

   559         }

   560     } else {

   561         switch (shiftop) {

   562         case 0: gen_helper_shl(var, var, shift); break;

   563         case 1: gen_helper_shr(var, var, shift); break;

   564         case 2: gen_helper_sar(var, var, shift); break;

   565         case 3: gen_helper_ror(var, var, shift); break;

   566         }

   567     }

   568     dead_tmp(shift);

   569 }

   570 

   571 #define PAS_OP(pfx) \

   572     switch (op2) {  \

   573     case 0: gen_pas_helper(glue(pfx,add16)); break; \

   574     case 1: gen_pas_helper(glue(pfx,addsubx)); break; \

   575     case 2: gen_pas_helper(glue(pfx,subaddx)); break; \

   576     case 3: gen_pas_helper(glue(pfx,sub16)); break; \

   577     case 4: gen_pas_helper(glue(pfx,add8)); break; \

   578     case 7: gen_pas_helper(glue(pfx,sub8)); break; \

   579     }

   580 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)

   581 {

   582     TCGv_ptr tmp;

   583 

   584     switch (op1) {

   585 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)

   586     case 1:

   587         tmp = tcg_temp_new_ptr();

   588         tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

   589         PAS_OP(s)

   590         break;

   591     case 5:

   592         tmp = tcg_temp_new_ptr();

   593         tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

   594         PAS_OP(u)

   595         break;

   596 #undef gen_pas_helper

   597 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)

   598     case 2:

   599         PAS_OP(q);

   600         break;

   601     case 3:

   602         PAS_OP(sh);

   603         break;

   604     case 6:

   605         PAS_OP(uq);

   606         break;

   607     case 7:

   608         PAS_OP(uh);

   609         break;

   610 #undef gen_pas_helper

   611     }

   612 }

   613 #undef PAS_OP

   614 

   615 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings.  */

   616 #define PAS_OP(pfx) \

   617     switch (op2) {  \

   618     case 0: gen_pas_helper(glue(pfx,add8)); break; \

   619     case 1: gen_pas_helper(glue(pfx,add16)); break; \

   620     case 2: gen_pas_helper(glue(pfx,addsubx)); break; \

   621     case 4: gen_pas_helper(glue(pfx,sub8)); break; \

   622     case 5: gen_pas_helper(glue(pfx,sub16)); break; \

   623     case 6: gen_pas_helper(glue(pfx,subaddx)); break; \

   624     }

   625 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)

   626 {

   627     TCGv_ptr tmp;

   628 

   629     switch (op1) {

   630 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)

   631     case 0:

   632         tmp = tcg_temp_new_ptr();

   633         tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

   634         PAS_OP(s)

   635         break;

   636     case 4:

   637         tmp = tcg_temp_new_ptr();

   638         tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

   639         PAS_OP(u)

   640         break;

   641 #undef gen_pas_helper

   642 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)

   643     case 1:

   644         PAS_OP(q);

   645         break;

   646     case 2:

   647         PAS_OP(sh);

   648         break;

   649     case 5:

   650         PAS_OP(uq);

   651         break;

   652     case 6:

   653         PAS_OP(uh);

   654         break;

   655 #undef gen_pas_helper

   656     }

   657 }

   658 #undef PAS_OP

   659 

   660 static void gen_test_cc(int cc, int label)

   661 {

   662     TCGv tmp;

   663     TCGv tmp2;

   664     int inv;

   665 

   666     switch (cc) {

   667     case 0: /* eq: Z */

   668         tmp = load_cpu_field(ZF);

   669         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

   670         break;

   671     case 1: /* ne: !Z */

   672         tmp = load_cpu_field(ZF);

   673         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

   674         break;

   675     case 2: /* cs: C */

   676         tmp = load_cpu_field(CF);

   677         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

   678         break;

   679     case 3: /* cc: !C */

   680         tmp = load_cpu_field(CF);

   681         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

   682         break;

   683     case 4: /* mi: N */

   684         tmp = load_cpu_field(NF);

   685         tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

   686         break;

   687     case 5: /* pl: !N */

   688         tmp = load_cpu_field(NF);

   689         tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

   690         break;

   691     case 6: /* vs: V */

   692         tmp = load_cpu_field(VF);

   693         tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

   694         break;

   695     case 7: /* vc: !V */

   696         tmp = load_cpu_field(VF);

   697         tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

   698         break;

   699     case 8: /* hi: C && !Z */

   700         inv = gen_new_label();

   701         tmp = load_cpu_field(CF);

   702         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);

   703         dead_tmp(tmp);

   704         tmp = load_cpu_field(ZF);

   705         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

   706         gen_set_label(inv);

   707         break;

   708     case 9: /* ls: !C || Z */

   709         tmp = load_cpu_field(CF);

   710         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

   711         dead_tmp(tmp);

   712         tmp = load_cpu_field(ZF);

   713         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

   714         break;

   715     case 10: /* ge: N == V -> N ^ V == 0 */

   716         tmp = load_cpu_field(VF);

   717         tmp2 = load_cpu_field(NF);

   718         tcg_gen_xor_i32(tmp, tmp, tmp2);

   719         dead_tmp(tmp2);

   720         tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

   721         break;

   722     case 11: /* lt: N != V -> N ^ V != 0 */

   723         tmp = load_cpu_field(VF);

   724         tmp2 = load_cpu_field(NF);

   725         tcg_gen_xor_i32(tmp, tmp, tmp2);

   726         dead_tmp(tmp2);

   727         tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

   728         break;

   729     case 12: /* gt: !Z && N == V */

   730         inv = gen_new_label();

   731         tmp = load_cpu_field(ZF);

   732         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);

   733         dead_tmp(tmp);

   734         tmp = load_cpu_field(VF);

   735         tmp2 = load_cpu_field(NF);

   736         tcg_gen_xor_i32(tmp, tmp, tmp2);

   737         dead_tmp(tmp2);

   738         tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

   739         gen_set_label(inv);

   740         break;

   741     case 13: /* le: Z || N != V */

   742         tmp = load_cpu_field(ZF);

   743         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

   744         dead_tmp(tmp);

   745         tmp = load_cpu_field(VF);

   746         tmp2 = load_cpu_field(NF);

   747         tcg_gen_xor_i32(tmp, tmp, tmp2);

   748         dead_tmp(tmp2);

   749         tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

   750         break;

   751     default:

   752         fprintf(stderr, "Bad condition code 0x%x\n", cc);

   753         abort();

   754     }

   755     dead_tmp(tmp);

   756 }

   757 

   758 static const uint8_t table_logic_cc[16] = {

   759     1, /* and */

   760     1, /* xor */

   761     0, /* sub */

   762     0, /* rsb */

   763     0, /* add */

   764     0, /* adc */

   765     0, /* sbc */

   766     0, /* rsc */

   767     1, /* andl */

   768     1, /* xorl */

   769     0, /* cmp */

   770     0, /* cmn */

   771     1, /* orr */

   772     1, /* mov */

   773     1, /* bic */

   774     1, /* mvn */

   775 };

   776 

   777 /* Set PC and Thumb state from an immediate address.  */

   778 static inline void gen_bx_im(DisasContext *s, uint32_t addr)

   779 {

   780     TCGv tmp;

   781 

   782     s->is_jmp = DISAS_UPDATE;

   783     tmp = new_tmp();

   784     if (s->thumb != (addr & 1)) {

   785         tcg_gen_movi_i32(tmp, addr & 1);

   786         tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));

   787     }

   788     tcg_gen_movi_i32(tmp, addr & ~1);

   789     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[15]));

   790     dead_tmp(tmp);

   791 }

   792 

   793 /* Set PC and Thumb state from var.  var is marked as dead.  */

   794 static inline void gen_bx(DisasContext *s, TCGv var)

   795 {

   796     TCGv tmp;

   797 

   798     s->is_jmp = DISAS_UPDATE;

   799     tmp = new_tmp();

   800     tcg_gen_andi_i32(tmp, var, 1);

   801     store_cpu_field(tmp, thumb);

   802     tcg_gen_andi_i32(var, var, ~1);

   803     store_cpu_field(var, regs[15]);

   804 }

   805 

   806 /* TODO: This should be removed.  Use gen_bx instead.  */

   807 static inline void gen_bx_T0(DisasContext *s)

   808 {

   809     TCGv tmp = new_tmp();

   810     tcg_gen_mov_i32(tmp, cpu_T[0]);

   811     gen_bx(s, tmp);

   812 }

   813 

   814 static inline TCGv gen_ld8s(TCGv addr, int index)

   815 {

   816     TCGv tmp = new_tmp();

   817     tcg_gen_qemu_ld8s(tmp, addr, index);

   818     return tmp;

   819 }

   820 static inline TCGv gen_ld8u(TCGv addr, int index)

   821 {

   822     TCGv tmp = new_tmp();

   823     tcg_gen_qemu_ld8u(tmp, addr, index);

   824     return tmp;

   825 }

   826 static inline TCGv gen_ld16s(TCGv addr, int index)

   827 {

   828     TCGv tmp = new_tmp();

   829     tcg_gen_qemu_ld16s(tmp, addr, index);

   830     return tmp;

   831 }

   832 static inline TCGv gen_ld16u(TCGv addr, int index)

   833 {

   834     TCGv tmp = new_tmp();

   835     tcg_gen_qemu_ld16u(tmp, addr, index);

   836     return tmp;

   837 }

   838 static inline TCGv gen_ld32(TCGv addr, int index)

   839 {

   840     TCGv tmp = new_tmp();

   841     tcg_gen_qemu_ld32u(tmp, addr, index);

   842     return tmp;

   843 }

   844 static inline void gen_st8(TCGv val, TCGv addr, int index)

   845 {

   846     tcg_gen_qemu_st8(val, addr, index);

   847     dead_tmp(val);

   848 }

   849 static inline void gen_st16(TCGv val, TCGv addr, int index)

   850 {

   851     tcg_gen_qemu_st16(val, addr, index);

   852     dead_tmp(val);

   853 }

   854 static inline void gen_st32(TCGv val, TCGv addr, int index)

   855 {

   856     tcg_gen_qemu_st32(val, addr, index);

   857     dead_tmp(val);

   858 }

   859 

   860 static inline void gen_movl_T0_reg(DisasContext *s, int reg)

   861 {

   862     load_reg_var(s, cpu_T[0], reg);

   863 }

   864 

   865 static inline void gen_movl_T1_reg(DisasContext *s, int reg)

   866 {

   867     load_reg_var(s, cpu_T[1], reg);

   868 }

   869 

   870 static inline void gen_movl_T2_reg(DisasContext *s, int reg)

   871 {

   872     load_reg_var(s, cpu_T[2], reg);

   873 }

   874 

   875 static inline void gen_set_pc_im(uint32_t val)

   876 {

   877     TCGv tmp = new_tmp();

   878     tcg_gen_movi_i32(tmp, val);

   879     store_cpu_field(tmp, regs[15]);

   880 }

   881 

   882 static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)

   883 {

   884     TCGv tmp;

   885     if (reg == 15) {

   886         tmp = new_tmp();

   887         tcg_gen_andi_i32(tmp, cpu_T[t], ~1);

   888     } else {

   889         tmp = cpu_T[t];

   890     }

   891     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[reg]));

   892     if (reg == 15) {

   893         dead_tmp(tmp);

   894         s->is_jmp = DISAS_JUMP;

   895     }

   896 }

   897 

   898 static inline void gen_movl_reg_T0(DisasContext *s, int reg)

   899 {

   900     gen_movl_reg_TN(s, reg, 0);

   901 }

   902 

   903 static inline void gen_movl_reg_T1(DisasContext *s, int reg)

   904 {

   905     gen_movl_reg_TN(s, reg, 1);

   906 }

   907 

   908 /* Force a TB lookup after an instruction that changes the CPU state.  */

   909 static inline void gen_lookup_tb(DisasContext *s)

   910 {

   911     gen_op_movl_T0_im(s->pc);

   912     gen_movl_reg_T0(s, 15);

   913     s->is_jmp = DISAS_UPDATE;

   914 }

   915 

   916 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,

   917                                        TCGv var)

   918 {

   919     int val, rm, shift, shiftop;

   920     TCGv offset;

   921 

   922     if (!(insn & (1 << 25))) {

   923         /* immediate */

   924         val = insn & 0xfff;

   925         if (!(insn & (1 << 23)))

   926             val = -val;

   927         if (val != 0)

   928             tcg_gen_addi_i32(var, var, val);

   929     } else {

   930         /* shift/register */

   931         rm = (insn) & 0xf;

   932         shift = (insn >> 7) & 0x1f;

   933         shiftop = (insn >> 5) & 3;

   934         offset = load_reg(s, rm);

   935         gen_arm_shift_im(offset, shiftop, shift, 0);

   936         if (!(insn & (1 << 23)))

   937             tcg_gen_sub_i32(var, var, offset);

   938         else

   939             tcg_gen_add_i32(var, var, offset);

   940         dead_tmp(offset);

   941     }

   942 }

   943 

   944 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,

   945                                         int extra, TCGv var)

   946 {

   947     int val, rm;

   948     TCGv offset;

   949 

   950     if (insn & (1 << 22)) {

   951         /* immediate */

   952         val = (insn & 0xf) | ((insn >> 4) & 0xf0);

   953         if (!(insn & (1 << 23)))

   954             val = -val;

   955         val += extra;

   956         if (val != 0)

   957             tcg_gen_addi_i32(var, var, val);

   958     } else {

   959         /* register */

   960         if (extra)

   961             tcg_gen_addi_i32(var, var, extra);

   962         rm = (insn) & 0xf;

   963         offset = load_reg(s, rm);

   964         if (!(insn & (1 << 23)))

   965             tcg_gen_sub_i32(var, var, offset);

   966         else

   967             tcg_gen_add_i32(var, var, offset);

   968         dead_tmp(offset);

   969     }

   970 }

   971 

   972 #define VFP_OP2(name)                                                 \

   973 static inline void gen_vfp_##name(int dp)                             \

   974 {                                                                     \

   975     if (dp)                                                           \

   976         gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \

   977     else                                                              \

   978         gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \

   979 }

   980 

   981 VFP_OP2(add)

   982 VFP_OP2(sub)

   983 VFP_OP2(mul)

   984 VFP_OP2(div)

   985 

   986 #undef VFP_OP2

   987 

   988 static inline void gen_vfp_abs(int dp)

   989 {

   990     if (dp)

   991         gen_helper_vfp_absd(cpu_F0d, cpu_F0d);

   992     else

   993         gen_helper_vfp_abss(cpu_F0s, cpu_F0s);

   994 }

   995 

   996 static inline void gen_vfp_neg(int dp)

   997 {

   998     if (dp)

   999         gen_helper_vfp_negd(cpu_F0d, cpu_F0d);

  1000     else

  1001         gen_helper_vfp_negs(cpu_F0s, cpu_F0s);

  1002 }

  1003 

  1004 static inline void gen_vfp_sqrt(int dp)

  1005 {

  1006     if (dp)

  1007         gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);

  1008     else

  1009         gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);

  1010 }

  1011 

  1012 static inline void gen_vfp_cmp(int dp)

  1013 {

  1014     if (dp)

  1015         gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);

  1016     else

  1017         gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);

  1018 }

  1019 

  1020 static inline void gen_vfp_cmpe(int dp)

  1021 {

  1022     if (dp)

  1023         gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);

  1024     else

  1025         gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);

  1026 }

  1027 

  1028 static inline void gen_vfp_F1_ld0(int dp)

  1029 {

  1030     if (dp)

  1031         tcg_gen_movi_i64(cpu_F1d, 0);

  1032     else

  1033         tcg_gen_movi_i32(cpu_F1s, 0);

  1034 }

  1035 

  1036 static inline void gen_vfp_uito(int dp)

  1037 {

  1038     if (dp)

  1039         gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);

  1040     else

  1041         gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);

  1042 }

  1043 

  1044 static inline void gen_vfp_sito(int dp)

  1045 {

  1046     if (dp)

  1047         gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);

  1048     else

  1049         gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);

  1050 }

  1051 

  1052 static inline void gen_vfp_toui(int dp)

  1053 {

  1054     if (dp)

  1055         gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);

  1056     else

  1057         gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);

  1058 }

  1059 

  1060 static inline void gen_vfp_touiz(int dp)

  1061 {

  1062     if (dp)

  1063         gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);

  1064     else

  1065         gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);

  1066 }

  1067 

  1068 static inline void gen_vfp_tosi(int dp)

  1069 {

  1070     if (dp)

  1071         gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);

  1072     else

  1073         gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);

  1074 }

  1075 

  1076 static inline void gen_vfp_tosiz(int dp)

  1077 {

  1078     if (dp)

  1079         gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);

  1080     else

  1081         gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);

  1082 }

  1083 

  1084 #define VFP_GEN_FIX(name) \

  1085 static inline void gen_vfp_##name(int dp, int shift) \

  1086 { \

  1087     if (dp) \

  1088         gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tcg_const_i32(shift), cpu_env);\

  1089     else \

  1090         gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tcg_const_i32(shift), cpu_env);\

  1091 }

  1092 VFP_GEN_FIX(tosh)

  1093 VFP_GEN_FIX(tosl)

  1094 VFP_GEN_FIX(touh)

  1095 VFP_GEN_FIX(toul)

  1096 VFP_GEN_FIX(shto)

  1097 VFP_GEN_FIX(slto)

  1098 VFP_GEN_FIX(uhto)

  1099 VFP_GEN_FIX(ulto)

  1100 #undef VFP_GEN_FIX

  1101 

  1102 static inline void gen_vfp_ld(DisasContext *s, int dp)

  1103 {

  1104     if (dp) {

  1105         /* VFP memory accesses only require word alignment, so split

  1106            doubleword accesses.  */

  1107         TCGv low = new_tmp();

  1108         TCGv high = new_tmp();

  1109         tcg_gen_qemu_ld32u(low, cpu_T[1], IS_USER(s));

  1110         tcg_gen_addi_i32(high, cpu_T[1], 4);

  1111         tcg_gen_qemu_ld32u(high, high, IS_USER(s));

  1112         tcg_gen_concat_i32_i64(cpu_F0d, low, high);

  1113         dead_tmp(high);

  1114         dead_tmp(low);

  1115     } else {

  1116         tcg_gen_qemu_ld32u(cpu_F0s, cpu_T[1], IS_USER(s));

  1117     }

  1118 }

  1119 

  1120 static inline void gen_vfp_st(DisasContext *s, int dp)

  1121 {

  1122     if (dp) {

  1123         /* VFP memory accesses only require word alignment, so split

  1124            doubleword accesses.  */

  1125         TCGv val = new_tmp();

  1126         TCGv addr = new_tmp();

  1127         tcg_gen_trunc_i64_i32(val, cpu_F0d);

  1128         tcg_gen_qemu_st32(val, cpu_T[1], IS_USER(s));

  1129         tcg_gen_addi_i32(addr, cpu_T[1], 4);

  1130         tcg_gen_shri_i64(cpu_F0d, cpu_F0d, 32);

  1131         tcg_gen_trunc_i64_i32(val, cpu_F0d);

  1132         tcg_gen_qemu_st32(val, addr, IS_USER(s));

  1133         dead_tmp(addr);

  1134         dead_tmp(val);