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1 /* |
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2 * CRIS virtual CPU header |
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3 * |
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4 * Copyright (c) 2007 AXIS Communications AB |
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5 * Written by Edgar E. Iglesias |
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6 * |
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7 * This library is free software; you can redistribute it and/or |
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8 * modify it under the terms of the GNU Lesser General Public |
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9 * License as published by the Free Software Foundation; either |
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10 * version 2 of the License, or (at your option) any later version. |
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11 * |
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12 * This library is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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15 * General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU Lesser General Public |
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18 * License along with this library; if not, write to the Free Software |
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19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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20 */ |
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21 #ifndef CPU_CRIS_H |
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22 #define CPU_CRIS_H |
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23 |
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24 #define TARGET_LONG_BITS 32 |
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25 |
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26 #include "cpu-defs.h" |
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27 |
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28 #define TARGET_HAS_ICE 1 |
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29 |
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30 #define ELF_MACHINE EM_CRIS |
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31 |
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32 #define EXCP_NMI 1 |
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33 #define EXCP_GURU 2 |
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34 #define EXCP_BUSFAULT 3 |
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35 #define EXCP_IRQ 4 |
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36 #define EXCP_BREAK 5 |
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37 |
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38 /* Register aliases. R0 - R15 */ |
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39 #define R_FP 8 |
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40 #define R_SP 14 |
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41 #define R_ACR 15 |
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42 |
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43 /* Support regs, P0 - P15 */ |
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44 #define PR_BZ 0 |
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45 #define PR_VR 1 |
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46 #define PR_PID 2 |
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47 #define PR_SRS 3 |
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48 #define PR_WZ 4 |
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49 #define PR_EXS 5 |
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50 #define PR_EDA 6 |
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51 #define PR_MOF 7 |
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52 #define PR_DZ 8 |
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53 #define PR_EBP 9 |
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54 #define PR_ERP 10 |
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55 #define PR_SRP 11 |
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56 #define PR_NRP 12 |
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57 #define PR_CCS 13 |
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58 #define PR_USP 14 |
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59 #define PR_SPC 15 |
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60 |
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61 /* CPU flags. */ |
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62 #define Q_FLAG 0x80000000 |
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63 #define M_FLAG 0x40000000 |
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64 #define S_FLAG 0x200 |
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65 #define R_FLAG 0x100 |
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66 #define P_FLAG 0x80 |
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67 #define U_FLAG 0x40 |
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68 #define P_FLAG 0x80 |
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69 #define U_FLAG 0x40 |
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70 #define I_FLAG 0x20 |
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71 #define X_FLAG 0x10 |
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72 #define N_FLAG 0x08 |
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73 #define Z_FLAG 0x04 |
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74 #define V_FLAG 0x02 |
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75 #define C_FLAG 0x01 |
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76 #define ALU_FLAGS 0x1F |
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77 |
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78 /* Condition codes. */ |
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79 #define CC_CC 0 |
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80 #define CC_CS 1 |
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81 #define CC_NE 2 |
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82 #define CC_EQ 3 |
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83 #define CC_VC 4 |
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84 #define CC_VS 5 |
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85 #define CC_PL 6 |
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86 #define CC_MI 7 |
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87 #define CC_LS 8 |
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88 #define CC_HI 9 |
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89 #define CC_GE 10 |
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90 #define CC_LT 11 |
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91 #define CC_GT 12 |
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92 #define CC_LE 13 |
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93 #define CC_A 14 |
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94 #define CC_P 15 |
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95 |
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96 /* Internal flags for the implementation. */ |
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97 #define F_DELAYSLOT 1 |
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98 |
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99 #define NB_MMU_MODES 2 |
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100 |
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101 typedef struct CPUCRISState { |
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102 uint32_t regs[16]; |
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103 /* P0 - P15 are referred to as special registers in the docs. */ |
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104 uint32_t pregs[16]; |
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105 |
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106 /* Pseudo register for the PC. Not directly accessable on CRIS. */ |
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107 uint32_t pc; |
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108 |
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109 /* Pseudo register for the kernel stack. */ |
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110 uint32_t ksp; |
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111 |
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112 /* Branch. */ |
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113 int dslot; |
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114 int btaken; |
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115 uint32_t btarget; |
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116 |
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117 /* Condition flag tracking. */ |
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118 uint32_t cc_op; |
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119 uint32_t cc_mask; |
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120 uint32_t cc_dest; |
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121 uint32_t cc_src; |
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122 uint32_t cc_result; |
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123 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */ |
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124 int cc_size; |
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125 /* X flag at the time of cc snapshot. */ |
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126 int cc_x; |
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127 |
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128 int interrupt_vector; |
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129 int fault_vector; |
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130 int trap_vector; |
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131 |
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132 /* FIXME: add a check in the translator to avoid writing to support |
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133 register sets beyond the 4th. The ISA allows up to 256! but in |
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134 practice there is no core that implements more than 4. |
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135 |
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136 Support function registers are used to control units close to the |
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137 core. Accesses do not pass down the normal hierarchy. |
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138 */ |
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139 uint32_t sregs[4][16]; |
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140 |
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141 /* Linear feedback shift reg in the mmu. Used to provide pseudo |
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142 randomness for the 'hint' the mmu gives to sw for chosing valid |
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143 sets on TLB refills. */ |
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144 uint32_t mmu_rand_lfsr; |
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145 |
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146 /* |
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147 * We just store the stores to the tlbset here for later evaluation |
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148 * when the hw needs access to them. |
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149 * |
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150 * One for I and another for D. |
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151 */ |
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152 struct |
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153 { |
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154 uint32_t hi; |
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155 uint32_t lo; |
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156 } tlbsets[2][4][16]; |
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157 |
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158 CPU_COMMON |
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159 } CPUCRISState; |
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160 |
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161 CPUCRISState *cpu_cris_init(const char *cpu_model); |
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162 int cpu_cris_exec(CPUCRISState *s); |
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163 void cpu_cris_close(CPUCRISState *s); |
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164 void do_interrupt(CPUCRISState *env); |
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165 /* you can call this signal handler from your SIGBUS and SIGSEGV |
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166 signal handlers to inform the virtual CPU of exceptions. non zero |
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167 is returned if the signal was handled by the virtual CPU. */ |
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168 int cpu_cris_signal_handler(int host_signum, void *pinfo, |
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169 void *puc); |
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170 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
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171 int is_asi, int size); |
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172 |
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173 enum { |
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174 CC_OP_DYNAMIC, /* Use env->cc_op */ |
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175 CC_OP_FLAGS, |
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176 CC_OP_CMP, |
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177 CC_OP_MOVE, |
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178 CC_OP_ADD, |
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179 CC_OP_ADDC, |
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180 CC_OP_MCP, |
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181 CC_OP_ADDU, |
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182 CC_OP_SUB, |
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183 CC_OP_SUBU, |
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184 CC_OP_NEG, |
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185 CC_OP_BTST, |
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186 CC_OP_MULS, |
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187 CC_OP_MULU, |
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188 CC_OP_DSTEP, |
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189 CC_OP_BOUND, |
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190 |
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191 CC_OP_OR, |
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192 CC_OP_AND, |
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193 CC_OP_XOR, |
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194 CC_OP_LSL, |
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195 CC_OP_LSR, |
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196 CC_OP_ASR, |
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197 CC_OP_LZ |
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198 }; |
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199 |
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200 /* CRIS uses 8k pages. */ |
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201 #define TARGET_PAGE_BITS 13 |
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202 #define MMAP_SHIFT TARGET_PAGE_BITS |
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203 |
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204 #define CPUState CPUCRISState |
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205 #define cpu_init cpu_cris_init |
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206 #define cpu_exec cpu_cris_exec |
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207 #define cpu_gen_code cpu_cris_gen_code |
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208 #define cpu_signal_handler cpu_cris_signal_handler |
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209 |
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210 #define CPU_SAVE_VERSION 1 |
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211 |
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212 /* MMU modes definitions */ |
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213 #define MMU_MODE0_SUFFIX _kernel |
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214 #define MMU_MODE1_SUFFIX _user |
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215 #define MMU_USER_IDX 1 |
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216 static inline int cpu_mmu_index (CPUState *env) |
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217 { |
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218 return !!(env->pregs[PR_CCS] & U_FLAG); |
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219 } |
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220 |
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221 #if defined(CONFIG_USER_ONLY) |
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222 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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223 { |
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224 if (newsp) |
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225 env->regs[14] = newsp; |
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226 env->regs[10] = 0; |
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227 } |
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228 #endif |
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229 |
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230 /* Support function regs. */ |
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231 #define SFR_RW_GC_CFG 0][0 |
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232 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 |
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233 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1 |
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234 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2 |
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235 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3 |
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236 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4 |
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237 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 |
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238 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 |
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239 |
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240 #include "cpu-all.h" |
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241 #include "exec-all.h" |
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242 |
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243 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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244 { |
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245 env->pc = tb->pc; |
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246 } |
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247 |
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248 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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249 target_ulong *cs_base, int *flags) |
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250 { |
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251 *pc = env->pc; |
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252 *cs_base = 0; |
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253 *flags = env->dslot | |
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254 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG)); |
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255 } |
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256 |
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257 #endif |