1 /*

     2  *  CRIS emulation for qemu: main translation routines.

     3  *

     4  *  Copyright (c) 2008 AXIS Communications AB

     5  *  Written by Edgar E. Iglesias.

     6  *

     7  * This library is free software; you can redistribute it and/or

     8  * modify it under the terms of the GNU Lesser General Public

     9  * License as published by the Free Software Foundation; either

    10  * version 2 of the License, or (at your option) any later version.

    11  *

    12  * This library is distributed in the hope that it will be useful,

    13  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    15  * Lesser General Public License for more details.

    16  *

    17  * You should have received a copy of the GNU Lesser General Public

    18  * License along with this library; if not, write to the Free Software

    19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    20  */

    21 

    22 /*

    23  * FIXME:

    24  * The condition code translation is in need of attention.

    25  */

    26 

    27 #include <stdarg.h>

    28 #include <stdlib.h>

    29 #include <stdio.h>

    30 #include <string.h>

    31 #include <inttypes.h>

    32 #include <assert.h>

    33 

    34 #include "cpu.h"

    35 #include "exec-all.h"

    36 #include "disas.h"

    37 #include "tcg-op.h"

    38 #include "helper.h"

    39 #include "crisv32-decode.h"

    40 #include "qemu-common.h"

    41 

    42 #define GEN_HELPER 1

    43 #include "helper.h"

    44 

    45 #define DISAS_CRIS 0

    46 #if DISAS_CRIS

    47 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x

    48 #else

    49 #define DIS(x)

    50 #endif

    51 

    52 #define D(x)

    53 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))

    54 #define BUG_ON(x) ({if (x) BUG();})

    55 

    56 #define DISAS_SWI 5

    57 

    58 /* Used by the decoder.  */

    59 #define EXTRACT_FIELD(src, start, end) \

    60             (((src) >> start) & ((1 << (end - start + 1)) - 1))

    61 

    62 #define CC_MASK_NZ 0xc

    63 #define CC_MASK_NZV 0xe

    64 #define CC_MASK_NZVC 0xf

    65 #define CC_MASK_RNZV 0x10e

    66 

    67 static TCGv_ptr cpu_env;

    68 static TCGv cpu_R[16];

    69 static TCGv cpu_PR[16];

    70 static TCGv cc_x;

    71 static TCGv cc_src;

    72 static TCGv cc_dest;

    73 static TCGv cc_result;

    74 static TCGv cc_op;

    75 static TCGv cc_size;

    76 static TCGv cc_mask;

    77 

    78 static TCGv env_btaken;

    79 static TCGv env_btarget;

    80 static TCGv env_pc;

    81 

    82 #include "gen-icount.h"

    83 

    84 /* This is the state at translation time.  */

    85 typedef struct DisasContext {

    86 	CPUState *env;

    87 	target_ulong pc, ppc;

    88 

    89 	/* Decoder.  */

    90 	uint32_t ir;

    91 	uint32_t opcode;

    92 	unsigned int op1;

    93 	unsigned int op2;

    94 	unsigned int zsize, zzsize;

    95 	unsigned int mode;

    96 	unsigned int postinc;

    97 

    98 	int update_cc;

    99 	int cc_op;

   100 	int cc_size;

   101 	uint32_t cc_mask;

   102 

   103 	int cc_size_uptodate; /* -1 invalid or last written value.  */

   104 

   105 	int cc_x_uptodate;  /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate.  */

   106 	int flags_uptodate; /* Wether or not $ccs is uptodate.  */

   107 	int flagx_known; /* Wether or not flags_x has the x flag known at

   108 			    translation time.  */

   109 	int flags_x;

   110 

   111 	int clear_x; /* Clear x after this insn?  */

   112 	int cpustate_changed;

   113 	unsigned int tb_flags; /* tb dependent flags.  */

   114 	int is_jmp;

   115 

   116 #define JMP_NOJMP    0

   117 #define JMP_DIRECT   1

   118 #define JMP_INDIRECT 2

   119 	int jmp; /* 0=nojmp, 1=direct, 2=indirect.  */ 

   120 	uint32_t jmp_pc;

   121 

   122 	int delayed_branch;

   123 

   124 	struct TranslationBlock *tb;

   125 	int singlestep_enabled;

   126 } DisasContext;

   127 

   128 static void gen_BUG(DisasContext *dc, const char *file, int line)

   129 {

   130 	printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);

   131 	fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);

   132 	cpu_abort(dc->env, "%s:%d\n", file, line);

   133 }

   134 

   135 static const char *regnames[] =

   136 {

   137 	"$r0", "$r1", "$r2", "$r3",

   138 	"$r4", "$r5", "$r6", "$r7",

   139 	"$r8", "$r9", "$r10", "$r11",

   140 	"$r12", "$r13", "$sp", "$acr",

   141 };

   142 static const char *pregnames[] =

   143 {

   144 	"$bz", "$vr", "$pid", "$srs",

   145 	"$wz", "$exs", "$eda", "$mof",

   146 	"$dz", "$ebp", "$erp", "$srp",

   147 	"$nrp", "$ccs", "$usp", "$spc",

   148 };

   149 

   150 /* We need this table to handle preg-moves with implicit width.  */

   151 static int preg_sizes[] = {

   152 	1, /* bz.  */

   153 	1, /* vr.  */

   154 	4, /* pid.  */

   155 	1, /* srs.  */

   156 	2, /* wz.  */

   157 	4, 4, 4,

   158 	4, 4, 4, 4,

   159 	4, 4, 4, 4,

   160 };

   161 

   162 #define t_gen_mov_TN_env(tn, member) \

   163  _t_gen_mov_TN_env((tn), offsetof(CPUState, member))

   164 #define t_gen_mov_env_TN(member, tn) \

   165  _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))

   166 

   167 static inline void t_gen_mov_TN_reg(TCGv tn, int r)

   168 {

   169 	if (r < 0 || r > 15)

   170 		fprintf(stderr, "wrong register read $r%d\n", r);

   171 	tcg_gen_mov_tl(tn, cpu_R[r]);

   172 }

   173 static inline void t_gen_mov_reg_TN(int r, TCGv tn)

   174 {

   175 	if (r < 0 || r > 15)

   176 		fprintf(stderr, "wrong register write $r%d\n", r);

   177 	tcg_gen_mov_tl(cpu_R[r], tn);

   178 }

   179 

   180 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)

   181 {

   182 	if (offset > sizeof (CPUState))

   183 		fprintf(stderr, "wrong load from env from off=%d\n", offset);

   184 	tcg_gen_ld_tl(tn, cpu_env, offset);

   185 }

   186 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)

   187 {

   188 	if (offset > sizeof (CPUState))

   189 		fprintf(stderr, "wrong store to env at off=%d\n", offset);

   190 	tcg_gen_st_tl(tn, cpu_env, offset);

   191 }

   192 

   193 static inline void t_gen_mov_TN_preg(TCGv tn, int r)

   194 {

   195 	if (r < 0 || r > 15)

   196 		fprintf(stderr, "wrong register read $p%d\n", r);

   197 	if (r == PR_BZ || r == PR_WZ || r == PR_DZ)

   198 		tcg_gen_mov_tl(tn, tcg_const_tl(0));

   199 	else if (r == PR_VR)

   200 		tcg_gen_mov_tl(tn, tcg_const_tl(32));

   201 	else if (r == PR_EDA) {

   202 		printf("read from EDA!\n");

   203 		tcg_gen_mov_tl(tn, cpu_PR[r]);

   204 	}

   205 	else

   206 		tcg_gen_mov_tl(tn, cpu_PR[r]);

   207 }

   208 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)

   209 {

   210 	if (r < 0 || r > 15)

   211 		fprintf(stderr, "wrong register write $p%d\n", r);

   212 	if (r == PR_BZ || r == PR_WZ || r == PR_DZ)

   213 		return;

   214 	else if (r == PR_SRS)

   215 		tcg_gen_andi_tl(cpu_PR[r], tn, 3);

   216 	else {

   217 		if (r == PR_PID) 

   218 			gen_helper_tlb_flush_pid(tn);

   219 		if (dc->tb_flags & S_FLAG && r == PR_SPC) 

   220 			gen_helper_spc_write(tn);

   221 		else if (r == PR_CCS)

   222 			dc->cpustate_changed = 1;

   223 		tcg_gen_mov_tl(cpu_PR[r], tn);

   224 	}

   225 }

   226 

   227 static inline void t_gen_raise_exception(uint32_t index)

   228 {

   229         TCGv_i32 tmp = tcg_const_i32(index);

   230 	gen_helper_raise_exception(tmp);

   231         tcg_temp_free_i32(tmp);

   232 }

   233 

   234 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)

   235 {

   236 	TCGv t0, t_31;

   237 

   238 	t0 = tcg_temp_new();

   239 	t_31 = tcg_const_tl(31);

   240 	tcg_gen_shl_tl(d, a, b);

   241 

   242 	tcg_gen_sub_tl(t0, t_31, b);

   243 	tcg_gen_sar_tl(t0, t0, t_31);

   244 	tcg_gen_and_tl(t0, t0, d);

   245 	tcg_gen_xor_tl(d, d, t0);

   246 	tcg_temp_free(t0);

   247 	tcg_temp_free(t_31);

   248 }

   249 

   250 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)

   251 {

   252 	TCGv t0, t_31;

   253 

   254 	t0 = tcg_temp_new();

   255 	t_31 = tcg_temp_new();

   256 	tcg_gen_shr_tl(d, a, b);

   257 

   258 	tcg_gen_movi_tl(t_31, 31);

   259 	tcg_gen_sub_tl(t0, t_31, b);

   260 	tcg_gen_sar_tl(t0, t0, t_31);

   261 	tcg_gen_and_tl(t0, t0, d);

   262 	tcg_gen_xor_tl(d, d, t0);

   263 	tcg_temp_free(t0);

   264 	tcg_temp_free(t_31);

   265 }

   266 

   267 static void t_gen_asr(TCGv d, TCGv a, TCGv b)

   268 {

   269 	TCGv t0, t_31;

   270 

   271 	t0 = tcg_temp_new();

   272 	t_31 = tcg_temp_new();

   273 	tcg_gen_sar_tl(d, a, b);

   274 

   275 	tcg_gen_movi_tl(t_31, 31);

   276 	tcg_gen_sub_tl(t0, t_31, b);

   277 	tcg_gen_sar_tl(t0, t0, t_31);

   278 	tcg_gen_or_tl(d, d, t0);

   279 	tcg_temp_free(t0);

   280 	tcg_temp_free(t_31);

   281 }

   282 

   283 /* 64-bit signed mul, lower result in d and upper in d2.  */

   284 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)

   285 {

   286 	TCGv_i64 t0, t1;

   287 

   288 	t0 = tcg_temp_new_i64();

   289 	t1 = tcg_temp_new_i64();

   290 

   291 	tcg_gen_ext_i32_i64(t0, a);

   292 	tcg_gen_ext_i32_i64(t1, b);

   293 	tcg_gen_mul_i64(t0, t0, t1);

   294 

   295 	tcg_gen_trunc_i64_i32(d, t0);

   296 	tcg_gen_shri_i64(t0, t0, 32);

   297 	tcg_gen_trunc_i64_i32(d2, t0);

   298 

   299 	tcg_temp_free_i64(t0);

   300 	tcg_temp_free_i64(t1);

   301 }

   302 

   303 /* 64-bit unsigned muls, lower result in d and upper in d2.  */

   304 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)

   305 {

   306 	TCGv_i64 t0, t1;

   307 

   308 	t0 = tcg_temp_new_i64();

   309 	t1 = tcg_temp_new_i64();

   310 

   311 	tcg_gen_extu_i32_i64(t0, a);

   312 	tcg_gen_extu_i32_i64(t1, b);

   313 	tcg_gen_mul_i64(t0, t0, t1);

   314 

   315 	tcg_gen_trunc_i64_i32(d, t0);

   316 	tcg_gen_shri_i64(t0, t0, 32);

   317 	tcg_gen_trunc_i64_i32(d2, t0);

   318 

   319 	tcg_temp_free_i64(t0);

   320 	tcg_temp_free_i64(t1);

   321 }

   322 

   323 /* 32bit branch-free binary search for counting leading zeros.  */

   324 static void t_gen_lz_i32(TCGv d, TCGv x)

   325 {

   326 	TCGv_i32 y, m, n;

   327 

   328 	y = tcg_temp_new_i32();

   329 	m = tcg_temp_new_i32();

   330 	n = tcg_temp_new_i32();

   331 

   332 	/* y = -(x >> 16)  */

   333 	tcg_gen_shri_i32(y, x, 16);

   334 	tcg_gen_neg_i32(y, y);

   335 

   336 	/* m = (y >> 16) & 16  */

   337 	tcg_gen_sari_i32(m, y, 16);

   338 	tcg_gen_andi_i32(m, m, 16);

   339 

   340 	/* n = 16 - m  */

   341 	tcg_gen_sub_i32(n, tcg_const_i32(16), m);

   342 	/* x = x >> m  */

   343 	tcg_gen_shr_i32(x, x, m);

   344 

   345 	/* y = x - 0x100  */

   346 	tcg_gen_subi_i32(y, x, 0x100);

   347 	/* m = (y >> 16) & 8  */

   348 	tcg_gen_sari_i32(m, y, 16);

   349 	tcg_gen_andi_i32(m, m, 8);

   350 	/* n = n + m  */

   351 	tcg_gen_add_i32(n, n, m);

   352 	/* x = x << m  */

   353 	tcg_gen_shl_i32(x, x, m);

   354 

   355 	/* y = x - 0x1000  */

   356 	tcg_gen_subi_i32(y, x, 0x1000);

   357 	/* m = (y >> 16) & 4  */

   358 	tcg_gen_sari_i32(m, y, 16);

   359 	tcg_gen_andi_i32(m, m, 4);

   360 	/* n = n + m  */

   361 	tcg_gen_add_i32(n, n, m);

   362 	/* x = x << m  */

   363 	tcg_gen_shl_i32(x, x, m);

   364 

   365 	/* y = x - 0x4000  */

   366 	tcg_gen_subi_i32(y, x, 0x4000);

   367 	/* m = (y >> 16) & 2  */

   368 	tcg_gen_sari_i32(m, y, 16);

   369 	tcg_gen_andi_i32(m, m, 2);

   370 	/* n = n + m  */

   371 	tcg_gen_add_i32(n, n, m);

   372 	/* x = x << m  */

   373 	tcg_gen_shl_i32(x, x, m);

   374 

   375 	/* y = x >> 14  */

   376 	tcg_gen_shri_i32(y, x, 14);

   377 	/* m = y & ~(y >> 1)  */

   378 	tcg_gen_sari_i32(m, y, 1);

   379 	tcg_gen_not_i32(m, m);

   380 	tcg_gen_and_i32(m, m, y);

   381 

   382 	/* d = n + 2 - m  */

   383 	tcg_gen_addi_i32(d, n, 2);

   384 	tcg_gen_sub_i32(d, d, m);

   385 

   386 	tcg_temp_free(y);

   387 	tcg_temp_free(m);

   388 	tcg_temp_free(n);

   389 }

   390 

   391 static void t_gen_btst(TCGv d, TCGv a, TCGv b)

   392 {

   393         TCGv sbit;

   394         TCGv bset;

   395         TCGv t0;

   396 	int l1;

   397 

   398         /* des ref:

   399            The N flag is set according to the selected bit in the dest reg.

   400            The Z flag is set if the selected bit and all bits to the right are

   401            zero.

   402            The X flag is cleared.

   403            Other flags are left untouched.

   404            The destination reg is not affected.

   405 

   406         unsigned int fz, sbit, bset, mask, masked_t0;

   407 

   408         sbit = T1 & 31;

   409         bset = !!(T0 & (1 << sbit));

   410         mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;

   411         masked_t0 = T0 & mask;

   412         fz = !(masked_t0 | bset);

   413 

   414         // Clear the X, N and Z flags.

   415         T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);

   416         // Set the N and Z flags accordingly.

   417         T0 |= (bset << 3) | (fz << 2);

   418         */

   419 

   420 	l1 = gen_new_label();

   421         sbit = tcg_temp_new();

   422         bset = tcg_temp_new();

   423         t0 = tcg_temp_new();

   424 

   425         /* Compute bset and sbit.  */

   426         tcg_gen_andi_tl(sbit, b, 31);

   427         tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);

   428         tcg_gen_and_tl(bset, a, t0);

   429         tcg_gen_shr_tl(bset, bset, sbit);

   430 	/* Displace to N_FLAG.  */

   431         tcg_gen_shli_tl(bset, bset, 3);

   432 

   433         tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);

   434         tcg_gen_subi_tl(sbit, sbit, 1);

   435         tcg_gen_and_tl(sbit, a, sbit);

   436 

   437         tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));

   438 	/* or in the N_FLAG.  */

   439         tcg_gen_or_tl(d, d, bset);

   440 	tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);

   441 	/* or in the Z_FLAG.  */

   442 	tcg_gen_ori_tl(d, d, Z_FLAG);

   443 	gen_set_label(l1);

   444 

   445         tcg_temp_free(sbit);

   446         tcg_temp_free(bset);

   447 }

   448 

   449 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)

   450 {

   451 	int l1;

   452 

   453 	l1 = gen_new_label();

   454 

   455 	/* 

   456 	 * d <<= 1

   457 	 * if (d >= s)

   458 	 *    d -= s;

   459 	 */

   460 	tcg_gen_shli_tl(d, a, 1);

   461 	tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);

   462 	tcg_gen_sub_tl(d, d, b);

   463 	gen_set_label(l1);

   464 }

   465 

   466 /* Extended arithmetics on CRIS.  */

   467 static inline void t_gen_add_flag(TCGv d, int flag)

   468 {

   469 	TCGv c;

   470 

   471 	c = tcg_temp_new();

   472 	t_gen_mov_TN_preg(c, PR_CCS);

   473 	/* Propagate carry into d.  */

   474 	tcg_gen_andi_tl(c, c, 1 << flag);

   475 	if (flag)

   476 		tcg_gen_shri_tl(c, c, flag);

   477 	tcg_gen_add_tl(d, d, c);

   478 	tcg_temp_free(c);

   479 }

   480 

   481 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)

   482 {

   483 	if (dc->flagx_known) {

   484 		if (dc->flags_x) {

   485 			TCGv c;

   486             

   487 			c = tcg_temp_new();

   488 			t_gen_mov_TN_preg(c, PR_CCS);

   489 			/* C flag is already at bit 0.  */

   490 			tcg_gen_andi_tl(c, c, C_FLAG);

   491 			tcg_gen_add_tl(d, d, c);

   492 			tcg_temp_free(c);

   493 		}

   494 	} else {

   495 		TCGv x, c;

   496 

   497 		x = tcg_temp_new();

   498 		c = tcg_temp_new();

   499 		t_gen_mov_TN_preg(x, PR_CCS);

   500 		tcg_gen_mov_tl(c, x);

   501 

   502 		/* Propagate carry into d if X is set. Branch free.  */

   503 		tcg_gen_andi_tl(c, c, C_FLAG);

   504 		tcg_gen_andi_tl(x, x, X_FLAG);

   505 		tcg_gen_shri_tl(x, x, 4);

   506 

   507 		tcg_gen_and_tl(x, x, c);

   508 		tcg_gen_add_tl(d, d, x);        

   509 		tcg_temp_free(x);

   510 		tcg_temp_free(c);

   511 	}

   512 }

   513 

   514 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)

   515 {

   516 	if (dc->flagx_known) {

   517 		if (dc->flags_x) {

   518 			TCGv c;

   519             

   520 			c = tcg_temp_new();

   521 			t_gen_mov_TN_preg(c, PR_CCS);

   522 			/* C flag is already at bit 0.  */

   523 			tcg_gen_andi_tl(c, c, C_FLAG);

   524 			tcg_gen_sub_tl(d, d, c);

   525 			tcg_temp_free(c);

   526 		}

   527 	} else {

   528 		TCGv x, c;

   529 

   530 		x = tcg_temp_new();

   531 		c = tcg_temp_new();

   532 		t_gen_mov_TN_preg(x, PR_CCS);

   533 		tcg_gen_mov_tl(c, x);

   534 

   535 		/* Propagate carry into d if X is set. Branch free.  */

   536 		tcg_gen_andi_tl(c, c, C_FLAG);

   537 		tcg_gen_andi_tl(x, x, X_FLAG);

   538 		tcg_gen_shri_tl(x, x, 4);

   539 

   540 		tcg_gen_and_tl(x, x, c);

   541 		tcg_gen_sub_tl(d, d, x);

   542 		tcg_temp_free(x);

   543 		tcg_temp_free(c);

   544 	}

   545 }

   546 

   547 /* Swap the two bytes within each half word of the s operand.

   548    T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff)  */

   549 static inline void t_gen_swapb(TCGv d, TCGv s)

   550 {

   551 	TCGv t, org_s;

   552 

   553 	t = tcg_temp_new();

   554 	org_s = tcg_temp_new();

   555 

   556 	/* d and s may refer to the same object.  */

   557 	tcg_gen_mov_tl(org_s, s);

   558 	tcg_gen_shli_tl(t, org_s, 8);

   559 	tcg_gen_andi_tl(d, t, 0xff00ff00);

   560 	tcg_gen_shri_tl(t, org_s, 8);

   561 	tcg_gen_andi_tl(t, t, 0x00ff00ff);

   562 	tcg_gen_or_tl(d, d, t);

   563 	tcg_temp_free(t);

   564 	tcg_temp_free(org_s);

   565 }

   566 

   567 /* Swap the halfwords of the s operand.  */

   568 static inline void t_gen_swapw(TCGv d, TCGv s)

   569 {

   570 	TCGv t;

   571 	/* d and s refer the same object.  */

   572 	t = tcg_temp_new();

   573 	tcg_gen_mov_tl(t, s);

   574 	tcg_gen_shli_tl(d, t, 16);

   575 	tcg_gen_shri_tl(t, t, 16);

   576 	tcg_gen_or_tl(d, d, t);

   577 	tcg_temp_free(t);

   578 }

   579 

   580 /* Reverse the within each byte.

   581    T0 = (((T0 << 7) & 0x80808080) |

   582    ((T0 << 5) & 0x40404040) |

   583    ((T0 << 3) & 0x20202020) |

   584    ((T0 << 1) & 0x10101010) |

   585    ((T0 >> 1) & 0x08080808) |

   586    ((T0 >> 3) & 0x04040404) |

   587    ((T0 >> 5) & 0x02020202) |

   588    ((T0 >> 7) & 0x01010101));

   589  */

   590 static inline void t_gen_swapr(TCGv d, TCGv s)

   591 {

   592 	struct {

   593 		int shift; /* LSL when positive, LSR when negative.  */

   594 		uint32_t mask;

   595 	} bitrev [] = {

   596 		{7, 0x80808080},

   597 		{5, 0x40404040},

   598 		{3, 0x20202020},

   599 		{1, 0x10101010},

   600 		{-1, 0x08080808},

   601 		{-3, 0x04040404},

   602 		{-5, 0x02020202},

   603 		{-7, 0x01010101}

   604 	};

   605 	int i;

   606 	TCGv t, org_s;

   607 

   608 	/* d and s refer the same object.  */

   609 	t = tcg_temp_new();

   610 	org_s = tcg_temp_new();

   611 	tcg_gen_mov_tl(org_s, s);

   612 

   613 	tcg_gen_shli_tl(t, org_s,  bitrev[0].shift);

   614 	tcg_gen_andi_tl(d, t,  bitrev[0].mask);

   615 	for (i = 1; i < ARRAY_SIZE(bitrev); i++) {

   616 		if (bitrev[i].shift >= 0) {

   617 			tcg_gen_shli_tl(t, org_s,  bitrev[i].shift);

   618 		} else {

   619 			tcg_gen_shri_tl(t, org_s,  -bitrev[i].shift);

   620 		}

   621 		tcg_gen_andi_tl(t, t,  bitrev[i].mask);

   622 		tcg_gen_or_tl(d, d, t);

   623 	}

   624 	tcg_temp_free(t);

   625 	tcg_temp_free(org_s);

   626 }

   627 

   628 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)

   629 {

   630 	TCGv btaken;

   631 	int l1;

   632 

   633 	l1 = gen_new_label();

   634 	btaken = tcg_temp_new();

   635 

   636 	/* Conditional jmp.  */

   637 	tcg_gen_mov_tl(btaken, env_btaken);

   638 	tcg_gen_mov_tl(env_pc, pc_false);

   639 	tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);

   640 	tcg_gen_mov_tl(env_pc, pc_true);

   641 	gen_set_label(l1);

   642 

   643 	tcg_temp_free(btaken);

   644 }

   645 

   646 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)

   647 {

   648 	TranslationBlock *tb;

   649 	tb = dc->tb;

   650 	if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {

   651 		tcg_gen_goto_tb(n);

   652 		tcg_gen_movi_tl(env_pc, dest);

   653 		tcg_gen_exit_tb((long)tb + n);

   654 	} else {

   655 		tcg_gen_movi_tl(env_pc, dest);

   656 		tcg_gen_exit_tb(0);

   657 	}

   658 }

   659 

   660 /* Sign extend at translation time.  */

   661 static int sign_extend(unsigned int val, unsigned int width)

   662 {

   663 	int sval;

   664 

   665 	/* LSL.  */

   666 	val <<= 31 - width;

   667 	sval = val;

   668 	/* ASR.  */

   669 	sval >>= 31 - width;

   670 	return sval;

   671 }

   672 

   673 static inline void cris_clear_x_flag(DisasContext *dc)

   674 {

   675 	if (dc->flagx_known && dc->flags_x)

   676 		dc->flags_uptodate = 0;

   677 

   678 	dc->flagx_known = 1;

   679 	dc->flags_x = 0;

   680 }

   681 

   682 static void cris_flush_cc_state(DisasContext *dc)

   683 {

   684 	if (dc->cc_size_uptodate != dc->cc_size) {

   685 		tcg_gen_movi_tl(cc_size, dc->cc_size);

   686 		dc->cc_size_uptodate = dc->cc_size;

   687 	}

   688 	tcg_gen_movi_tl(cc_op, dc->cc_op);

   689 	tcg_gen_movi_tl(cc_mask, dc->cc_mask);

   690 }

   691 

   692 static void cris_evaluate_flags(DisasContext *dc)

   693 {

   694 	if (!dc->flags_uptodate) {

   695 		cris_flush_cc_state(dc);

   696 

   697 		switch (dc->cc_op)

   698 		{

   699 			case CC_OP_MCP:

   700 				gen_helper_evaluate_flags_mcp();

   701 				break;

   702 			case CC_OP_MULS:

   703 				gen_helper_evaluate_flags_muls();

   704 				break;

   705 			case CC_OP_MULU:

   706 				gen_helper_evaluate_flags_mulu();

   707 				break;

   708 			case CC_OP_MOVE:

   709 			case CC_OP_AND:

   710 			case CC_OP_OR:

   711 			case CC_OP_XOR:

   712 			case CC_OP_ASR:

   713 			case CC_OP_LSR:

   714 			case CC_OP_LSL:

   715 				switch (dc->cc_size)

   716 				{

   717 					case 4:

   718 						gen_helper_evaluate_flags_move_4();

   719 						break;

   720 					case 2:

   721 						gen_helper_evaluate_flags_move_2();

   722 						break;

   723 					default:

   724 						gen_helper_evaluate_flags();

   725 						break;

   726 				}

   727 				break;

   728 			case CC_OP_FLAGS:

   729 				/* live.  */

   730 				break;

   731 			default:

   732 			{

   733 				switch (dc->cc_size)

   734 				{

   735 					case 4:

   736 						gen_helper_evaluate_flags_alu_4();

   737 						break;

   738 					default:

   739 						gen_helper_evaluate_flags();

   740 						break;

   741 				}

   742 			}

   743 			break;

   744 		}

   745 		if (dc->flagx_known) {

   746 			if (dc->flags_x)

   747 				tcg_gen_ori_tl(cpu_PR[PR_CCS], 

   748 					       cpu_PR[PR_CCS], X_FLAG);

   749 			else

   750 				tcg_gen_andi_tl(cpu_PR[PR_CCS], 

   751 						cpu_PR[PR_CCS], ~X_FLAG);

   752 	        }

   753 

   754 		dc->flags_uptodate = 1;

   755 	}

   756 }

   757 

   758 static void cris_cc_mask(DisasContext *dc, unsigned int mask)

   759 {

   760 	uint32_t ovl;

   761 

   762 	if (!mask) {

   763 		dc->update_cc = 0;

   764 		return;

   765 	}	

   766 

   767 	/* Check if we need to evaluate the condition codes due to 

   768 	   CC overlaying.  */

   769 	ovl = (dc->cc_mask ^ mask) & ~mask;

   770 	if (ovl) {

   771 		/* TODO: optimize this case. It trigs all the time.  */

   772 		cris_evaluate_flags (dc);

   773 	}

   774 	dc->cc_mask = mask;

   775 	dc->update_cc = 1;

   776 }

   777 

   778 static void cris_update_cc_op(DisasContext *dc, int op, int size)

   779 {

   780 	dc->cc_op = op;

   781 	dc->cc_size = size;

   782 	dc->flags_uptodate = 0;

   783 }

   784 

   785 static inline void cris_update_cc_x(DisasContext *dc)

   786 {

   787 	/* Save the x flag state at the time of the cc snapshot.  */

   788 	if (dc->flagx_known) {

   789 		if (dc->cc_x_uptodate == (2 | dc->flags_x))

   790 			return;

   791 		tcg_gen_movi_tl(cc_x, dc->flags_x);

   792 		dc->cc_x_uptodate = 2 | dc->flags_x;

   793 	}

   794 	else {

   795 		tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);

   796 		dc->cc_x_uptodate = 1;

   797 	}

   798 }

   799 

   800 /* Update cc prior to executing ALU op. Needs source operands untouched.  */

   801 static void cris_pre_alu_update_cc(DisasContext *dc, int op, 

   802 				   TCGv dst, TCGv src, int size)

   803 {

   804 	if (dc->update_cc) {

   805 		cris_update_cc_op(dc, op, size);

   806 		tcg_gen_mov_tl(cc_src, src);

   807 

   808 		if (op != CC_OP_MOVE

   809 		    && op != CC_OP_AND

   810 		    && op != CC_OP_OR

   811 		    && op != CC_OP_XOR

   812 		    && op != CC_OP_ASR

   813 		    && op != CC_OP_LSR

   814 		    && op != CC_OP_LSL)

   815 			tcg_gen_mov_tl(cc_dest, dst);

   816 

   817 		cris_update_cc_x(dc);

   818 	}

   819 }

   820 

   821 /* Update cc after executing ALU op. needs the result.  */

   822 static inline void cris_update_result(DisasContext *dc, TCGv res)

   823 {

   824 	if (dc->update_cc) {

   825 		if (dc->cc_size == 4 && 

   826 		    (dc->cc_op == CC_OP_SUB

   827 		     || dc->cc_op == CC_OP_ADD))

   828 			return;

   829 		tcg_gen_mov_tl(cc_result, res);

   830 	}

   831 }

   832 

   833 /* Returns one if the write back stage should execute.  */

   834 static void cris_alu_op_exec(DisasContext *dc, int op, 

   835 			       TCGv dst, TCGv a, TCGv b, int size)

   836 {

   837 	/* Emit the ALU insns.  */

   838 	switch (op)

   839 	{

   840 		case CC_OP_ADD:

   841 			tcg_gen_add_tl(dst, a, b);

   842 			/* Extended arithmetics.  */

   843 			t_gen_addx_carry(dc, dst);

   844 			break;

   845 		case CC_OP_ADDC:

   846 			tcg_gen_add_tl(dst, a, b);

   847 			t_gen_add_flag(dst, 0); /* C_FLAG.  */

   848 			break;

   849 		case CC_OP_MCP:

   850 			tcg_gen_add_tl(dst, a, b);

   851 			t_gen_add_flag(dst, 8); /* R_FLAG.  */

   852 			break;

   853 		case CC_OP_SUB:

   854 			tcg_gen_sub_tl(dst, a, b);

   855 			/* Extended arithmetics.  */

   856 			t_gen_subx_carry(dc, dst);

   857 			break;

   858 		case CC_OP_MOVE:

   859 			tcg_gen_mov_tl(dst, b);

   860 			break;

   861 		case CC_OP_OR:

   862 			tcg_gen_or_tl(dst, a, b);

   863 			break;

   864 		case CC_OP_AND:

   865 			tcg_gen_and_tl(dst, a, b);

   866 			break;

   867 		case CC_OP_XOR:

   868 			tcg_gen_xor_tl(dst, a, b);

   869 			break;

   870 		case CC_OP_LSL:

   871 			t_gen_lsl(dst, a, b);

   872 			break;

   873 		case CC_OP_LSR:

   874 			t_gen_lsr(dst, a, b);

   875 			break;

   876 		case CC_OP_ASR:

   877 			t_gen_asr(dst, a, b);

   878 			break;

   879 		case CC_OP_NEG:

   880 			tcg_gen_neg_tl(dst, b);

   881 			/* Extended arithmetics.  */

   882 			t_gen_subx_carry(dc, dst);

   883 			break;

   884 		case CC_OP_LZ:

   885 			t_gen_lz_i32(dst, b);

   886 			break;

   887 		case CC_OP_BTST:

   888 			t_gen_btst(dst, a, b);

   889 			break;

   890 		case CC_OP_MULS:

   891 			t_gen_muls(dst, cpu_PR[PR_MOF], a, b);

   892 			break;

   893 		case CC_OP_MULU:

   894 			t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);

   895 			break;

   896 		case CC_OP_DSTEP:

   897 			t_gen_cris_dstep(dst, a, b);

   898 			break;

   899 		case CC_OP_BOUND:

   900 		{

   901 			int l1;

   902 			l1 = gen_new_label();

   903 			tcg_gen_mov_tl(dst, a);

   904 			tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);

   905 			tcg_gen_mov_tl(dst, b);

   906 			gen_set_label(l1);

   907 		}

   908 		break;

   909 		case CC_OP_CMP:

   910 			tcg_gen_sub_tl(dst, a, b);

   911 			/* Extended arithmetics.  */

   912 			t_gen_subx_carry(dc, dst);

   913 			break;

   914 		default:

   915 			fprintf (logfile, "illegal ALU op.\n");

   916 			BUG();

   917 			break;

   918 	}

   919 

   920 	if (size == 1)

   921 		tcg_gen_andi_tl(dst, dst, 0xff);

   922 	else if (size == 2)

   923 		tcg_gen_andi_tl(dst, dst, 0xffff);

   924 }

   925 

   926 static void cris_alu(DisasContext *dc, int op,

   927 			       TCGv d, TCGv op_a, TCGv op_b, int size)

   928 {

   929 	TCGv tmp;

   930 	int writeback;

   931 

   932 	writeback = 1;

   933 

   934 	if (op == CC_OP_BOUND || op == CC_OP_BTST)

   935 		tmp = tcg_temp_local_new();

   936 

   937 	if (op == CC_OP_CMP) {

   938 		tmp = tcg_temp_new();

   939 		writeback = 0;

   940 	} else if (size == 4) {

   941 		tmp = d;

   942 		writeback = 0;

   943 	} else

   944 		tmp = tcg_temp_new();

   945 

   946 

   947 	cris_pre_alu_update_cc(dc, op, op_a, op_b, size);

   948 	cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);

   949 	cris_update_result(dc, tmp);

   950 

   951 	/* Writeback.  */

   952 	if (writeback) {

   953 		if (size == 1)

   954 			tcg_gen_andi_tl(d, d, ~0xff);

   955 		else

   956 			tcg_gen_andi_tl(d, d, ~0xffff);

   957 		tcg_gen_or_tl(d, d, tmp);

   958 	}

   959 	if (!TCGV_EQUAL(tmp, d))

   960 		tcg_temp_free(tmp);

   961 }

   962 

   963 static int arith_cc(DisasContext *dc)

   964 {

   965 	if (dc->update_cc) {

   966 		switch (dc->cc_op) {

   967 			case CC_OP_ADDC: return 1;

   968 			case CC_OP_ADD: return 1;

   969 			case CC_OP_SUB: return 1;

   970 			case CC_OP_DSTEP: return 1;

   971 			case CC_OP_LSL: return 1;

   972 			case CC_OP_LSR: return 1;

   973 			case CC_OP_ASR: return 1;

   974 			case CC_OP_CMP: return 1;

   975 			case CC_OP_NEG: return 1;

   976 			case CC_OP_OR: return 1;

   977 			case CC_OP_XOR: return 1;

   978 			case CC_OP_MULU: return 1;

   979 			case CC_OP_MULS: return 1;

   980 			default:

   981 				return 0;

   982 		}

   983 	}

   984 	return 0;

   985 }

   986 

   987 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)

   988 {

   989 	int arith_opt, move_opt;

   990 

   991 	/* TODO: optimize more condition codes.  */

   992 

   993 	/*

   994 	 * If the flags are live, we've gotta look into the bits of CCS.

   995 	 * Otherwise, if we just did an arithmetic operation we try to

   996 	 * evaluate the condition code faster.

   997 	 *

   998 	 * When this function is done, T0 should be non-zero if the condition

   999 	 * code is true.

  1000 	 */

  1001 	arith_opt = arith_cc(dc) && !dc->flags_uptodate;

  1002 	move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;

  1003 	switch (cond) {

  1004 		case CC_EQ:

  1005 			if (arith_opt || move_opt) {

  1006 				/* If cc_result is zero, T0 should be 

  1007 				   non-zero otherwise T0 should be zero.  */

  1008 				int l1;

  1009 				l1 = gen_new_label();

  1010 				tcg_gen_movi_tl(cc, 0);

  1011 				tcg_gen_brcondi_tl(TCG_COND_NE, cc_result, 

  1012 						   0, l1);

  1013 				tcg_gen_movi_tl(cc, 1);

  1014 				gen_set_label(l1);

  1015 			}

  1016 			else {

  1017 				cris_evaluate_flags(dc);

  1018 				tcg_gen_andi_tl(cc, 

  1019 						cpu_PR[PR_CCS], Z_FLAG);

  1020 			}

  1021 			break;

  1022 		case CC_NE:

  1023 			if (arith_opt || move_opt)

  1024 				tcg_gen_mov_tl(cc, cc_result);

  1025 			else {

  1026 				cris_evaluate_flags(dc);

  1027 				tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],

  1028 						Z_FLAG);

  1029 				tcg_gen_andi_tl(cc, cc, Z_FLAG);

  1030 			}

  1031 			break;

  1032 		case CC_CS:

  1033 			cris_evaluate_flags(dc);

  1034 			tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);

  1035 			break;

  1036 		case CC_CC:

  1037 			cris_evaluate_flags(dc);

  1038 			tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);

  1039 			tcg_gen_andi_tl(cc, cc, C_FLAG);

  1040 			break;

  1041 		case CC_VS:

  1042 			cris_evaluate_flags(dc);

  1043 			tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);

  1044 			break;

  1045 		case CC_VC:

  1046 			cris_evaluate_flags(dc);

  1047 			tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],

  1048 					V_FLAG);

  1049 			tcg_gen_andi_tl(cc, cc, V_FLAG);

  1050 			break;

  1051 		case CC_PL:

  1052 			if (arith_opt || move_opt) {

  1053 				int bits = 31;

  1054 

  1055 				if (dc->cc_size == 1)

  1056 					bits = 7;

  1057 				else if (dc->cc_size == 2)

  1058 					bits = 15;	

  1059 

  1060 				tcg_gen_shri_tl(cc, cc_result, bits);

  1061 				tcg_gen_xori_tl(cc, cc, 1);

  1062 			} else {

  1063 				cris_evaluate_flags(dc);

  1064 				tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],

  1065 						N_FLAG);

  1066 				tcg_gen_andi_tl(cc, cc, N_FLAG);

  1067 			}

  1068 			break;

  1069 		case CC_MI:

  1070 			if (arith_opt || move_opt) {

  1071 				int bits = 31;

  1072 

  1073 				if (dc->cc_size == 1)

  1074 					bits = 7;

  1075 				else if (dc->cc_size == 2)

  1076 					bits = 15;	

  1077 

  1078 				tcg_gen_shri_tl(cc, cc_result, 31);

  1079 			}

  1080 			else {

  1081 				cris_evaluate_flags(dc);

  1082 				tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],

  1083 						N_FLAG);

  1084 			}

  1085 			break;

  1086 		case CC_LS:

  1087 			cris_evaluate_flags(dc);

  1088 			tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],

  1089 					C_FLAG | Z_FLAG);

  1090 			break;

  1091 		case CC_HI:

  1092 			cris_evaluate_flags(dc);

  1093 			{

  1094 				TCGv tmp;

  1095 

  1096 				tmp = tcg_temp_new();

  1097 				tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],

  1098 						C_FLAG | Z_FLAG);

  1099 				/* Overlay the C flag on top of the Z.  */

  1100 				tcg_gen_shli_tl(cc, tmp, 2);

  1101 				tcg_gen_and_tl(cc, tmp, cc);

  1102 				tcg_gen_andi_tl(cc, cc, Z_FLAG);

  1103 

  1104 				tcg_temp_free(tmp);

  1105 			}

  1106 			break;

  1107 		case CC_GE:

  1108 			cris_evaluate_flags(dc);

  1109 			/* Overlay the V flag on top of the N.  */

  1110 			tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);

  1111 			tcg_gen_xor_tl(cc,

  1112 				       cpu_PR[PR_CCS], cc);

  1113 			tcg_gen_andi_tl(cc, cc, N_FLAG);

  1114 			tcg_gen_xori_tl(cc, cc, N_FLAG);

  1115 			break;

  1116 		case CC_LT:

  1117 			cris_evaluate_flags(dc);

  1118 			/* Overlay the V flag on top of the N.  */

  1119 			tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);

  1120 			tcg_gen_xor_tl(cc,

  1121 				       cpu_PR[PR_CCS], cc);

  1122 			tcg_gen_andi_tl(cc, cc, N_FLAG);

  1123 			break;

  1124 		case CC_GT:

  1125 			cris_evaluate_flags(dc);

  1126 			{

  1127 				TCGv n, z;

  1128 

  1129 				n = tcg_temp_new();

  1130 				z = tcg_temp_new();

  1131 

  1132 				/* To avoid a shift we overlay everything on

  1133 				   the V flag.  */

  1134 				tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);

  1135 				tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);